WCH-Templates/CH32V00x
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Random whitespace removal

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Logan G 2024-01-05 04:17:16 -07:00
parent 60f272e4a3
commit 7c6505132b
Signed by: logan
GPG key ID: E328528C921E7A7A
3 changed files with 12 additions and 12 deletions
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6
Debug/debug.c
View file

@ -7,7 +7,7 @@
* Printf , Delay functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <debug.h>
@ -167,7 +167,7 @@ void SDI_Printf_Enable(void)
*
* @return size - Data length
*/
__attribute__((used))
__attribute__((used))
int _write(int fd, char *buf, int size)
{
int i = 0;
@ -224,7 +224,7 @@ int _write(int fd, char *buf, int size)
*
* @return size: Data length
*/
__attribute__((used))
__attribute__((used))
void *_sbrk(ptrdiff_t incr)
{
extern char _end[];

2
Debug/debug.h
View file

@ -7,7 +7,7 @@
* Printf , Delay functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __DEBUG_H

16
User/system_ch32v00x.c
View file

@ -9,10 +9,10 @@
*********************************************************************************/
#include <ch32v00x.h>
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source.
* If none of the define below is enabled, the HSI is used as System clock source.
*/
//#define SYSCLK_FREQ_8MHz_HSI 8000000
@ -153,10 +153,10 @@ static void SetSysClock(void)
#elif defined SYSCLK_FREQ_48MHz_HSE
SetSysClockTo_48MHz_HSE();
#endif
/* If none of the define above is enabled, the HSI is used as System clock£¬
* source (default after reset)
*/
* source (default after reset)
*/
}
@ -229,7 +229,7 @@ static void SetSysClockTo_48MHZ_HSI(void)
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
@ -438,4 +438,4 @@ static void SetSysClockTo_48MHz_HSE(void)