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Merge pull request 'Update CH32V003 Template' (#1) from logan/CH32V00x:master into master

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Reviewed-on: #1
This commit is contained in:
Thomas Muller 2024-03-20 23:42:45 -04:00
commit ea84a7326e
42 changed files with 15157 additions and 14504 deletions
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18
CMakeLists.txt
View file

@ -1,11 +1,11 @@
cmake_minimum_required(VERSION 3.10) cmake_minimum_required(VERSION 3.10)
project(main) project(blink)
# set(CMAKE_VERBOSE_MAKEFILE ON) # set(CMAKE_VERBOSE_MAKEFILE ON)
set(CMAKE_C_COMPILER riscv-none-embed-gcc) set(CMAKE_C_COMPILER riscv-none-elf-gcc)
set(CMAKE_CXX_COMPILER riscv-none-embed-gcc) set(CMAKE_CXX_COMPILER riscv-none-elf-gcc)
set(CMAKE_OBJCOPY riscv-none-embed-objcopy) set(CMAKE_OBJCOPY riscv-none-elf-objcopy)
set(CMAKE_SIZE riscv-none-embed-size) set(CMAKE_SIZE riscv-none-elf-size)
set_property(SOURCE Startup/startup_ch32v00x.S PROPERTY LANGUAGE C) set_property(SOURCE Startup/startup_ch32v00x.S PROPERTY LANGUAGE C)
@ -18,7 +18,8 @@ include_directories(Debug)
include_directories(Core) include_directories(Core)
include_directories(User) include_directories(User)
include_directories(Peripheral/inc) include_directories(Peripheral/inc)
add_definitions(-march=rv32ec -mabi=ilp32e -msmall-data-limit=0 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common)
add_definitions(-Wall -Wextra -march=rv32ec_zicsr -mabi=ilp32e -msmall-data-limit=0 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common)
file(GLOB SOURCES "Debug/*.c" "Core/*.c" "User/*.c" "Peripheral/src/*.c" "Startup/*.S") file(GLOB SOURCES "Debug/*.c" "Core/*.c" "User/*.c" "Peripheral/src/*.c" "Startup/*.S")
@ -31,5 +32,6 @@ add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}.siz
COMMAND ${CMAKE_SIZE} COMMAND ${CMAKE_SIZE}
ARGS --format=berkeley ${CMAKE_PROJECT_NAME}.elf) ARGS --format=berkeley ${CMAKE_PROJECT_NAME}.elf)
add_executable(${CMAKE_PROJECT_NAME}.elf ${SOURCES} ${CMAKE_PROJECT_NAME}.hex ${CMAKE_PROJECT_NAME}.siz) add_executable(${CMAKE_PROJECT_NAME}.elf ${SOURCES})
target_link_options(${CMAKE_PROJECT_NAME}.elf PRIVATE -T ${CMAKE_SOURCE_DIR}/Ld/Link.ld -march=rv32ec -mabi=ilp32e -nostartfiles -Xlinker -gc-sections --specs=nano.specs --specs=nosys.specs)
target_link_options(${CMAKE_PROJECT_NAME}.elf PRIVATE -T ${CMAKE_SOURCE_DIR}/Ld/Link.ld -march=rv32ec_zicsr -mabi=ilp32e -nostartfiles -Xlinker -gc-sections --specs=nano.specs --specs=nosys.specs -mcmodel=medany)

550
Core/core_riscv.c
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@ -1,274 +1,276 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.c * File Name : core_riscv.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.1
* Date : 2022/08/08 * Date : 2023/11/11
* Description : RISC-V Core Peripheral Access Layer Source File * Description : RISC-V V2 Core Peripheral Access Layer Source File for CH32V003
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <stdint.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
/* define compiler specific symbols */ #include <stdint.h>
#if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */ /* define compiler specific symbols */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */ #if defined(__CC_ARM)
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#elif defined(__ICCARM__) #define __INLINE __inline /*!< inline keyword for ARM Compiler */
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #elif defined(__ICCARM__)
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#elif defined(__GNUC__) #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */ #elif defined(__GNUC__)
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#elif defined(__TASKING__) #define __INLINE inline /*!< inline keyword for GNU Compiler */
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */ #elif defined(__TASKING__)
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#endif #define __INLINE inline /*!< inline keyword for TASKING Compiler */
/********************************************************************* #endif
* @fn __get_MSTATUS
* /*********************************************************************
* @brief Return the Machine Status Register * @fn __get_MSTATUS
* *
* @return mstatus value * @brief Return the Machine Status Register
*/ *
uint32_t __get_MSTATUS(void) * @return mstatus value
{ */
uint32_t result; uint32_t __get_MSTATUS(void)
{
__ASM volatile("csrr %0," "mstatus": "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0," "mstatus": "=r"(result));
return (result);
/********************************************************************* }
* @fn __set_MSTATUS
* /*********************************************************************
* @brief Set the Machine Status Register * @fn __set_MSTATUS
* *
* @param value - set mstatus value * @brief Set the Machine Status Register
* *
* @return none * @param value - set mstatus value
*/ *
void __set_MSTATUS(uint32_t value) * @return none
{ */
__ASM volatile("csrw mstatus, %0" : : "r"(value)); void __set_MSTATUS(uint32_t value)
} {
__ASM volatile("csrw mstatus, %0" : : "r"(value));
/********************************************************************* }
* @fn __get_MISA
* /*********************************************************************
* @brief Return the Machine ISA Register * @fn __get_MISA
* *
* @return misa value * @brief Return the Machine ISA Register
*/ *
uint32_t __get_MISA(void) * @return misa value
{ */
uint32_t result; uint32_t __get_MISA(void)
{
__ASM volatile("csrr %0,""misa" : "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0,""misa" : "=r"(result));
return (result);
/********************************************************************* }
* @fn __set_MISA
* /*********************************************************************
* @brief Set the Machine ISA Register * @fn __set_MISA
* *
* @param value - set misa value * @brief Set the Machine ISA Register
* *
* @return none * @param value - set misa value
*/ *
void __set_MISA(uint32_t value) * @return none
{ */
__ASM volatile("csrw misa, %0" : : "r"(value)); void __set_MISA(uint32_t value)
} {
__ASM volatile("csrw misa, %0" : : "r"(value));
/********************************************************************* }
* @fn __get_MTVEC
* /*********************************************************************
* @brief Return the Machine Trap-Vector Base-Address Register * @fn __get_MTVEC
* *
* @return mtvec value * @brief Return the Machine Trap-Vector Base-Address Register
*/ *
uint32_t __get_MTVEC(void) * @return mtvec value
{ */
uint32_t result; uint32_t __get_MTVEC(void)
{
__ASM volatile("csrr %0," "mtvec": "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0," "mtvec": "=r"(result));
return (result);
/********************************************************************* }
* @fn __set_MTVEC
* /*********************************************************************
* @brief Set the Machine Trap-Vector Base-Address Register * @fn __set_MTVEC
* *
* @param value - set mtvec value * @brief Set the Machine Trap-Vector Base-Address Register
* *
* @return none * @param value - set mtvec value
*/ *
void __set_MTVEC(uint32_t value) * @return none
{ */
__ASM volatile("csrw mtvec, %0":: "r"(value)); void __set_MTVEC(uint32_t value)
} {
__ASM volatile("csrw mtvec, %0":: "r"(value));
/********************************************************************* }
* @fn __get_MSCRATCH
* /*********************************************************************
* @brief Return the Machine Seratch Register * @fn __get_MSCRATCH
* *
* @return mscratch value * @brief Return the Machine Seratch Register
*/ *
uint32_t __get_MSCRATCH(void) * @return mscratch value
{ */
uint32_t result; uint32_t __get_MSCRATCH(void)
{
__ASM volatile("csrr %0," "mscratch" : "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0," "mscratch" : "=r"(result));
return (result);
/********************************************************************* }
* @fn __set_MSCRATCH
* /*********************************************************************
* @brief Set the Machine Seratch Register * @fn __set_MSCRATCH
* *
* @param value - set mscratch value * @brief Set the Machine Seratch Register
* *
* @return none * @param value - set mscratch value
*/ *
void __set_MSCRATCH(uint32_t value) * @return none
{ */
__ASM volatile("csrw mscratch, %0" : : "r"(value)); void __set_MSCRATCH(uint32_t value)
} {
__ASM volatile("csrw mscratch, %0" : : "r"(value));
/********************************************************************* }
* @fn __get_MEPC
* /*********************************************************************
* @brief Return the Machine Exception Program Register * @fn __get_MEPC
* *
* @return mepc value * @brief Return the Machine Exception Program Register
*/ *
uint32_t __get_MEPC(void) * @return mepc value
{ */
uint32_t result; uint32_t __get_MEPC(void)
{
__ASM volatile("csrr %0," "mepc" : "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0," "mepc" : "=r"(result));
return (result);
/********************************************************************* }
* @fn __set_MEPC
* /*********************************************************************
* @brief Set the Machine Exception Program Register * @fn __set_MEPC
* *
* @return mepc value * @brief Set the Machine Exception Program Register
*/ *
void __set_MEPC(uint32_t value) * @return mepc value
{ */
__ASM volatile("csrw mepc, %0" : : "r"(value)); void __set_MEPC(uint32_t value)
} {
__ASM volatile("csrw mepc, %0" : : "r"(value));
/********************************************************************* }
* @fn __get_MCAUSE
* /*********************************************************************
* @brief Return the Machine Cause Register * @fn __get_MCAUSE
* *
* @return mcause value * @brief Return the Machine Cause Register
*/ *
uint32_t __get_MCAUSE(void) * @return mcause value
{ */
uint32_t result; uint32_t __get_MCAUSE(void)
{
__ASM volatile("csrr %0," "mcause": "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0," "mcause": "=r"(result));
return (result);
/********************************************************************* }
* @fn __set_MEPC
* /*********************************************************************
* @brief Set the Machine Cause Register * @fn __set_MEPC
* *
* @return mcause value * @brief Set the Machine Cause Register
*/ *
void __set_MCAUSE(uint32_t value) * @return mcause value
{ */
__ASM volatile("csrw mcause, %0":: "r"(value)); void __set_MCAUSE(uint32_t value)
} {
__ASM volatile("csrw mcause, %0":: "r"(value));
/********************************************************************* }
* @fn __get_MVENDORID
* /*********************************************************************
* @brief Return Vendor ID Register * @fn __get_MVENDORID
* *
* @return mvendorid value * @brief Return Vendor ID Register
*/ *
uint32_t __get_MVENDORID(void) * @return mvendorid value
{ */
uint32_t result; uint32_t __get_MVENDORID(void)
{
__ASM volatile("csrr %0,""mvendorid": "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0,""mvendorid": "=r"(result));
return (result);
/********************************************************************* }
* @fn __get_MARCHID
* /*********************************************************************
* @brief Return Machine Architecture ID Register * @fn __get_MARCHID
* *
* @return marchid value * @brief Return Machine Architecture ID Register
*/ *
uint32_t __get_MARCHID(void) * @return marchid value
{ */
uint32_t result; uint32_t __get_MARCHID(void)
{
__ASM volatile("csrr %0,""marchid": "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0,""marchid": "=r"(result));
return (result);
/********************************************************************* }
* @fn __get_MIMPID
* /*********************************************************************
* @brief Return Machine Implementation ID Register * @fn __get_MIMPID
* *
* @return mimpid value * @brief Return Machine Implementation ID Register
*/ *
uint32_t __get_MIMPID(void) * @return mimpid value
{ */
uint32_t result; uint32_t __get_MIMPID(void)
{
__ASM volatile("csrr %0,""mimpid": "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0,""mimpid": "=r"(result));
return (result);
/********************************************************************* }
* @fn __get_MHARTID
* /*********************************************************************
* @brief Return Hart ID Register * @fn __get_MHARTID
* *
* @return mhartid value * @brief Return Hart ID Register
*/ *
uint32_t __get_MHARTID(void) * @return mhartid value
{ */
uint32_t result; uint32_t __get_MHARTID(void)
{
__ASM volatile("csrr %0,""mhartid": "=r"(result)); uint32_t result;
return (result);
} __ASM volatile("csrr %0,""mhartid": "=r"(result));
return (result);
/********************************************************************* }
* @fn __get_SP
* /*********************************************************************
* @brief Return SP Register * @fn __get_SP
* *
* @return SP value * @brief Return SP Register
*/ *
uint32_t __get_SP(void) * @return SP value
{ */
uint32_t result; uint32_t __get_SP(void)
{
__ASM volatile("mv %0,""sp": "=r"(result):); uint32_t result;
return (result);
} __ASM volatile("mv %0,""sp": "=r"(result):);
return (result);
}

761
Core/core_riscv.h
View file

@ -1,360 +1,401 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h * File Name : core_riscv.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.1
* Date : 2022/08/08 * Date : 2023/12/21
* Description : RISC-V Core Peripheral Access Layer Header File * Description : RISC-V V2 Core Peripheral Access Layer Header File for CH32V003
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CORE_RISCV_H__ * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CORE_RISCV_H__ *******************************************************************************/
#ifndef __CORE_RISCV_H__
/* IO definitions */ #define __CORE_RISCV_H__
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */ #ifdef __cplusplus
#else extern "C" {
#define __I volatile const /*!< defines 'read only' permissions */ #endif
#endif
#define __O volatile /*!< defines 'write only' permissions */ /* IO definitions */
#define __IO volatile /*!< defines 'read / write' permissions */ #ifdef __cplusplus
#define __I volatile /* defines 'read only' permissions */
/* Standard Peripheral Library old types (maintained for legacy purpose) */ #else
typedef __I uint32_t vuc32; /* Read Only */ #define __I volatile const /* defines 'read only' permissions */
typedef __I uint16_t vuc16; /* Read Only */ #endif
typedef __I uint8_t vuc8; /* Read Only */ #define __O volatile /* defines 'write only' permissions */
#define __IO volatile /* defines 'read / write' permissions */
typedef const uint32_t uc32; /* Read Only */
typedef const uint16_t uc16; /* Read Only */ /* Standard Peripheral Library old types (maintained for legacy purpose) */
typedef const uint8_t uc8; /* Read Only */ typedef __I uint32_t vuc32; /* Read Only */
typedef __I uint16_t vuc16; /* Read Only */
typedef __I int32_t vsc32; /* Read Only */ typedef __I uint8_t vuc8; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __I int8_t vsc8; /* Read Only */ typedef const uint32_t uc32; /* Read Only */
typedef const uint16_t uc16; /* Read Only */
typedef const int32_t sc32; /* Read Only */ typedef const uint8_t uc8; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef const int8_t sc8; /* Read Only */ typedef __I int32_t vsc32; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __IO uint32_t vu32; typedef __I int8_t vsc8; /* Read Only */
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8; typedef const int32_t sc32; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef uint32_t u32; typedef const int8_t sc8; /* Read Only */
typedef uint16_t u16;
typedef uint8_t u8; typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO int32_t vs32; typedef __IO uint8_t vu8;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8; typedef uint32_t u32;
typedef uint16_t u16;
typedef int32_t s32; typedef uint8_t u8;
typedef int16_t s16;
typedef int8_t s8; typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; typedef __IO int8_t vs8;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; typedef int32_t s32;
typedef int16_t s16;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; typedef int8_t s8;
#define RV_STATIC_INLINE static inline typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef struct{
__I uint32_t ISR[8]; typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
__I uint32_t IPR[8];
__IO uint32_t ITHRESDR; #define RV_STATIC_INLINE static inline
__IO uint32_t RESERVED;
__IO uint32_t CFGR; /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
__I uint32_t GISR; typedef struct{
__IO uint8_t VTFIDR[4]; __I uint32_t ISR[8];
uint8_t RESERVED0[12]; __I uint32_t IPR[8];
__IO uint32_t VTFADDR[4]; __IO uint32_t ITHRESDR;
uint8_t RESERVED1[0x90]; __IO uint32_t RESERVED;
__O uint32_t IENR[8]; __IO uint32_t CFGR;
uint8_t RESERVED2[0x60]; __I uint32_t GISR;
__O uint32_t IRER[8]; __IO uint8_t VTFIDR[4];
uint8_t RESERVED3[0x60]; uint8_t RESERVED0[12];
__O uint32_t IPSR[8]; __IO uint32_t VTFADDR[4];
uint8_t RESERVED4[0x60]; uint8_t RESERVED1[0x90];
__O uint32_t IPRR[8]; __O uint32_t IENR[8];
uint8_t RESERVED5[0x60]; uint8_t RESERVED2[0x60];
__IO uint32_t IACTR[8]; __O uint32_t IRER[8];
uint8_t RESERVED6[0xE0]; uint8_t RESERVED3[0x60];
__IO uint8_t IPRIOR[256]; __O uint32_t IPSR[8];
uint8_t RESERVED7[0x810]; uint8_t RESERVED4[0x60];
__IO uint32_t SCTLR; __O uint32_t IPRR[8];
}PFIC_Type; uint8_t RESERVED5[0x60];
__IO uint32_t IACTR[8];
/* memory mapped structure for SysTick */ uint8_t RESERVED6[0xE0];
typedef struct __IO uint8_t IPRIOR[256];
{ uint8_t RESERVED7[0x810];
__IO uint32_t CTLR; __IO uint32_t SCTLR;
__IO uint32_t SR; }PFIC_Type;
__IO uint32_t CNT;
uint32_t RESERVED0; /* memory mapped structure for SysTick */
__IO uint32_t CMP; typedef struct
uint32_t RESERVED1; {
}SysTick_Type; __IO uint32_t CTLR;
__IO uint32_t SR;
__IO uint32_t CNT;
#define PFIC ((PFIC_Type *) 0xE000E000 ) uint32_t RESERVED0;
#define NVIC PFIC __IO uint32_t CMP;
#define NVIC_KEY1 ((uint32_t)0xFA050000) uint32_t RESERVED1;
#define NVIC_KEY2 ((uint32_t)0xBCAF0000) }SysTick_Type;
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *) 0xE000F000) #define PFIC ((PFIC_Type *) 0xE000E000 )
#define NVIC PFIC
#define NVIC_KEY1 ((uint32_t)0xFA050000)
/********************************************************************* #define NVIC_KEY2 ((uint32_t)0xBCAF0000)
* @fn __enable_irq #define NVIC_KEY3 ((uint32_t)0xBEEF0000)
*
* @brief Enable Global Interrupt #define SysTick ((SysTick_Type *) 0xE000F000)
*
* @return none
*/ /*********************************************************************
RV_STATIC_INLINE void __enable_irq() * @fn __enable_irq
{ * This function is only used for Machine mode.
__asm volatile ("csrw mstatus, %0" : : "r" (0x1888) ); *
} * @brief Enable Global Interrupt
*
/********************************************************************* * @return none
* @fn __disable_irq */
* __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
* @brief Disable Global Interrupt {
* __asm volatile ("csrs mstatus, %0" : : "r" (0x88) );
* @return none }
*/
RV_STATIC_INLINE void __disable_irq() /*********************************************************************
{ * @fn __disable_irq
__asm volatile ("csrw mstatus, %0" : : "r" (0x1800) ); * This function is only used for Machine mode.
} *
* @brief Disable Global Interrupt
/********************************************************************* *
* @fn __NOP * @return none
* */
* @brief nop __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
* {
* @return none __asm volatile ("csrc mstatus, %0" : : "r" (0x88) );
*/ }
RV_STATIC_INLINE void __NOP()
{ /*********************************************************************
__asm volatile ("nop"); * @fn __NOP
} *
* @brief nop
/********************************************************************* *
* @fn NVIC_EnableIRQ * @return none
* */
* @brief Disable Interrupt __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
* {
* @param IRQn - Interrupt Numbers __asm volatile ("nop");
* }
* @return none
*/ /*********************************************************************
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) * @fn NVIC_EnableIRQ
{ *
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); * @brief Enable Interrupt
} *
* @param IRQn - Interrupt Numbers
/********************************************************************* *
* @fn NVIC_DisableIRQ * @return none
* */
* @brief Disable Interrupt __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
* {
* @param IRQn - Interrupt Numbers NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
* }
* @return none
*/ /*********************************************************************
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) * @fn NVIC_DisableIRQ
{ *
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); * @brief Disable Interrupt
} *
* @param IRQn - Interrupt Numbers
/********************************************************************* *
* @fn NVIC_GetStatusIRQ * @return none
* */
* @brief Get Interrupt Enable State __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
* {
* @param IRQn - Interrupt Numbers NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
* }
* @return 1 - 1: Interrupt Pending Enable
* 0 - Interrupt Pending Disable /*********************************************************************
*/ * @fn NVIC_GetStatusIRQ
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) *
{ * @brief Get Interrupt Enable State
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); *
} * @param IRQn - Interrupt Numbers
*
/********************************************************************* * @return 1 - Interrupt Pending Enable
* @fn NVIC_GetPendingIRQ * 0 - Interrupt Pending Disable
* */
* @brief Get Interrupt Pending State __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
* {
* @param IRQn - Interrupt Numbers return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
* }
* @return 1 - 1: Interrupt Pending Enable
* 0 - Interrupt Pending Disable /*********************************************************************
*/ * @fn NVIC_GetPendingIRQ
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) *
{ * @brief Get Interrupt Pending State
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); *
} * @param IRQn - Interrupt Numbers
*
/********************************************************************* * @return 1 - Interrupt Pending Enable
* @fn NVIC_SetPendingIRQ * 0 - Interrupt Pending Disable
* */
* @brief Set Interrupt Pending __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
* {
* @param IRQn - Interrupt Numbers return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
* }
* @return none
*/ /*********************************************************************
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) * @fn NVIC_SetPendingIRQ
{ *
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); * @brief Set Interrupt Pending
} *
* @param IRQn - Interrupt Numbers
/********************************************************************* *
* @fn NVIC_ClearPendingIRQ * @return none
* */
* @brief Clear Interrupt Pending __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
* {
* @param IRQn - Interrupt Numbers NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
* }
* @return none
*/ /*********************************************************************
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) * @fn NVIC_ClearPendingIRQ
{ *
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); * @brief Clear Interrupt Pending
} *
* @param IRQn - Interrupt Numbers
/********************************************************************* *
* @fn NVIC_GetActive * @return none
* */
* @brief Get Interrupt Active State __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
* {
* @param IRQn - Interrupt Numbers NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
* }
* @return 1 - Interrupt Active
* 0 - Interrupt No Active /*********************************************************************
*/ * @fn NVIC_GetActive
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) *
{ * @brief Get Interrupt Active State
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); *
} * @param IRQn - Interrupt Numbers
*
/********************************************************************* * @return 1 - Interrupt Active
* @fn NVIC_SetPriority * 0 - Interrupt No Active
* */
* @brief Set Interrupt Priority __attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
* {
* @param IRQn - Interrupt Numbers return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
* priority: bit7 - pre-emption priority }
* bit6 - subpriority
* bit[5-0] - reserved /*********************************************************************
* * @fn NVIC_SetPriority
* @return none *
*/ * @brief Set Interrupt Priority
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) *
{ * @param IRQn - Interrupt Numbers
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; * interrupt nesting enable(CSR-0x804 bit1 = 1)
} * priority - bit[7] - Preemption Priority
* bit[6] - Sub priority
/********************************************************************* * bit[5:0] - Reserve
* @fn __WFI * interrupt nesting disable(CSR-0x804 bit1 = 0)
* * priority - bit[7:6] - Sub priority
* @brief Wait for Interrupt * bit[5:0] - Reserve
* * @return none
* @return none */
*/ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) {
{ NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
NVIC->SCTLR &= ~(1<<3); // wfi }
asm volatile ("wfi");
} /*********************************************************************
* @fn __WFI
/********************************************************************* *
* @fn __WFE * @brief Wait for Interrupt
* *
* @brief Wait for Events * @return none
* */
* @return none __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
*/ {
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) NVIC->SCTLR &= ~(1<<3); // wfi
{ asm volatile ("wfi");
uint32_t t; }
t = NVIC->SCTLR; /*********************************************************************
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) * @fn _SEV
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); *
asm volatile ("wfi"); * @brief Set Event
asm volatile ("wfi"); *
} * @return none
*/
/********************************************************************* __attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
* @fn SetVTFIRQ {
* uint32_t t;
* @brief Set VTF Interrupt
* t = NVIC->SCTLR;
* @param addr - VTF interrupt service function base address. NVIC->SCTLR |= (1<<3)|(1<<5);
* IRQn - Interrupt Numbers NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
* num - VTF Interrupt Numbers }
* NewState - DISABLE or ENABLE
* /*********************************************************************
* @return none * @fn _WFE
*/ *
RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ * @brief Wait for Events
if(num > 1) return ; *
* @return none
if (NewState != DISABLE) */
{ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
NVIC->VTFIDR[num] = IRQn; {
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); NVIC->SCTLR |= (1<<3);
} asm volatile ("wfi");
else{ }
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); /*********************************************************************
} * @fn __WFE
} *
* @brief Wait for Events
/********************************************************************* *
* @fn NVIC_SystemReset * @return none
* */
* @brief Initiate a system reset request __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
* {
* @return none _SEV();
*/ _WFE();
RV_STATIC_INLINE void NVIC_SystemReset(void) _WFE();
{ }
NVIC->CFGR = NVIC_KEY3|(1<<7);
} /*********************************************************************
* @fn SetVTFIRQ
*
/* Core_Exported_Functions */ * @brief Set VTF Interrupt
extern uint32_t __get_MSTATUS(void); *
extern void __set_MSTATUS(uint32_t value); * @param addr - VTF interrupt service function base address.
extern uint32_t __get_MISA(void); * IRQn - Interrupt Numbers
extern void __set_MISA(uint32_t value); * num - VTF Interrupt Numbers
extern uint32_t __get_MTVEC(void); * NewState - DISABLE or ENABLE
extern void __set_MTVEC(uint32_t value); *
extern uint32_t __get_MSCRATCH(void); * @return none
extern void __set_MSCRATCH(uint32_t value); */
extern uint32_t __get_MEPC(void); __attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
extern void __set_MEPC(uint32_t value); {
extern uint32_t __get_MCAUSE(void); if(num > 1) return ;
extern void __set_MCAUSE(uint32_t value);
extern uint32_t __get_MVENDORID(void); if (NewState != DISABLE)
extern uint32_t __get_MARCHID(void); {
extern uint32_t __get_MIMPID(void); NVIC->VTFIDR[num] = IRQn;
extern uint32_t __get_MHARTID(void); NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
extern uint32_t __get_SP(void); }
else
{
#endif/* __CORE_RISCV_H__ */ NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
}
}
/*********************************************************************
* @fn NVIC_SystemReset
*
* @brief Initiate a system reset request
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
{
NVIC->CFGR = NVIC_KEY3|(1<<7);
}
/* Core_Exported_Functions */
extern uint32_t __get_MSTATUS(void);
extern void __set_MSTATUS(uint32_t value);
extern uint32_t __get_MISA(void);
extern void __set_MISA(uint32_t value);
extern uint32_t __get_MTVEC(void);
extern void __set_MTVEC(uint32_t value);
extern uint32_t __get_MSCRATCH(void);
extern void __set_MSCRATCH(uint32_t value);
extern uint32_t __get_MEPC(void);
extern void __set_MEPC(uint32_t value);
extern uint32_t __get_MCAUSE(void);
extern void __set_MCAUSE(uint32_t value);
extern uint32_t __get_MVENDORID(void);
extern uint32_t __get_MARCHID(void);
extern uint32_t __get_MIMPID(void);
extern uint32_t __get_MHARTID(void);
extern uint32_t __get_SP(void);
#ifdef __cplusplus
}
#endif
#endif/* __CORE_RISCV_H__ */

430
Debug/debug.c
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@ -1,153 +1,277 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : debug.c * File Name : debug.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for UART * Description : This file contains all the functions prototypes for UART
* Printf , Delay functions. * Printf , Delay functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <debug.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
static uint8_t p_us = 0; #include <debug.h>
static uint16_t p_ms = 0;
static uint8_t p_us = 0;
/********************************************************************* static uint16_t p_ms = 0;
* @fn Delay_Init
* #define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE00000F4)
* @brief Initializes Delay Funcation. #define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE00000F8)
*
* @return none /*********************************************************************
*/ * @fn Delay_Init
void Delay_Init(void) *
{ * @brief Initializes Delay Funcation.
p_us = SystemCoreClock / 8000000; *
p_ms = (uint16_t)p_us * 1000; * @return none
} */
void Delay_Init(void)
/********************************************************************* {
* @fn Delay_Us p_us = SystemCoreClock / 8000000;
* p_ms = p_us * 1000;
* @brief Microsecond Delay Time.
* SysTick->CTLR &= ~0x8000001F;
* @param n - Microsecond number. SysTick->CNT = 0;
* SysTick->CTLR |= (1 << 0);
* @return None }
*/
void Delay_Us(uint32_t n) uint64_t SysTick_Read(void)
{ {
uint32_t i; uint64_t ticks;
SysTick->CTLR &= ~(1 << 0);
SysTick->SR &= ~(1 << 0); ticks = SysTick->CNT;
i = (uint32_t)n * p_us; SysTick->CTLR |= (1 << 0);
SysTick->CMP = i; return ticks;
SysTick->CNT = 0; }
SysTick->CTLR |= (1 << 5) | (1 << 0);
uint64_t SysTick_Us(void)
while((SysTick->SR & (1 << 0)) != (1 << 0)); {
SysTick->CTLR &= ~(1 << 0); return SysTick_Read() / p_us;
} }
/********************************************************************* uint64_t SysTick_Ms(void)
* @fn Delay_Ms {
* return SysTick_Read() / p_ms;
* @brief Millisecond Delay Time. }
*
* @param n - Millisecond number. /*********************************************************************
* * @fn Delay_Us
* @return None *
*/ * @brief Microsecond Delay Time.
void Delay_Ms(uint32_t n) *
{ * @param n - Microsecond number.
uint32_t i; *
* @return None
SysTick->SR &= ~(1 << 0); */
i = (uint32_t)n * p_ms; void Delay_Us(uint32_t n)
{
SysTick->CMP = i; uint32_t i;
SysTick->CNT = 0;
SysTick->CTLR |= (1 << 5) | (1 << 0); SysTick->SR &= ~(1 << 0);
i = (uint32_t)n * p_us;
while((SysTick->SR & (1 << 0)) != (1 << 0));
SysTick->CTLR &= ~(1 << 0); SysTick->CMP = SysTick_Read() + i;
} while((SysTick->SR & (1 << 0)) != (1 << 0));
/*********************************************************************
* @fn USART_Printf_Init /*
* SysTick->CMP = i;
* @brief Initializes the USARTx peripheral. SysTick->CTLR |= (1 << 4);
* SysTick->CTLR |= (1 << 5) | (1 << 0);
* @param baudrate - USART communication baud rate.
* while((SysTick->SR & (1 << 0)) != (1 << 0));
* @return None SysTick->CTLR &= ~(1 << 0);
*/ */
void USART_Printf_Init(uint32_t baudrate) }
{
GPIO_InitTypeDef GPIO_InitStructure; /*********************************************************************
USART_InitTypeDef USART_InitStructure; * @fn Delay_Ms
*
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE); * @brief Millisecond Delay Time.
*
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; * @param n - Millisecond number.
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; *
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; * @return None
GPIO_Init(GPIOD, &GPIO_InitStructure); */
void Delay_Ms(uint32_t n)
USART_InitStructure.USART_BaudRate = baudrate; {
USART_InitStructure.USART_WordLength = USART_WordLength_8b; uint32_t i;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No; SysTick->SR &= ~(1 << 0);
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; i = (uint32_t)n * p_ms;
USART_InitStructure.USART_Mode = USART_Mode_Tx;
SysTick->CMP = SysTick_Read() + i;
USART_Init(USART1, &USART_InitStructure); while((SysTick->SR & (1 << 0)) != (1 << 0));
USART_Cmd(USART1, ENABLE);
} /*
SysTick->CMP = i;
/********************************************************************* SysTick->CTLR |= (1 << 4);
* @fn _write SysTick->CTLR |= (1 << 5) | (1 << 0);
*
* @brief Support Printf Function while((SysTick->SR & (1 << 0)) != (1 << 0));
* SysTick->CTLR &= ~(1 << 0);
* @param *buf - UART send Data. */
* size - Data length. }
*
* @return size - Data length /*********************************************************************
*/ * @fn USART_Printf_Init
__attribute__((used)) *
int _write(int fd, char *buf, int size) * @brief Initializes the USARTx peripheral.
{ *
int i; * @param baudrate - USART communication baud rate.
*
for(i = 0; i < size; i++){ * @return None
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); */
USART_SendData(USART1, *buf++); void USART_Printf_Init(uint32_t baudrate)
} {
GPIO_InitTypeDef GPIO_InitStructure;
return size; USART_InitTypeDef USART_InitStructure;
}
#if (DEBUG == DEBUG_UART1_NoRemap)
/********************************************************************* RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE);
* @fn _sbrk
* GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
* @brief Change the spatial position of data segment. GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
* GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
* @return size: Data length GPIO_Init(GPIOD, &GPIO_InitStructure);
*/
void *_sbrk(ptrdiff_t incr) #elif (DEBUG == DEBUG_UART1_Remap1)
{ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
extern char _end[]; GPIO_PinRemapConfig(GPIO_PartialRemap1_USART1, ENABLE);
extern char _heap_end[];
static char *curbrk = _end; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
return NULL - 1; GPIO_Init(GPIOD, &GPIO_InitStructure);
curbrk += incr; #elif (DEBUG == DEBUG_UART1_Remap2)
return curbrk - incr; RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
} GPIO_PinRemapConfig(GPIO_PartialRemap2_USART1, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#elif (DEBUG == DEBUG_UART1_Remap3)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
GPIO_PinRemapConfig(GPIO_FullRemap_USART1, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
#endif
USART_InitStructure.USART_BaudRate = baudrate;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Tx;
USART_Init(USART1, &USART_InitStructure);
USART_Cmd(USART1, ENABLE);
}
/*********************************************************************
* @fn SDI_Printf_Enable
*
* @brief Initializes the SDI printf Function.
*
* @param None
*
* @return None
*/
void SDI_Printf_Enable(void)
{
*(DEBUG_DATA0_ADDRESS) = 0;
Delay_Init();
Delay_Ms(1);
}
/*********************************************************************
* @fn _write
*
* @brief Support Printf Function
*
* @param *buf - UART send Data.
* size - Data length.
*
* @return size - Data length
*/
__attribute__((used))
int _write(int fd, char *buf, int size)
{
int i = 0;
int writeSize = size;
#if (SDI_PRINT == SDI_PR_OPEN)
do
{
/**
* data0 data1 8 bytes
* data0 The lowest byte storage length, the maximum is 7
*
*/
while( (*(DEBUG_DATA0_ADDRESS) != 0u))
{
}
if(writeSize>7)
{
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
i += 7;
writeSize -= 7;
}
else
{
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
writeSize = 0;
}
} while (writeSize);
#else
for(i = 0; i < size; i++){
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
USART_SendData(USART1, *buf++);
}
#endif
return writeSize;
}
/*********************************************************************
* @fn _sbrk
*
* @brief Change the spatial position of data segment.
*
* @return size: Data length
*/
__attribute__((used))
void *_sbrk(ptrdiff_t incr)
{
extern char _end[];
extern char _heap_end[];
static char *curbrk = _end;
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
return NULL - 1;
curbrk += incr;
return curbrk - incr;
}

83
Debug/debug.h
View file

@ -1,28 +1,55 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : debug.h * File Name : debug.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for UART * Description : This file contains all the functions prototypes for UART
* Printf , Delay functions. * Printf , Delay functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __DEBUG_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __DEBUG_H *******************************************************************************/
#ifndef __DEBUG_H
#include <ch32v00x.h> #define __DEBUG_H
#include <stdio.h>
#ifdef __cplusplus
/* UART Printf Definition */ extern "C" {
#define DEBUG_UART1 1 #endif
/* DEBUG UATR Definition */ #include <ch32v00x.h>
#define DEBUG DEBUG_UART1 #include <stdio.h>
void Delay_Init(void); /* UART Printf Definition */
void Delay_Us(uint32_t n); #define DEBUG_UART1_NoRemap 1 //Tx-PD5
void Delay_Ms(uint32_t n); #define DEBUG_UART1_Remap1 2 //Tx-PD0
void USART_Printf_Init(uint32_t baudrate); #define DEBUG_UART1_Remap2 3 //Tx-PD6
#define DEBUG_UART1_Remap3 4 //Tx-PC0
#endif /* __DEBUG_H */
/* DEBUG UATR Definition */
#ifndef DEBUG
#define DEBUG DEBUG_UART1_NoRemap
#endif
/* SDI Printf Definition */
#define SDI_PR_CLOSE 0
#define SDI_PR_OPEN 1
#ifndef SDI_PRINT
#define SDI_PRINT SDI_PR_CLOSE
#endif
void Delay_Init(void);
uint64_t SysTick_Read(void);
uint64_t SysTick_Us(void);
uint64_t SysTick_Ms(void);
void Delay_Us(uint32_t n);
void Delay_Ms(uint32_t n);
void USART_Printf_Init(uint32_t baudrate);
void SDI_Printf_Enable(void);
#ifdef __cplusplus
}
#endif
#endif /* __DEBUG_H */

2
Ld/Link.ld
View file

@ -1,6 +1,6 @@
ENTRY( _start ) ENTRY( _start )
__stack_size = 512; __stack_size = 256;
PROVIDE( _stack_size = __stack_size ); PROVIDE( _stack_size = __stack_size );

4627
Peripheral/inc/ch32v00x.h
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File diff suppressed because it is too large Load diff

350
Peripheral/inc/ch32v00x_adc.h
View file

@ -1,174 +1,176 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_adc.h * File Name : ch32v00x_adc.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* ADC firmware library. * ADC firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_ADC_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_ADC_H *******************************************************************************/
#ifndef __CH32V00x_ADC_H
#ifdef __cplusplus #define __CH32V00x_ADC_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* ADC Init structure definition */ #include <ch32v00x.h>
typedef struct
{ /* ADC Init structure definition */
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or typedef struct
dual mode. {
This parameter can be a value of @ref ADC_mode */ uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
dual mode.
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in This parameter can be a value of @ref ADC_mode */
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */ FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in This parameter can be set to ENABLE or DISABLE */
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */ FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
Continuous or Single mode.
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog This parameter can be set to ENABLE or DISABLE. */
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
This parameter can be a value of @ref ADC_data_align */
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted This parameter can be a value of @ref ADC_data_align */
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */ uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
} ADC_InitTypeDef; using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
/* ADC_mode */ } ADC_InitTypeDef;
#define ADC_Mode_Independent ((uint32_t)0x00000000)
/* ADC_mode */
/* ADC_external_trigger_sources_for_regular_channels_conversion */ #define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) /* ADC_external_trigger_sources_for_regular_channels_conversion */
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) #define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000) #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000) #define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
/* ADC_data_align */ #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800) /* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
/* ADC_channels */ #define ADC_DataAlign_Left ((uint32_t)0x00000800)
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01) /* ADC_channels */
#define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8) #define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
/* ADC_sampling_time */ #define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
#define ADC_SampleTime_9Cycles ((uint8_t)0x01) /* ADC_sampling_time */
#define ADC_SampleTime_15Cycles ((uint8_t)0x02) #define ADC_SampleTime_3Cycles ((uint8_t)0x00)
#define ADC_SampleTime_30Cycles ((uint8_t)0x03) #define ADC_SampleTime_9Cycles ((uint8_t)0x01)
#define ADC_SampleTime_43Cycles ((uint8_t)0x04) #define ADC_SampleTime_15Cycles ((uint8_t)0x02)
#define ADC_SampleTime_57Cycles ((uint8_t)0x05) #define ADC_SampleTime_30Cycles ((uint8_t)0x03)
#define ADC_SampleTime_73Cycles ((uint8_t)0x06) #define ADC_SampleTime_43Cycles ((uint8_t)0x04)
#define ADC_SampleTime_241Cycles ((uint8_t)0x07) #define ADC_SampleTime_57Cycles ((uint8_t)0x05)
#define ADC_SampleTime_73Cycles ((uint8_t)0x06)
/* ADC_external_trigger_sources_for_injected_channels_conversion */ #define ADC_SampleTime_241Cycles ((uint8_t)0x07)
#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) /* ADC_external_trigger_sources_for_injected_channels_conversion */
#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) #define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000) #define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) #define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
/* ADC_injected_channel_selection */ #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18) /* ADC_injected_channel_selection */
#define ADC_InjectedChannel_3 ((uint8_t)0x1C) #define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_4 ((uint8_t)0x20) #define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
/* ADC_analog_watchdog_selection */ #define ADC_InjectedChannel_4 ((uint8_t)0x20)
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) /* ADC_analog_watchdog_selection */
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
/* ADC_interrupts_definition */ #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140) /* ADC_interrupts_definition */
#define ADC_IT_JEOC ((uint16_t)0x0480) #define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
/* ADC_flags_definition */ #define ADC_IT_JEOC ((uint16_t)0x0480)
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02) /* ADC_flags_definition */
#define ADC_FLAG_JEOC ((uint8_t)0x04) #define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_JSTRT ((uint8_t)0x08) #define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_STRT ((uint8_t)0x10) #define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
/* ADC_calibration_voltage_definition */ #define ADC_FLAG_STRT ((uint8_t)0x10)
#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000)
#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000) /* ADC_calibration_voltage_definition */
#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000)
/* ADC_external_trigger_sources_delay_channels_definition */ #define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000)
#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000) /* ADC_external_trigger_sources_delay_channels_definition */
#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000)
void ADC_DeInit(ADC_TypeDef *ADCx);
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); void ADC_DeInit(ADC_TypeDef *ADCx);
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef *ADCx); void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_StartCalibration(ADC_TypeDef *ADCx); void ADC_ResetCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_StartCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL); ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim); void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL);
#ifdef __cplusplus void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim);
}
#endif #ifdef __cplusplus
}
#endif /*__CH32V00x_ADC_H */ #endif
#endif /*__CH32V00x_ADC_H */

74
Peripheral/inc/ch32v00x_dbgmcu.h
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@ -1,36 +1,38 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_dbgmcu.h * File Name : ch32v00x_dbgmcu.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* DBGMCU firmware library. * DBGMCU firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_DBGMCU_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_DBGMCU_H *******************************************************************************/
#ifndef __CH32V00x_DBGMCU_H
#ifdef __cplusplus #define __CH32V00x_DBGMCU_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* CFGR0 Register */ #include <ch32v00x.h>
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002) /* CFGR0 Register */
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010) #define DBGMCU_IWDG_STOP ((uint32_t)0x00000001)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000002)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010)
uint32_t DBGMCU_GetREVID(void); #define DBGMCU_TIM2_STOP ((uint32_t)0x00000020)
uint32_t DBGMCU_GetDEVID(void);
uint32_t __get_DEBUG_CR(void); uint32_t DBGMCU_GetREVID(void);
void __set_DEBUG_CR(uint32_t value); uint32_t DBGMCU_GetDEVID(void);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); uint32_t __get_DEBUG_CR(void);
void __set_DEBUG_CR(uint32_t value);
#ifdef __cplusplus void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
} uint32_t DBGMCU_GetCHIPID( void );
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_DBGMCU_H */ #endif
#endif /* __CH32V00x_DBGMCU_H */

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Peripheral/inc/ch32v00x_dma.h
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@ -1,175 +1,177 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_dma.h * File Name : ch32v00x_dma.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* DMA firmware library. * DMA firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_DMA_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_DMA_H *******************************************************************************/
#ifndef __CH32V00x_DMA_H
#ifdef __cplusplus #define __CH32V00x_DMA_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* DMA Init structure definition */ #include <ch32v00x.h>
typedef struct
{ /* DMA Init structure definition */
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ typedef struct
{
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. This parameter can be a value of @ref DMA_data_transfer_direction */
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */ uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. or DMA_MemoryDataSize members depending in the transfer direction. */
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. This parameter can be a value of @ref DMA_peripheral_incremented_mode */
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. This parameter can be a value of @ref DMA_memory_incremented_mode */
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. This parameter can be a value of @ref DMA_peripheral_data_size */
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. This parameter can be a value of @ref DMA_memory_data_size */
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
data transfer is configured on the selected Channel */ This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. data transfer is configured on the selected Channel */
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. This parameter can be a value of @ref DMA_priority_level */
This parameter can be a value of @ref DMA_memory_to_memory */
} DMA_InitTypeDef; uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
/* DMA_data_transfer_direction */ } DMA_InitTypeDef;
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) /* DMA_data_transfer_direction */
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
/* DMA_peripheral_incremented_mode */ #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) /* DMA_peripheral_incremented_mode */
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
/* DMA_memory_incremented_mode */ #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) /* DMA_memory_incremented_mode */
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
/* DMA_peripheral_data_size */ #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) /* DMA_peripheral_data_size */
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
/* DMA_memory_data_size */ #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) /* DMA_memory_data_size */
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
/* DMA_circular_normal_mode */ #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000) /* DMA_circular_normal_mode */
#define DMA_Mode_Circular ((uint32_t)0x00000020)
/* DMA_priority_level */ #define DMA_Mode_Normal ((uint32_t)0x00000000)
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000) /* DMA_priority_level */
#define DMA_Priority_Medium ((uint32_t)0x00001000) #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_Low ((uint32_t)0x00000000) #define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
/* DMA_memory_to_memory */ #define DMA_Priority_Low ((uint32_t)0x00000000)
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000) /* DMA_memory_to_memory */
#define DMA_M2M_Enable ((uint32_t)0x00004000)
/* DMA_interrupts_definition */ #define DMA_M2M_Disable ((uint32_t)0x00000000)
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004) /* DMA_interrupts_definition */
#define DMA_IT_TE ((uint32_t)0x00000008) #define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA1_IT_GL1 ((uint32_t)0x00000001) #define DMA_IT_TE ((uint32_t)0x00000008)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004) #define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TE1 ((uint32_t)0x00000008) #define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_GL2 ((uint32_t)0x00000010) #define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TC2 ((uint32_t)0x00000020) #define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_HT2 ((uint32_t)0x00000040) #define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TE2 ((uint32_t)0x00000080) #define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_GL3 ((uint32_t)0x00000100) #define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TC3 ((uint32_t)0x00000200) #define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_HT3 ((uint32_t)0x00000400) #define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TE3 ((uint32_t)0x00000800) #define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_GL4 ((uint32_t)0x00001000) #define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TC4 ((uint32_t)0x00002000) #define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_HT4 ((uint32_t)0x00004000) #define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000) #define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000) #define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000) #define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000) #define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000) #define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000) #define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000) #define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000) #define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000) #define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000) #define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000) #define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000) #define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000) #define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
/* DMA_flags_definition */ #define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) /* DMA_flags_definition */
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
void DMA_ClearFlag(uint32_t DMAy_FLAG); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT); FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearITPendingBit(uint32_t DMAy_IT); void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
#ifdef __cplusplus void DMA_ClearITPendingBit(uint32_t DMAy_IT);
}
#endif #ifdef __cplusplus
}
#endif /*__CH32V00x_DMA_H */ #endif
#endif /*__CH32V00x_DMA_H */

154
Peripheral/inc/ch32v00x_exti.h
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@ -1,76 +1,78 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_exti.h * File Name : ch32v00x_exti.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* EXTI firmware library. * EXTI firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_EXTI_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_EXTI_H *******************************************************************************/
#ifndef __CH32V00x_EXTI_H
#ifdef __cplusplus #define __CH32V00x_EXTI_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* EXTI mode enumeration */ #include <ch32v00x.h>
typedef enum
{ /* EXTI mode enumeration */
EXTI_Mode_Interrupt = 0x00, typedef enum
EXTI_Mode_Event = 0x04 {
} EXTIMode_TypeDef; EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
/* EXTI Trigger enumeration */ } EXTIMode_TypeDef;
typedef enum
{ /* EXTI Trigger enumeration */
EXTI_Trigger_Rising = 0x08, typedef enum
EXTI_Trigger_Falling = 0x0C, {
EXTI_Trigger_Rising_Falling = 0x10 EXTI_Trigger_Rising = 0x08,
} EXTITrigger_TypeDef; EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
/* EXTI Init Structure definition */ } EXTITrigger_TypeDef;
typedef struct
{ /* EXTI Init Structure definition */
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. typedef struct
This parameter can be any combination of @ref EXTI_Lines */ {
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. This parameter can be any combination of @ref EXTI_Lines */
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. This parameter can be a value of @ref EXTIMode_TypeDef */
This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitTypeDef; FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
/* EXTI_Lines */ } EXTI_InitTypeDef;
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ /* EXTI_Lines */
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ #define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ #define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ #define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ #define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ #define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ #define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */ #define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/ #define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */
void EXTI_DeInit(void); #define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); void EXTI_DeInit(void);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_ClearFlag(uint32_t EXTI_Line); void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line); void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
#ifdef __cplusplus void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
}
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_EXTI_H */ #endif
#endif /* __CH32V00x_EXTI_H */

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Peripheral/inc/ch32v00x_flash.h
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@ -1,126 +1,138 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_flash.h * File Name : ch32v00x_flash.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2023/12/25
* Description : This file contains all the functions prototypes for the FLASH * Description : This file contains all the functions prototypes for the FLASH
* firmware library. * firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_FLASH_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_FLASH_H *******************************************************************************/
#ifndef __CH32V00x_FLASH_H
#ifdef __cplusplus #define __CH32V00x_FLASH_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* FLASH Status */ #include <ch32v00x.h>
typedef enum
{ /* FLASH Status */
FLASH_BUSY = 1, typedef enum
FLASH_ERROR_PG, {
FLASH_ERROR_WRP, FLASH_BUSY = 1,
FLASH_COMPLETE, FLASH_ERROR_PG,
FLASH_TIMEOUT FLASH_ERROR_WRP,
} FLASH_Status; FLASH_COMPLETE,
FLASH_TIMEOUT,
/* Flash_Latency */ FLASH_OP_RANGE_ERROR = 0xFD,
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ FLASH_ALIGN_ERROR = 0xFE,
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ FLASH_ADR_RANGE_ERROR = 0xFF,
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ } FLASH_Status;
/* Values to be used with CH32V00x devices (1page = 64Byte) */ /* Flash_Latency */
#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */ #define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */ #define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */ #define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */
#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */ /* Values to be used with CH32V00x devices (1page = 64Byte) */
#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */ #define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */ #define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */ #define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */
#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */ #define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */
#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */ #define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */
#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */ #define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */
#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */ #define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */
#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */ #define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */
#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */ #define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */
#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */ #define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */
#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */ #define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */
#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */
#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */ #define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */
#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */
/* Option_Bytes_IWatchdog */ #define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ #define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
/* Option_Bytes_nRST_STOP */
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ /* Option_Bytes_IWatchdog */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
/* Option_Bytes_nRST_STDBY */
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ /* Option_Bytes_nRST_STOP */
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ #define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
/* Option_Bytes_RST_ENandDT */
#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/ /* Option_Bytes_nRST_STDBY */
#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */ #define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */ #define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */
/* Option_Bytes_RST_ENandDT */
/* FLASH_Interrupts */ #define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ #define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ #define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ #define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128us */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
/* Option_Bytes_Power_ON_Start_Mode */
/* FLASH_Flags */ #define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ #define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ /* FLASH_Interrupts */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ #define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
/* FLASH_Flags */
/* System_Reset_Start_Mode */ #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define Start_Mode_USER ((uint32_t)0x00000000) #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define Start_Mode_BOOT ((uint32_t)0x00004000) #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
/*Functions used for all CH32V00x devices*/ #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
void FLASH_SetLatency(uint32_t FLASH_Latency); #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
void FLASH_Unlock(void); #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address); /* System_Reset_Start_Mode */
FLASH_Status FLASH_EraseAllPages(void); #define Start_Mode_USER ((uint32_t)0x00000000)
FLASH_Status FLASH_EraseOptionBytes(void); #define Start_Mode_BOOT ((uint32_t)0x00004000)
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); /*Functions used for all CH32V00x devices*/
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); void FLASH_SetLatency(uint32_t FLASH_Latency);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); void FLASH_Unlock(void);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY, uint16_t OB_RST); void FLASH_Lock(void);
uint32_t FLASH_GetUserOptionByte(void); FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
uint32_t FLASH_GetWriteProtectionOptionByte(void); FLASH_Status FLASH_EraseAllPages(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void); FLASH_Status FLASH_EraseOptionBytes(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
void FLASH_ClearFlag(uint32_t FLASH_FLAG); FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
void FLASH_Unlock_Fast(void); FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode);
void FLASH_Lock_Fast(void); uint32_t FLASH_GetUserOptionByte(void);
void FLASH_BufReset(void); uint32_t FLASH_GetWriteProtectionOptionByte(void);
void FLASH_BufLoad(uint32_t Address, uint32_t Data0); FlagStatus FLASH_GetReadOutProtectionStatus(void);
void FLASH_ErasePage_Fast(uint32_t Page_Address); void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
void FLASH_ProgramPage_Fast(uint32_t Page_Address); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
#ifdef __cplusplus FLASH_Status FLASH_GetStatus(void);
} FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
#endif void FLASH_Unlock_Fast(void);
void FLASH_Lock_Fast(void);
#endif /* __CH32V00x_FLASH_H */ void FLASH_BufReset(void);
void FLASH_BufLoad(uint32_t Address, uint32_t Data0);
void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address);
void SystemReset_StartMode(uint32_t Mode);
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V00x_FLASH_H */

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Peripheral/inc/ch32v00x_gpio.h
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@ -1,128 +1,130 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_gpio.h * File Name : ch32v00x_gpio.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* GPIO firmware library. * GPIO firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_GPIO_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_GPIO_H *******************************************************************************/
#ifndef __CH32V00x_GPIO_H
#ifdef __cplusplus #define __CH32V00x_GPIO_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* Output Maximum frequency selection */ #include <ch32v00x.h>
typedef enum
{ /* Output Maximum frequency selection */
GPIO_Speed_10MHz = 1, typedef enum
GPIO_Speed_2MHz, {
GPIO_Speed_50MHz GPIO_Speed_10MHz = 1,
} GPIOSpeed_TypeDef; GPIO_Speed_2MHz,
GPIO_Speed_50MHz
/* Configuration Mode enumeration */ } GPIOSpeed_TypeDef;
typedef enum
{ /* Configuration Mode enumeration */
GPIO_Mode_AIN = 0x0, typedef enum
GPIO_Mode_IN_FLOATING = 0x04, {
GPIO_Mode_IPD = 0x28, GPIO_Mode_AIN = 0x0,
GPIO_Mode_IPU = 0x48, GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_Out_OD = 0x14, GPIO_Mode_IPD = 0x28,
GPIO_Mode_Out_PP = 0x10, GPIO_Mode_IPU = 0x48,
GPIO_Mode_AF_OD = 0x1C, GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_AF_PP = 0x18 GPIO_Mode_Out_PP = 0x10,
} GPIOMode_TypeDef; GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
/* GPIO Init structure definition */ } GPIOMode_TypeDef;
typedef struct
{ /* GPIO Init structure definition */
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. typedef struct
This parameter can be any value of @ref GPIO_pins_define */ {
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. This parameter can be any value of @ref GPIO_pins_define */
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIOSpeed_TypeDef */
This parameter can be a value of @ref GPIOMode_TypeDef */
} GPIO_InitTypeDef; GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
/* Bit_SET and Bit_RESET enumeration */ } GPIO_InitTypeDef;
typedef enum
{ /* Bit_SET and Bit_RESET enumeration */
Bit_RESET = 0, typedef enum
Bit_SET {
} BitAction; Bit_RESET = 0,
Bit_SET
/* GPIO_pins_define */ } BitAction;
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ /* GPIO_pins_define */
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
/* GPIO_Remap_define */ #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */ /* GPIO_Remap_define */
#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */ #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */
#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */ #define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */
#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */ #define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */ #define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ #define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */ #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ #define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */
#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */ #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */ #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */
/* GPIO_Port_Sources */ #define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02) /* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOD ((uint8_t)0x03) #define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
/* GPIO_Pin_sources */ #define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01) /* GPIO_Pin_sources */
#define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
void GPIO_DeInit(GPIO_TypeDef *GPIOx); #define GPIO_PinSource7 ((uint8_t)0x07)
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); void GPIO_DeInit(GPIO_TypeDef *GPIOx);
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); void GPIO_AFIODeInit(void);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
void GPIO_EventOutputCmd(FunctionalState NewState); void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
#ifdef __cplusplus void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
}
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_GPIO_H */ #endif
#endif /* __CH32V00x_GPIO_H */

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Peripheral/inc/ch32v00x_i2c.h
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@ -1,185 +1,415 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_i2c.h * File Name : ch32v00x_i2c.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* I2C firmware library. * I2C firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_I2C_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_I2C_H *******************************************************************************/
#ifndef __CH32V00x_I2C_H
#ifdef __cplusplus #define __CH32V00x_I2C_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* I2C Init structure definition */ #include <ch32v00x.h>
typedef struct
{ /* I2C Init structure definition */
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. typedef struct
This parameter must be set to a value lower than 400kHz */ {
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
uint16_t I2C_Mode; /* Specifies the I2C mode. This parameter must be set to a value lower than 400kHz */
This parameter can be a value of @ref I2C_mode */
uint16_t I2C_Mode; /* Specifies the I2C mode.
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. This parameter can be a value of @ref I2C_mode */
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
uint16_t I2C_OwnAddress1; /* Specifies the first device own address. This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
uint16_t I2C_Ack; /* Enables or disables the acknowledgement. This parameter can be a 7-bit or 10-bit address. */
This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. This parameter can be a value of @ref I2C_acknowledgement */
This parameter can be a value of @ref I2C_acknowledged_address */
} I2C_InitTypeDef; uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */
/* I2C_mode */ } I2C_InitTypeDef;
#define I2C_Mode_I2C ((uint16_t)0x0000)
/* I2C_mode */
/* I2C_duty_cycle_in_fast_mode */ #define I2C_Mode_I2C ((uint16_t)0x0000)
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ /* I2C_duty_cycle_in_fast_mode */
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
/* I2C_acknowledgement */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
#define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000) /* I2C_acknowledgement */
#define I2C_Ack_Enable ((uint16_t)0x0400)
/* I2C_transfer_direction */ #define I2C_Ack_Disable ((uint16_t)0x0000)
#define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01) /* I2C_transfer_direction */
#define I2C_Direction_Transmitter ((uint8_t)0x00)
/* I2C_acknowledged_address */ #define I2C_Direction_Receiver ((uint8_t)0x01)
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) /* I2C_acknowledged_address */
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
/* I2C_registers */ #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
#define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_CTLR2 ((uint8_t)0x04) /* I2C_registers */
#define I2C_Register_OADDR1 ((uint8_t)0x08) #define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_OADDR2 ((uint8_t)0x0C) #define I2C_Register_CTLR2 ((uint8_t)0x04)
#define I2C_Register_DATAR ((uint8_t)0x10) #define I2C_Register_OADDR1 ((uint8_t)0x08)
#define I2C_Register_STAR1 ((uint8_t)0x14) #define I2C_Register_OADDR2 ((uint8_t)0x0C)
#define I2C_Register_STAR2 ((uint8_t)0x18) #define I2C_Register_DATAR ((uint8_t)0x10)
#define I2C_Register_CKCFGR ((uint8_t)0x1C) #define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18)
/* I2C_PEC_position */ #define I2C_Register_CKCFGR ((uint8_t)0x1C)
#define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF) /* I2C_PEC_position */
#define I2C_PECPosition_Next ((uint16_t)0x0800)
/* I2C_NACK_position */ #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) /* I2C_NACK_position */
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
/* I2C_interrupts_definition */ #define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
#define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200) /* I2C_interrupts_definition */
#define I2C_IT_ERR ((uint16_t)0x0100) #define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200)
/* I2C_interrupts_definition */ #define I2C_IT_ERR ((uint16_t)0x0100)
#define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800) /* I2C_interrupts_definition */
#define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_SB ((uint32_t)0x02000001) #define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002)
/* SR2 register flags */ #define I2C_IT_SB ((uint32_t)0x02000001)
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) /* SR2 register flags */
#define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000) #define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
/* SR1 register flags */ #define I2C_FLAG_MSL ((uint32_t)0x00010000)
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800) /* SR1 register flags */
#define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_SB ((uint32_t)0x10000001) #define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
/****************I2C Master Events (Events grouped in order of communication)********************/ #define I2C_FLAG_SB ((uint32_t)0x10000001)
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ /****************I2C Master Events (Events grouped in order of communication)********************/
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ /********************************************************************************************************************
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ * @brief Start communicate
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ *
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ * After master use I2C_GenerateSTART() function sending the START condition,the master
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ * has to wait for event 5(the Start condition has been correctly
* released on the I2C bus ).
/******************I2C Slave Events (Events grouped in order of communication)******************/ *
*/
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ /* EVT5 */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ /********************************************************************************************************************
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ * @brief Address Acknowledge
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ *
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ * When start condition correctly released on the bus(check EVT5), the
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ * his address. If an acknowledge is sent on the bus, one of the following events will be set:
*
void I2C_DeInit(I2C_TypeDef *I2Cx); *
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); *
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); * event is set.
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); *
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); * is set
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); *
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); * 3) In case of 10-Bit addressing mode, the master (after generating the START
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); * of the 10-bit address (LSB) . Then master should wait for event 6.
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); *
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); *
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); */
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); /* EVT6 */
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); /*EVT9 */
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); /********************************************************************************************************************
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); * @brief Communication events
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); *
* If START condition has generated and slave address
/**************************************************************************************** * been acknowledged. then the master has to check one of the following events for
* I2C State Monitoring Functions * communication procedures:
****************************************************************************************/ *
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT); * I2C_ReceiveData() function to read the data received from the slave .
uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx); *
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); * 2) Master Transmitter mode: The master use I2C_SendData() function to send data
* then to wait on event EVT8 or EVT8_2.
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); * These two events are similar:
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); * - EVT8 means that the data has been written in the data register and is
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); * being shifted out.
* - EVT8_2 means that the data has been physically shifted out and output
#ifdef __cplusplus * on the bus.
} * In most cases, using EVT8 is sufficient for the application.
#endif * Using EVT8_2 will leads to a slower communication speed but will more reliable .
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
#endif /*__CH32V00x_I2C_H */ *
*
* Note:
* In case the user software does not guarantee that this event EVT7 is managed before
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
*
*
*/
/* Master Receive mode */
/* EVT7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master Transmitter mode*/
/* EVT8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* EVT8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/******************I2C Slave Events (Events grouped in order of communication)******************/
/********************************************************************************************************************
* @brief Start Communicate events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a start condition of master device generate on the bus.
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
*
*
*
* a) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* b) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* c) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* EVT1 */
/* a) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* b) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* c) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/********************************************************************************************************************
* @brief Communication events
*
* Wait on one of these events when EVT1 has already been checked :
*
* - Slave Receiver mode:
* - EVT2--The device is expecting to receive a data byte .
* - EVT4--The device is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
* the EVT3 is managed before the current byte end of transfer The second one can optionally
* be used.
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission
* shall end . The slave device has to stop sending
* data bytes and wait a Stop condition from bus.
*
* Note:
* If the user software does not guarantee that the event 2 is
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time .
* In this case the communication will be slower.
*
*/
/* Slave Receiver mode*/
/* EVT2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* EVT4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave Transmitter mode -----------------------*/
/* EVT3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/*EVT3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
void I2C_DeInit(I2C_TypeDef *I2Cx);
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
/*****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* profit the application requirements and constraints:
*
*
* a) First way:
* Using I2C_CheckEvent() function:
* It compares the status registers (STARR1 and STAR2) content to a given event
* (can be the combination of more flags).
* If the current status registers includes the given flags will return SUCCESS.
* and if the current status registers miss flags will returns ERROR.
* - When to use:
* - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (CH32V03RM).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs besides to the monitored error,
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* in corrupted state. it is suggeted to use error interrupts to monitor the error
* events and handle them in IRQ handler.
*
*
* Note:
* The following functions are recommended for error management: :
* - I2C_ITConfig() main function of configure and enable the error interrupts.
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
* to determine which error occurred.
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
* \ I2C_GenerateStop() will be use to clear the error flag and source,
* and return to correct communication status.
*
*
* b) Second way:
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
* - When to use:
*
* - This function is suitable for the same applications above but it
* don't have the limitations of I2C_GetFlagStatus() function .
* The returned value could be compared to events already defined in the
* library (CH32V00x_i2c.h) or to custom values defined by user.
* - This function can be used to monitor the status of multiple flags simultaneously.
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to
* accept the event according to the user's needs (when all event flags are set and
* no other flags are set, or only when the required flags are set)
*
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* c) Third way:
* Using the function I2C_GetFlagStatus() get the status of
* one single flag .
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed .
*
* - Limitations:
* - Call this function to access the status register. Some flag bits may be cleared.
* - Function may need to be called twice or more in order to monitor one single event.
*/
/*********************************************************
*
* a) Basic state monitoring(First way)
********************************************************
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/*********************************************************
*
* b) Advanced state monitoring(Second way:)
********************************************************
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/*********************************************************
*
* c) Flag-based state monitoring(Third way)
*********************************************************
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V00x_I2C_H */

98
Peripheral/inc/ch32v00x_iwdg.h
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@ -1,48 +1,50 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_iwdg.h * File Name : ch32v00x_iwdg.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* IWDG firmware library. * IWDG firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_IWDG_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_IWDG_H *******************************************************************************/
#ifndef __CH32V00x_IWDG_H
#ifdef __cplusplus #define __CH32V00x_IWDG_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* IWDG_WriteAccess */ #include <ch32v00x.h>
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) /* IWDG_WriteAccess */
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
/* IWDG_prescaler */ #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01) /* IWDG_prescaler */
#define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_256 ((uint8_t)0x06) #define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
/* IWDG_Flag */ #define IWDG_Prescaler_256 ((uint8_t)0x06)
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002) /* IWDG_Flag */
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); #define IWDG_FLAG_RVU ((uint16_t)0x0002)
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload); void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_ReloadCounter(void); void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_Enable(void); void IWDG_SetReload(uint16_t Reload);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
#ifdef __cplusplus FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
}
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_IWDG_H */ #endif
#endif /* __CH32V00x_IWDG_H */

120
Peripheral/inc/ch32v00x_misc.h
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@ -1,46 +1,74 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_misc.h * File Name : ch32v00x_misc.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2023/12/26
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* miscellaneous firmware library functions. * miscellaneous firmware library functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00X_MISC_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00X_MISC_H *******************************************************************************/
#ifndef __CH32V00X_MISC_H
#ifdef __cplusplus #define __CH32V00X_MISC_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* NVIC Init Structure definition */ #include <ch32v00x.h>
typedef struct
{ /* CSR_INTSYSCR_INEST_definition */
uint8_t NVIC_IRQChannel; #define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
uint8_t NVIC_IRQChannelPreemptionPriority; #define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd; /* Check the configuration of CSR(0x804) in the startup file(.S)
} NVIC_InitTypeDef; * interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6] - Sub priority
/* Preemption_Priority_Group */ * bit[5:0] - Reserve
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) * interrupt nesting disable(CSR-0x804 bit1 = 0)
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) * priority - bit[7:6] - Sub priority
#define NVIC_PriorityGroup_2 ((uint32_t)0x02) * bit[5:0] - Reserve
#define NVIC_PriorityGroup_3 ((uint32_t)0x03) */
#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
#ifndef INTSYSCR_INEST
#define INTSYSCR_INEST INTSYSCR_INEST_EN
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); #endif
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
/* NVIC Init Structure definition
#ifdef __cplusplus * interrupt nesting enable(CSR-0x804 bit1 = 1)
} * NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
#endif * NVIC_IRQChannelSubPriority - range from 0 to 1.
*
#endif /* __CH32V00x_MISC_H */ * interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Preemption_Priority_Group */
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
#else
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#endif
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
#ifdef __cplusplus
}
#endif
#endif /* __CH32V00x_MISC_H */

104
Peripheral/inc/ch32v00x_opa.h
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@ -1,51 +1,53 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_opa.h * File Name : ch32v00x_opa.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* OPA firmware library. * OPA firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_OPA_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_OPA_H *******************************************************************************/
#ifndef __CH32V00x_OPA_H
#ifdef __cplusplus #define __CH32V00x_OPA_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include "ch32v00x.h" #endif
/* OPA PSEL enumeration */ #include "ch32v00x.h"
typedef enum
{ /* OPA PSEL enumeration */
CHP0 = 0, typedef enum
CHP1 {
} OPA_PSEL_TypeDef; CHP0 = 0,
CHP1
/* OPA NSEL enumeration */ } OPA_PSEL_TypeDef;
typedef enum
{ /* OPA NSEL enumeration */
CHN0 = 0, typedef enum
CHN1 {
} OPA_NSEL_TypeDef; CHN0 = 0,
CHN1
} OPA_NSEL_TypeDef;
/* OPA Init Structure definition */
typedef struct
{ /* OPA Init Structure definition */
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ typedef struct
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ {
} OPA_InitTypeDef; OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
void OPA_DeInit(void); } OPA_InitTypeDef;
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct);
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); void OPA_DeInit(void);
void OPA_Cmd(FunctionalState NewState); void OPA_Init(OPA_InitTypeDef *OPA_InitStruct);
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct);
#ifdef __cplusplus void OPA_Cmd(FunctionalState NewState);
}
#endif #ifdef __cplusplus
}
#endif #endif
#endif

136
Peripheral/inc/ch32v00x_pwr.h
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@ -1,67 +1,69 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_pwr.h * File Name : ch32v00x_pwr.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the PWR * Description : This file contains all the functions prototypes for the PWR
* firmware library. * firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_PWR_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_PWR_H *******************************************************************************/
#ifndef __CH32V00x_PWR_H
#ifdef __cplusplus #define __CH32V00x_PWR_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* PVD_detection_level */ #include <ch32v00x.h>
#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000)
#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020) /* PVD_detection_level */
#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040) #define PWR_PVDLevel_2V9 ((uint32_t)0x00000000)
#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060) #define PWR_PVDLevel_3V1 ((uint32_t)0x00000020)
#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080) #define PWR_PVDLevel_3V3 ((uint32_t)0x00000040)
#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0) #define PWR_PVDLevel_3V5 ((uint32_t)0x00000060)
#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0) #define PWR_PVDLevel_3V7 ((uint32_t)0x00000080)
#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0) #define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0)
/* PWR_AWU_Prescaler */ #define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0)
#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000)
#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002) /* PWR_AWU_Prescaler */
#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003) #define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000)
#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004) #define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002)
#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005) #define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003)
#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006) #define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004)
#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007) #define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005)
#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008) #define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006)
#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009) #define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007)
#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A) #define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008)
#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B) #define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009)
#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C) #define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A)
#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D) #define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B)
#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E) #define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C)
#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F) #define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D)
#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E)
/* STOP_mode_entry */ #define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F)
#define PWR_STANDBYEntry_WFI ((uint8_t)0x01)
#define PWR_STANDBYEntry_WFE ((uint8_t)0x02) /* STOP_mode_entry */
#define PWR_STANDBYEntry_WFI ((uint8_t)0x01)
/* PWR_Flag */ #define PWR_STANDBYEntry_WFE ((uint8_t)0x02)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
/* PWR_Flag */
void PWR_DeInit(void); #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_DeInit(void);
void PWR_AutoWakeUpCmd(FunctionalState NewState); void PWR_PVDCmd(FunctionalState NewState);
void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler); void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_AWU_SetWindowValue(uint8_t WindowValue); void PWR_AutoWakeUpCmd(FunctionalState NewState);
void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry); void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); void PWR_AWU_SetWindowValue(uint8_t WindowValue);
void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry);
#ifdef __cplusplus FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
}
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_PWR_H */ #endif
#endif /* __CH32V00x_PWR_H */

306
Peripheral/inc/ch32v00x_rcc.h
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/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_rcc.h * File Name : ch32v00x_rcc.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the RCC firmware functions. * Description : This file provides all the RCC firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_RCC_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_RCC_H *******************************************************************************/
#ifndef __CH32V00x_RCC_H
#ifdef __cplusplus #define __CH32V00x_RCC_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* RCC_Exported_Types */ #include <ch32v00x.h>
typedef struct
{ /* RCC_Exported_Types */
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ typedef struct
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ {
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
} RCC_ClocksTypeDef; uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
/* HSE_configuration */ } RCC_ClocksTypeDef;
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000) /* HSE_configuration */
#define RCC_HSE_Bypass ((uint32_t)0x00040000) #define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
/* PLL_entry_clock_source */ #define RCC_HSE_Bypass ((uint32_t)0x00040000)
#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000) /* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
/* System_clock_source */ #define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) /* System_clock_source */
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
/* AHB_clock_source */ #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) /* AHB_clock_source */
#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) #define RCC_SYSCLK_Div3 ((uint32_t)0x00000020)
#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) #define RCC_SYSCLK_Div4 ((uint32_t)0x00000030)
#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) #define RCC_SYSCLK_Div5 ((uint32_t)0x00000040)
#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) #define RCC_SYSCLK_Div6 ((uint32_t)0x00000050)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) #define RCC_SYSCLK_Div7 ((uint32_t)0x00000060)
#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) #define RCC_SYSCLK_Div8 ((uint32_t)0x00000070)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) #define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) #define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
/* RCC_Interrupt_source */ #define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_HSIRDY ((uint8_t)0x04) /* RCC_Interrupt_source */
#define RCC_IT_HSERDY ((uint8_t)0x08) #define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_PLLRDY ((uint8_t)0x10) #define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_CSS ((uint8_t)0x80) #define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
/* ADC_clock_source */ #define RCC_IT_CSS ((uint8_t)0x80)
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00000800) /* ADC_clock_source */
#define RCC_PCLK2_Div6 ((uint32_t)0x00001000) #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div8 ((uint32_t)0x00001800) #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div12 ((uint32_t)0x00009000) #define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div16 ((uint32_t)0x00009100) #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
#define RCC_PCLK2_Div24 ((uint32_t)0x0000B000) #define RCC_PCLK2_Div12 ((uint32_t)0x0000A000)
#define RCC_PCLK2_Div32 ((uint32_t)0x0000B100) #define RCC_PCLK2_Div16 ((uint32_t)0x0000E000)
#define RCC_PCLK2_Div48 ((uint32_t)0x0000D000) #define RCC_PCLK2_Div24 ((uint32_t)0x0000A800)
#define RCC_PCLK2_Div64 ((uint32_t)0x0000D100) #define RCC_PCLK2_Div32 ((uint32_t)0x0000E800)
#define RCC_PCLK2_Div96 ((uint32_t)0x0000F000) #define RCC_PCLK2_Div48 ((uint32_t)0x0000B000)
#define RCC_PCLK2_Div128 ((uint32_t)0x0000F100) #define RCC_PCLK2_Div64 ((uint32_t)0x0000F000)
#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
/* AHB_peripheral */ #define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) /* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
/* APB2_peripheral */ #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) /* APB2_peripheral */
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
/* APB1_peripheral */ #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) /* APB1_peripheral */
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
/* Clock_source_to_output_on_MCO_pin */ #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04) /* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_HSI ((uint8_t)0x05) #define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_HSE ((uint8_t)0x06) #define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_PLLCLK ((uint8_t)0x07) #define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
/* RCC_Flag */ #define RCC_MCO_PLLCLK ((uint8_t)0x07)
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31) /* RCC_Flag */
#define RCC_FLAG_PLLRDY ((uint8_t)0x39) #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61) #define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PINRST ((uint8_t)0x7A) #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PORRST ((uint8_t)0x7B) #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C) #define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
/* SysTick_clock_source */ #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) /* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
void RCC_DeInit(void); #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void); void RCC_DeInit(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_HSEConfig(uint32_t RCC_HSE);
void RCC_HSICmd(FunctionalState NewState); ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_PLLCmd(FunctionalState NewState); void RCC_HSICmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); void RCC_PLLConfig(uint32_t RCC_PLLSource);
uint8_t RCC_GetSYSCLKSource(void); void RCC_PLLCmd(FunctionalState NewState);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); uint8_t RCC_GetSYSCLKSource(void);
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_LSICmd(FunctionalState NewState); void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_LSICmd(FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState); void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_ClearFlag(void); void RCC_MCOConfig(uint8_t RCC_MCO);
ITStatus RCC_GetITStatus(uint8_t RCC_IT); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearITPendingBit(uint8_t RCC_IT); void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
#ifdef __cplusplus void RCC_ClearITPendingBit(uint8_t RCC_IT);
}
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_RCC_H */ #endif
#endif /* __CH32V00x_RCC_H */

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Peripheral/inc/ch32v00x_spi.h
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@ -1,152 +1,155 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_spi.h * File Name : ch32v00x_spi.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* SPI firmware library. * SPI firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_SPI_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_SPI_H *******************************************************************************/
#ifndef __CH32V00x_SPI_H
#ifdef __cplusplus #define __CH32V00x_SPI_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* SPI Init structure definition */ #include <ch32v00x.h>
typedef struct
{ /* SPI Init structure definition */
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. typedef struct
This parameter can be a value of @ref SPI_data_direction */ {
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
uint16_t SPI_Mode; /* Specifies the SPI operating mode. This parameter can be a value of @ref SPI_data_direction */
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
uint16_t SPI_DataSize; /* Specifies the SPI data size. This parameter can be a value of @ref SPI_mode */
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_DataSize; /* Specifies the SPI data size.
uint16_t SPI_CPOL; /* Specifies the serial clock steady state. This parameter can be a value of @ref SPI_data_size */
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_Clock_Polarity */
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by This parameter can be a value of @ref SPI_Clock_Phase */
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */ uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be This parameter can be a value of @ref SPI_Slave_Select_management */
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler. uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
@note The communication clock is derived from the master used to configure the transmit and receive SCK clock.
clock. The slave clock does not need to be set. */ This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */ clock. The slave clock does not need to be set. */
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB bit. */
} SPI_InitTypeDef;
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
/* SPI_data_direction */ } SPI_InitTypeDef;
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) /* SPI_data_direction */
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
/* SPI_mode */ #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000) /* SPI_mode */
#define SPI_Mode_Master ((uint16_t)0x0104)
/* SPI_data_size */ #define SPI_Mode_Slave ((uint16_t)0x0000)
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000) /* SPI_data_size */
#define SPI_DataSize_16b ((uint16_t)0x0800)
/* SPI_Clock_Polarity */ #define SPI_DataSize_8b ((uint16_t)0x0000)
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002) /* SPI_Clock_Polarity */
#define SPI_CPOL_Low ((uint16_t)0x0000)
/* SPI_Clock_Phase */ #define SPI_CPOL_High ((uint16_t)0x0002)
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001) /* SPI_Clock_Phase */
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
/* SPI_Slave_Select_management */ #define SPI_CPHA_2Edge ((uint16_t)0x0001)
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000) /* SPI_Slave_Select_management */
#define SPI_NSS_Soft ((uint16_t)0x0200)
/* SPI_BaudRate_Prescaler */ #define SPI_NSS_Hard ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) /* SPI_BaudRate_Prescaler */
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
/* SPI_MSB transmission */ #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
/* SPI_MSB_LSB transmission */
/* SPI_I2S_DMA_transfer_requests */ #define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
/* SPI_I2S_DMA_transfer_requests */
/* SPI_NSS_internal_software_management */ #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
/* SPI_NSS_internal_software_management */
/* SPI_CRC_Transmit_Receive */ #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_CRC_Tx ((uint8_t)0x00) #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
#define SPI_CRC_Rx ((uint8_t)0x01)
/* SPI_CRC_Transmit_Receive */
/* SPI_direction_transmit_receive */ #define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_Direction_Rx ((uint16_t)0xBFFF) #define SPI_CRC_Rx ((uint8_t)0x01)
#define SPI_Direction_Tx ((uint16_t)0x4000)
/* SPI_direction_transmit_receive */
/* SPI_I2S_interrupts_definition */ #define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_I2S_IT_TXE ((uint8_t)0x71) #define SPI_Direction_Tx ((uint16_t)0x4000)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50) /* SPI_I2S_interrupts_definition */
#define SPI_I2S_IT_OVR ((uint8_t)0x56) #define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_IT_MODF ((uint8_t)0x55) #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_IT_CRCERR ((uint8_t)0x54) #define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define I2S_IT_UDR ((uint8_t)0x53) #define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
/* SPI_I2S_flags_definition */ #define SPI_IT_CRCERR ((uint8_t)0x54)
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) #define I2S_IT_UDR ((uint8_t)0x53)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) /* SPI_I2S_flags_definition */
#define I2S_FLAG_UDR ((uint16_t)0x0008) #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010) #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define SPI_FLAG_MODF ((uint16_t)0x0020) #define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) #define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
void SPI_I2S_DeInit(SPI_TypeDef *SPIx); #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
void SPI_TransmitCRC(SPI_TypeDef *SPIx); void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); void SPI_TransmitCRC(SPI_TypeDef *SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
#ifdef __cplusplus ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
} void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
#endif
#ifdef __cplusplus
#endif /*__CH32V00x_SPI_H */ }
#endif
#endif /*__CH32V00x_SPI_H */

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Peripheral/inc/ch32v00x_tim.h
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Peripheral/inc/ch32v00x_usart.h
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@ -1,185 +1,187 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_usart.h * File Name : ch32v00x_usart.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* USART firmware library. * USART firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_USART_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_USART_H *******************************************************************************/
#ifndef __CH32V00x_USART_H
#ifdef __cplusplus #define __CH32V00x_USART_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* USART Init Structure definition */ #include <ch32v00x.h>
typedef struct
{ /* USART Init Structure definition */
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. typedef struct
The baud rate is computed using the following formula: {
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. This parameter can be a value of @ref USART_Word_Length */
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
uint16_t USART_Parity; /* Specifies the parity mode. This parameter can be a value of @ref USART_Stop_Bits */
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted uint16_t USART_Parity; /* Specifies the parity mode.
at the MSB position of the transmitted data (9th bit when This parameter can be a value of @ref USART_Parity
the word length is set to 9 data bits; 8th bit when the @note When parity is enabled, the computed parity is inserted
word length is set to 8 data bits). */ at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. word length is set to 8 data bits). */
This parameter can be a value of @ref USART_Mode */
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled This parameter can be a value of @ref USART_Mode */
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */ uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
} USART_InitTypeDef; or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
/* USART Clock Init Structure definition */ } USART_InitTypeDef;
typedef struct
{ /* USART Clock Init Structure definition */
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. typedef struct
This parameter can be a value of @ref USART_Clock */ {
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. This parameter can be a value of @ref USART_Clock */
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. This parameter can be a value of @ref USART_Clock_Polarity */
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted This parameter can be a value of @ref USART_Clock_Phase */
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */ uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
} USART_ClockInitTypeDef; data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
/* USART_Word_Length */ } USART_ClockInitTypeDef;
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000) /* USART_Word_Length */
#define USART_WordLength_8b ((uint16_t)0x0000)
/* USART_Stop_Bits */ #define USART_WordLength_9b ((uint16_t)0x1000)
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000) /* USART_Stop_Bits */
#define USART_StopBits_2 ((uint16_t)0x2000) #define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_1_5 ((uint16_t)0x3000) #define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
/* USART_Parity */ #define USART_StopBits_1_5 ((uint16_t)0x3000)
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400) /* USART_Parity */
#define USART_Parity_Odd ((uint16_t)0x0600) #define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
/* USART_Mode */ #define USART_Parity_Odd ((uint16_t)0x0600)
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008) /* USART_Mode */
#define USART_Mode_Rx ((uint16_t)0x0004)
/* USART_Hardware_Flow_Control */ #define USART_Mode_Tx ((uint16_t)0x0008)
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) /* USART_Hardware_Flow_Control */
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) #define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
/* USART_Clock */ #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800) /* USART_Clock */
#define USART_Clock_Disable ((uint16_t)0x0000)
/* USART_Clock_Polarity */ #define USART_Clock_Enable ((uint16_t)0x0800)
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400) /* USART_Clock_Polarity */
#define USART_CPOL_Low ((uint16_t)0x0000)
/* USART_Clock_Phase */ #define USART_CPOL_High ((uint16_t)0x0400)
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200) /* USART_Clock_Phase */
#define USART_CPHA_1Edge ((uint16_t)0x0000)
/* USART_Last_Bit */ #define USART_CPHA_2Edge ((uint16_t)0x0200)
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100) /* USART_Last_Bit */
#define USART_LastBit_Disable ((uint16_t)0x0000)
/* USART_Interrupt_definition */ #define USART_LastBit_Enable ((uint16_t)0x0100)
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727) /* USART_Interrupt_definition */
#define USART_IT_TC ((uint16_t)0x0626) #define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_RXNE ((uint16_t)0x0525) #define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_ORE_RX ((uint16_t)0x0325) #define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_IDLE ((uint16_t)0x0424) #define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_LBD ((uint16_t)0x0846) #define USART_IT_ORE_RX ((uint16_t)0x0325)
#define USART_IT_CTS ((uint16_t)0x096A) #define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_ERR ((uint16_t)0x0060) #define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_ORE_ER ((uint16_t)0x0360) #define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_NE ((uint16_t)0x0260) #define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_FE ((uint16_t)0x0160) #define USART_IT_ORE_ER ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_ORE USART_IT_ORE_ER #define USART_IT_FE ((uint16_t)0x0160)
/* USART_DMA_Requests */ #define USART_IT_ORE USART_IT_ORE_ER
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040) /* USART_DMA_Requests */
#define USART_DMAReq_Tx ((uint16_t)0x0080)
/* USART_WakeUp_methods */ #define USART_DMAReq_Rx ((uint16_t)0x0040)
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800) /* USART_WakeUp_methods */
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
/* USART_LIN_Break_Detection_Length */ #define USART_WakeUp_AddressMark ((uint16_t)0x0800)
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) /* USART_LIN_Break_Detection_Length */
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
/* USART_IrDA_Low_Power */ #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000) /* USART_IrDA_Low_Power */
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
/* USART_Flags */ #define USART_IrDAMode_Normal ((uint16_t)0x0000)
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100) /* USART_Flags */
#define USART_FLAG_TXE ((uint16_t)0x0080) #define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_TC ((uint16_t)0x0040) #define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_RXNE ((uint16_t)0x0020) #define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_IDLE ((uint16_t)0x0010) #define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_ORE ((uint16_t)0x0008) #define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_NE ((uint16_t)0x0004) #define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_FE ((uint16_t)0x0002) #define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_PE ((uint16_t)0x0001) #define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
void USART_DeInit(USART_TypeDef *USARTx); #define USART_FLAG_PE ((uint16_t)0x0001)
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
void USART_StructInit(USART_InitTypeDef *USART_InitStruct); void USART_DeInit(USART_TypeDef *USARTx);
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
uint16_t USART_ReceiveData(USART_TypeDef *USARTx); void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SendBreak(USART_TypeDef *USARTx); void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); void USART_SendBreak(USART_TypeDef *USARTx);
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
#ifdef __cplusplus void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
}
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_USART_H */ #endif
#endif /* __CH32V00x_USART_H */

80
Peripheral/inc/ch32v00x_wwdg.h
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@ -1,39 +1,41 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_wwdg.h * File Name : ch32v00x_wwdg.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file contains all the functions prototypes for the WWDG * Description : This file contains all the functions prototypes for the WWDG
* firmware library. * firmware library.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#ifndef __CH32V00x_WWDG_H * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#define __CH32V00x_WWDG_H *******************************************************************************/
#ifndef __CH32V00x_WWDG_H
#ifdef __cplusplus #define __CH32V00x_WWDG_H
extern "C" {
#endif #ifdef __cplusplus
extern "C" {
#include <ch32v00x.h> #endif
/* WWDG_Prescaler */ #include <ch32v00x.h>
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080) /* WWDG_Prescaler */
#define WWDG_Prescaler_4 ((uint32_t)0x00000100) #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180) #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
void WWDG_DeInit(void); #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue); void WWDG_DeInit(void);
void WWDG_EnableIT(void); void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetCounter(uint8_t Counter); void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_Enable(uint8_t Counter); void WWDG_EnableIT(void);
FlagStatus WWDG_GetFlagStatus(void); void WWDG_SetCounter(uint8_t Counter);
void WWDG_ClearFlag(void); void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void);
#ifdef __cplusplus void WWDG_ClearFlag(void);
}
#endif #ifdef __cplusplus
}
#endif /* __CH32V00x_WWDG_H */ #endif
#endif /* __CH32V00x_WWDG_H */

2118
Peripheral/src/ch32v00x_adc.c
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215
Peripheral/src/ch32v00x_dbgmcu.c
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@ -1,99 +1,116 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_dbgmcu.c * File Name : ch32v00x_dbgmcu.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the DBGMCU firmware functions. * Description : This file provides all the DBGMCU firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
****************************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_dbgmcu.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_dbgmcu.h>
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
/********************************************************************* #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
* @fn DBGMCU_GetREVID
* /*********************************************************************
* @brief Returns the device revision identifier. * @fn DBGMCU_GetREVID
* *
* @return Revision identifier. * @brief Returns the device revision identifier.
*/ *
uint32_t DBGMCU_GetREVID(void) * @return Revision identifier.
{ */
return ((*(uint32_t *)0x1FFFF7C4) >> 16); uint32_t DBGMCU_GetREVID(void)
} {
return ((*(uint32_t *)0x1FFFF7C4) >> 16);
/********************************************************************* }
* @fn DBGMCU_GetDEVID
* /*********************************************************************
* @brief Returns the device identifier. * @fn DBGMCU_GetDEVID
* *
* @return Device identifier. * @brief Returns the device identifier.
*/ *
uint32_t DBGMCU_GetDEVID(void) * @return Device identifier.
{ */
return ((*(uint32_t *)0x1FFFF7C4) & IDCODE_DEVID_MASK); uint32_t DBGMCU_GetDEVID(void)
} {
return ((*(uint32_t *)0x1FFFF7C4) & IDCODE_DEVID_MASK);
/********************************************************************* }
* @fn __get_DEBUG_CR
* /*********************************************************************
* @brief Return the DEBUGE Control Register * @fn __get_DEBUG_CR
* *
* @return DEBUGE Control value * @brief Return the DEBUGE Control Register
*/ *
uint32_t __get_DEBUG_CR(void) * @return DEBUGE Control value
{ */
uint32_t result; uint32_t __get_DEBUG_CR(void)
{
__asm volatile("csrr %0,""0x7C0" : "=r"(result)); uint32_t result;
return (result);
} __asm volatile("csrr %0,""0x7C0" : "=r"(result));
return (result);
/********************************************************************* }
* @fn __set_DEBUG_CR
* /*********************************************************************
* @brief Set the DEBUGE Control Register * @fn __set_DEBUG_CR
* *
* @param value - set DEBUGE Control value * @brief Set the DEBUGE Control Register
* *
* @return none * @param value - set DEBUGE Control value
*/ *
void __set_DEBUG_CR(uint32_t value) * @return none
{ */
__asm volatile("csrw 0x7C0, %0" : : "r"(value)); void __set_DEBUG_CR(uint32_t value)
} {
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
}
/*********************************************************************
* @fn DBGMCU_Config
* /*********************************************************************
* @brief Configures the specified peripheral and low power mode behavior * @fn DBGMCU_Config
* when the MCU under Debug mode. *
* * @brief Configures the specified peripheral and low power mode behavior
* @param DBGMCU_Periph - specifies the peripheral and low power mode. * when the MCU under Debug mode.
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted *
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted * @param DBGMCU_Periph - specifies the peripheral and low power mode.
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
* NewState - ENABLE or DISABLE. * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
* * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
* @return none * NewState - ENABLE or DISABLE.
*/ *
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) * @return none
{ */
uint32_t val; void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
if(NewState != DISABLE) uint32_t val;
{
__set_DEBUG_CR(DBGMCU_Periph); if(NewState != DISABLE)
} {
else __set_DEBUG_CR(DBGMCU_Periph);
{ }
val = __get_DEBUG_CR(); else
val &= ~(uint32_t)DBGMCU_Periph; {
__set_DEBUG_CR(val); val = __get_DEBUG_CR();
} val &= ~(uint32_t)DBGMCU_Periph;
__set_DEBUG_CR(val);
} }
}
/*********************************************************************
* @fn DBGMCU_GetCHIPID
*
* @brief Returns the CHIP identifier.
*
* @return Device identifier.
* ChipID List-
* CH32V003F4P6-0x003005x0
* CH32V003F4U6-0x003105x0
* CH32V003A4M6-0x003205x0
* CH32V003J4M6-0x003305x0
*/
uint32_t DBGMCU_GetCHIPID( void )
{
return( *( uint32_t * )0x1FFFF7C4 );
}

830
Peripheral/src/ch32v00x_dma.c
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@ -1,414 +1,416 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_dma.c * File Name : ch32v00x_dma.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the DMA firmware functions. * Description : This file provides all the DMA firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_dma.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#include <ch32v00x_rcc.h> *******************************************************************************/
#include <ch32v00x_dma.h>
/* DMA1 Channelx interrupt pending bit masks */ #include <ch32v00x_rcc.h>
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) /* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
/* DMA2 FLAG mask */ #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
#define FLAG_Mask ((uint32_t)0x10000000)
/* DMA2 FLAG mask */
/* DMA registers Masks */ #define FLAG_Mask ((uint32_t)0x10000000)
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/* DMA registers Masks */
/********************************************************************* #define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
* @fn DMA_DeInit
* /*********************************************************************
* @brief Deinitializes the DMAy Channelx registers to their default * @fn DMA_DeInit
* reset values. *
* * @brief Deinitializes the DMAy Channelx registers to their default
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * reset values.
* 1 to 7 for DMA1 to select the DMA Channel. *
* * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* @return none * 1 to 7 for DMA1 to select the DMA Channel.
*/ *
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) * @return none
{ */
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
DMAy_Channelx->CFGR = 0; {
DMAy_Channelx->CNTR = 0; DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
DMAy_Channelx->PADDR = 0; DMAy_Channelx->CFGR = 0;
DMAy_Channelx->MADDR = 0; DMAy_Channelx->CNTR = 0;
if(DMAy_Channelx == DMA1_Channel1) DMAy_Channelx->PADDR = 0;
{ DMAy_Channelx->MADDR = 0;
DMA1->INTFCR |= DMA1_Channel1_IT_Mask; if(DMAy_Channelx == DMA1_Channel1)
} {
else if(DMAy_Channelx == DMA1_Channel2) DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
{ }
DMA1->INTFCR |= DMA1_Channel2_IT_Mask; else if(DMAy_Channelx == DMA1_Channel2)
} {
else if(DMAy_Channelx == DMA1_Channel3) DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
{ }
DMA1->INTFCR |= DMA1_Channel3_IT_Mask; else if(DMAy_Channelx == DMA1_Channel3)
} {
else if(DMAy_Channelx == DMA1_Channel4) DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
{ }
DMA1->INTFCR |= DMA1_Channel4_IT_Mask; else if(DMAy_Channelx == DMA1_Channel4)
} {
else if(DMAy_Channelx == DMA1_Channel5) DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
{ }
DMA1->INTFCR |= DMA1_Channel5_IT_Mask; else if(DMAy_Channelx == DMA1_Channel5)
} {
else if(DMAy_Channelx == DMA1_Channel6) DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
{ }
DMA1->INTFCR |= DMA1_Channel6_IT_Mask; else if(DMAy_Channelx == DMA1_Channel6)
} {
else if(DMAy_Channelx == DMA1_Channel7) DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
{ }
DMA1->INTFCR |= DMA1_Channel7_IT_Mask; else if(DMAy_Channelx == DMA1_Channel7)
} {
} DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
}
/********************************************************************* }
* @fn DMA_Init
* /*********************************************************************
* @brief Initializes the DMAy Channelx according to the specified * @fn DMA_Init
* parameters in the DMA_InitStruct. *
* * @brief Initializes the DMAy Channelx according to the specified
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * parameters in the DMA_InitStruct.
* 1 to 7 for DMA1 to select the DMA Channel. *
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* contains the configuration information for the specified DMA Channel. * 1 to 7 for DMA1 to select the DMA Channel.
* * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* @return none * contains the configuration information for the specified DMA Channel.
*/ *
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) * @return none
{ */
uint32_t tmpreg = 0; void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
{
tmpreg = DMAy_Channelx->CFGR; uint32_t tmpreg = 0;
tmpreg &= CFGR_CLEAR_Mask;
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | tmpreg = DMAy_Channelx->CFGR;
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | tmpreg &= CFGR_CLEAR_Mask;
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMAy_Channelx->CFGR = tmpreg; DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; DMAy_Channelx->CFGR = tmpreg;
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
} DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
/********************************************************************* }
* @fn DMA_StructInit
* /*********************************************************************
* @brief Fills each DMA_InitStruct member with its default value. * @fn DMA_StructInit
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @brief Fills each DMA_InitStruct member with its default value.
* 1 to 7 for DMA1 to select the DMA Channel. *
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* contains the configuration information for the specified DMA Channel. * 1 to 7 for DMA1 to select the DMA Channel.
* * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* @return none * contains the configuration information for the specified DMA Channel.
*/ *
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) * @return none
{ */
DMA_InitStruct->DMA_PeripheralBaseAddr = 0; void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
DMA_InitStruct->DMA_MemoryBaseAddr = 0; {
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
DMA_InitStruct->DMA_BufferSize = 0; DMA_InitStruct->DMA_MemoryBaseAddr = 0;
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; DMA_InitStruct->DMA_BufferSize = 0;
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStruct->DMA_Priority = DMA_Priority_Low; DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
} DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
/********************************************************************* }
* @fn DMA_Cmd
* /*********************************************************************
* @brief Enables or disables the specified DMAy Channelx. * @fn DMA_Cmd
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @brief Enables or disables the specified DMAy Channelx.
* 1 to 7 for DMA1 to select the DMA Channel. *
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE). * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* * 1 to 7 for DMA1 to select the DMA Channel.
* @return none * NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*/ *
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) * @return none
{ */
if(NewState != DISABLE) void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
{ {
DMAy_Channelx->CFGR |= DMA_CFGR1_EN; if(NewState != DISABLE)
} {
else DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
{ }
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); else
} {
} DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
}
/********************************************************************* }
* @fn DMA_ITConfig
* /*********************************************************************
* @brief Enables or disables the specified DMAy Channelx interrupts. * @fn DMA_ITConfig
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @brief Enables or disables the specified DMAy Channelx interrupts.
* 1 to 7 for DMA1 to select the DMA Channel. *
* DMA_IT - specifies the DMA interrupts sources to be enabled * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* or disabled. * 1 to 7 for DMA1 to select the DMA Channel.
* DMA_IT_TC - Transfer complete interrupt mask * DMA_IT - specifies the DMA interrupts sources to be enabled
* DMA_IT_HT - Half transfer interrupt mask * or disabled.
* DMA_IT_TE - Transfer error interrupt mask * DMA_IT_TC - Transfer complete interrupt mask
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE). * DMA_IT_HT - Half transfer interrupt mask
* * DMA_IT_TE - Transfer error interrupt mask
* @return none * NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*/ *
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) * @return none
{ */
if(NewState != DISABLE) void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{ {
DMAy_Channelx->CFGR |= DMA_IT; if(NewState != DISABLE)
} {
else DMAy_Channelx->CFGR |= DMA_IT;
{ }
DMAy_Channelx->CFGR &= ~DMA_IT; else
} {
} DMAy_Channelx->CFGR &= ~DMA_IT;
}
/********************************************************************* }
* @fn DMA_SetCurrDataCounter
* /*********************************************************************
* @brief Sets the number of data units in the current DMAy Channelx transfer. * @fn DMA_SetCurrDataCounter
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @brief Sets the number of data units in the current DMAy Channelx transfer.
* 1 to 7 for DMA1 to select the DMA Channel. *
* DataNumber - The number of data units in the current DMAy Channelx * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* transfer. * 1 to 7 for DMA1 to select the DMA Channel.
* * DataNumber - The number of data units in the current DMAy Channelx
* @return none * transfer.
*/ *
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) * @return none
{ */
DMAy_Channelx->CNTR = DataNumber; void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
} {
DMAy_Channelx->CNTR = DataNumber;
/********************************************************************* }
* @fn DMA_GetCurrDataCounter
* /*********************************************************************
* @brief Returns the number of remaining data units in the current * @fn DMA_GetCurrDataCounter
* DMAy Channelx transfer. *
* * @brief Returns the number of remaining data units in the current
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * DMAy Channelx transfer.
* 1 to 7 for DMA1 to select the DMA Channel. *
* * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* @return DataNumber - The number of remaining data units in the current * 1 to 7 for DMA1 to select the DMA Channel.
* DMAy Channelx transfer. *
*/ * @return DataNumber - The number of remaining data units in the current
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) * DMAy Channelx transfer.
{ */
return ((uint16_t)(DMAy_Channelx->CNTR)); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
} {
return ((uint16_t)(DMAy_Channelx->CNTR));
/********************************************************************* }
* @fn DMA_GetFlagStatus
* /*********************************************************************
* @brief Checks whether the specified DMAy Channelx flag is set or not. * @fn DMA_GetFlagStatus
* *
* @param DMAy_FLAG - specifies the flag to check. * @brief Checks whether the specified DMAy Channelx flag is set or not.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag. *
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. * @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. * DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag. * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. * DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag. * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. * DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag. * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. * DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag. * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. * DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag. * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. * DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag. * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. * DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* @return The new state of DMAy_FLAG (SET or RESET). * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
*/ *
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) * @return The new state of DMAy_FLAG (SET or RESET).
{ */
FlagStatus bitstatus = RESET; FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
uint32_t tmpreg = 0; {
FlagStatus bitstatus = RESET;
tmpreg = DMA1->INTFR; uint32_t tmpreg = 0;
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) tmpreg = DMA1->INTFR;
{
bitstatus = SET; if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
} {
else bitstatus = SET;
{ }
bitstatus = RESET; else
} {
bitstatus = RESET;
return bitstatus; }
}
return bitstatus;
/********************************************************************* }
* @fn DMA_ClearFlag
* /*********************************************************************
* @brief Clears the DMAy Channelx's pending flags. * @fn DMA_ClearFlag
* *
* @param DMAy_FLAG - specifies the flag to check. * @brief Clears the DMAy Channelx's pending flags.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag. *
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. * @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. * DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag. * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. * DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag. * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. * DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag. * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. * DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag. * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. * DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag. * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. * DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag. * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. * DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* @return none * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
*/ *
void DMA_ClearFlag(uint32_t DMAy_FLAG) * @return none
{ */
void DMA_ClearFlag(uint32_t DMAy_FLAG)
DMA1->INTFCR = DMAy_FLAG; {
} DMA1->INTFCR = DMAy_FLAG;
/********************************************************************* }
* @fn DMA_GetITStatus
* /*********************************************************************
* @brief Checks whether the specified DMAy Channelx interrupt has * @fn DMA_GetITStatus
* occurred or not. *
* * @brief Checks whether the specified DMAy Channelx interrupt has
* @param DMAy_IT - specifies the DMAy interrupt source to check. * occurred or not.
* DMA1_IT_GL1 - DMA1 Channel1 global flag. *
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. * @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. * DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag. * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. * DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag. * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. * DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag. * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. * DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag. * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. * DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag. * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. * DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag. * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. * DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* @return The new state of DMAy_IT (SET or RESET). * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
*/ *
ITStatus DMA_GetITStatus(uint32_t DMAy_IT) * @return The new state of DMAy_IT (SET or RESET).
{ */
ITStatus bitstatus = RESET; ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
uint32_t tmpreg = 0; {
ITStatus bitstatus = RESET;
tmpreg = DMA1->INTFR; uint32_t tmpreg = 0;
if((tmpreg & DMAy_IT) != (uint32_t)RESET) tmpreg = DMA1->INTFR;
{
bitstatus = SET; if((tmpreg & DMAy_IT) != (uint32_t)RESET)
} {
else bitstatus = SET;
{ }
bitstatus = RESET; else
} {
return bitstatus; bitstatus = RESET;
} }
return bitstatus;
/********************************************************************* }
* @fn DMA_ClearITPendingBit
* /*********************************************************************
* @brief Clears the DMAy Channelx's interrupt pending bits. * @fn DMA_ClearITPendingBit
* *
* @param DMAy_IT - specifies the DMAy interrupt source to check. * @brief Clears the DMAy Channelx's interrupt pending bits.
* DMA1_IT_GL1 - DMA1 Channel1 global flag. *
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. * @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. * DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag. * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. * DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag. * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. * DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag. * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. * DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag. * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. * DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag. * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. * DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag. * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. * DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* @return none * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
*/ *
void DMA_ClearITPendingBit(uint32_t DMAy_IT) * @return none
{ */
DMA1->INTFCR = DMAy_IT; void DMA_ClearITPendingBit(uint32_t DMAy_IT)
} {
DMA1->INTFCR = DMAy_IT;
}

362
Peripheral/src/ch32v00x_exti.c
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@ -1,180 +1,182 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_exti.c * File Name : ch32v00x_exti.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the EXTI firmware functions. * Description : This file provides all the EXTI firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
***************************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_exti.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
/* No interrupt selected */ #include <ch32v00x_exti.h>
#define EXTI_LINENONE ((uint32_t)0x00000)
/* No interrupt selected */
/********************************************************************* #define EXTI_LINENONE ((uint32_t)0x00000)
* @fn EXTI_DeInit
* /*********************************************************************
* @brief Deinitializes the EXTI peripheral registers to their default * @fn EXTI_DeInit
* reset values. *
* * @brief Deinitializes the EXTI peripheral registers to their default
* @return none. * reset values.
*/ *
void EXTI_DeInit(void) * @return none.
{ */
EXTI->INTENR = 0x00000000; void EXTI_DeInit(void)
EXTI->EVENR = 0x00000000; {
EXTI->RTENR = 0x00000000; EXTI->INTENR = 0x00000000;
EXTI->FTENR = 0x00000000; EXTI->EVENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF; EXTI->RTENR = 0x00000000;
} EXTI->FTENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF;
/********************************************************************* }
* @fn EXTI_Init
* /*********************************************************************
* @brief Initializes the EXTI peripheral according to the specified * @fn EXTI_Init
* parameters in the EXTI_InitStruct. *
* * @brief Initializes the EXTI peripheral according to the specified
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure * parameters in the EXTI_InitStruct.
* *
* @return none. * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
*/ *
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) * @return none.
{ */
uint32_t tmp = 0; void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
{
tmp = (uint32_t)EXTI_BASE; uint32_t tmp = 0;
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{ tmp = (uint32_t)EXTI_BASE;
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; {
tmp += EXTI_InitStruct->EXTI_Mode; EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; tmp += EXTI_InitStruct->EXTI_Mode;
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
{ EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; {
} EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
else EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
{ }
tmp = (uint32_t)EXTI_BASE; else
tmp += EXTI_InitStruct->EXTI_Trigger; {
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; tmp = (uint32_t)EXTI_BASE;
} tmp += EXTI_InitStruct->EXTI_Trigger;
} *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
else }
{ }
tmp += EXTI_InitStruct->EXTI_Mode; else
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; {
} tmp += EXTI_InitStruct->EXTI_Mode;
} *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
}
/********************************************************************* }
* @fn EXTI_StructInit
* /*********************************************************************
* @brief Fills each EXTI_InitStruct member with its reset value. * @fn EXTI_StructInit
* *
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure * @brief Fills each EXTI_InitStruct member with its reset value.
* *
* @return none. * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
*/ *
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) * @return none.
{ */
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; {
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_LineCmd = DISABLE; EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
} EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
/********************************************************************* }
* @fn EXTI_GenerateSWInterrupt
* /*********************************************************************
* @brief Generates a Software interrupt. * @fn EXTI_GenerateSWInterrupt
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @brief Generates a Software interrupt.
* *
* @return none. * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*/ *
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) * @return none.
{ */
EXTI->SWIEVR |= EXTI_Line; void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
} {
EXTI->SWIEVR |= EXTI_Line;
/********************************************************************* }
* @fn EXTI_GetFlagStatus
* /*********************************************************************
* @brief Checks whether the specified EXTI line flag is set or not. * @fn EXTI_GetFlagStatus
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @brief Checks whether the specified EXTI line flag is set or not.
* *
* @return The new state of EXTI_Line (SET or RESET). * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*/ *
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) * @return The new state of EXTI_Line (SET or RESET).
{ */
FlagStatus bitstatus = RESET; FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) {
{ FlagStatus bitstatus = RESET;
bitstatus = SET; if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
} {
else bitstatus = SET;
{ }
bitstatus = RESET; else
} {
return bitstatus; bitstatus = RESET;
} }
return bitstatus;
/********************************************************************* }
* @fn EXTI_ClearFlag
* /*********************************************************************
* @brief Clears the EXTI's line pending flags. * @fn EXTI_ClearFlag
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @brief Clears the EXTI's line pending flags.
* *
* @return None * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*/ *
void EXTI_ClearFlag(uint32_t EXTI_Line) * @return None
{ */
EXTI->INTFR = EXTI_Line; void EXTI_ClearFlag(uint32_t EXTI_Line)
} {
EXTI->INTFR = EXTI_Line;
/********************************************************************* }
* @fn EXTI_GetITStatus
* /*********************************************************************
* @brief Checks whether the specified EXTI line is asserted or not. * @fn EXTI_GetITStatus
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @brief Checks whether the specified EXTI line is asserted or not.
* *
* @return The new state of EXTI_Line (SET or RESET). * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*/ *
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) * @return The new state of EXTI_Line (SET or RESET).
{ */
ITStatus bitstatus = RESET; ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
uint32_t enablestatus = 0; {
ITStatus bitstatus = RESET;
enablestatus = EXTI->INTENR & EXTI_Line; uint32_t enablestatus = 0;
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{ enablestatus = EXTI->INTENR & EXTI_Line;
bitstatus = SET; if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
} {
else bitstatus = SET;
{ }
bitstatus = RESET; else
} {
return bitstatus; bitstatus = RESET;
} }
return bitstatus;
/********************************************************************* }
* @fn EXTI_ClearITPendingBit
* /*********************************************************************
* @brief Clears the EXTI's line pending bits. * @fn EXTI_ClearITPendingBit
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @brief Clears the EXTI's line pending bits.
* *
* @return none * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*/ *
void EXTI_ClearITPendingBit(uint32_t EXTI_Line) * @return none
{ */
EXTI->INTFR = EXTI_Line; void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
} {
EXTI->INTFR = EXTI_Line;
}

1900
Peripheral/src/ch32v00x_flash.c
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File diff suppressed because it is too large Load diff

963
Peripheral/src/ch32v00x_gpio.c
View file

@ -1,456 +1,507 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_gpio.c * File Name : ch32v00x_gpio.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the GPIO firmware functions. * Description : This file provides all the GPIO firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_gpio.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#include <ch32v00x_rcc.h> *******************************************************************************/
#include <ch32v00x_gpio.h>
/* MASK */ #include <ch32v00x_rcc.h>
#define LSB_MASK ((uint16_t)0xFFFF)
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) /* MASK */
#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF) #define LSB_MASK ((uint16_t)0xFFFF)
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) #define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) #define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF)
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
/********************************************************************* #define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
* @fn GPIO_DeInit
* /*********************************************************************
* @brief Deinitializes the GPIOx peripheral registers to their default * @fn GPIO_DeInit
* reset values. *
* * @brief Deinitializes the GPIOx peripheral registers to their default
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral. * reset values.
* *
* @return none * @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*/ *
void GPIO_DeInit(GPIO_TypeDef *GPIOx) * @return none
{ */
if(GPIOx == GPIOA) void GPIO_DeInit(GPIO_TypeDef *GPIOx)
{ {
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); if(GPIOx == GPIOA)
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); {
} RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
else if(GPIOx == GPIOC) RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
{ }
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); else if(GPIOx == GPIOC)
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); {
} RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
else if(GPIOx == GPIOD) RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
{ }
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); else if(GPIOx == GPIOD)
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); {
} RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
} RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
}
/********************************************************************* }
* @fn GPIO_AFIODeInit
* /*********************************************************************
* @brief Deinitializes the Alternate Functions (remap, event control * @fn GPIO_AFIODeInit
* and EXTI configuration) registers to their default reset values. *
* * @brief Deinitializes the Alternate Functions (remap, event control
* @return none * and EXTI configuration) registers to their default reset values.
*/ *
void GPIO_AFIODeInit(void) * @return none
{ */
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); void GPIO_AFIODeInit(void)
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); {
} RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
/********************************************************************* }
* @fn GPIO_Init
* /*********************************************************************
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. * @fn GPIO_Init
* *
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
* contains the configuration information for the specified GPIO peripheral. *
* * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
* @return none * contains the configuration information for the specified GPIO peripheral.
*/ *
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) * @return none
{ */
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
uint32_t tmpreg = 0x00, pinmask = 0x00; {
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); uint32_t tmpreg = 0x00, pinmask = 0x00;
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
{
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
} {
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) }
{
tmpreg = GPIOx->CFGLR; if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
{
for(pinpos = 0x00; pinpos < 0x08; pinpos++) tmpreg = GPIOx->CFGLR;
{
pos = ((uint32_t)0x01) << pinpos; for(pinpos = 0x00; pinpos < 0x08; pinpos++)
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; {
pos = ((uint32_t)0x01) << pinpos;
if(currentpin == pos) currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
{
pos = pinpos << 2; if(currentpin == pos)
pinmask = ((uint32_t)0x0F) << pos; {
tmpreg &= ~pinmask; pos = pinpos << 2;
tmpreg |= (currentmode << pos); pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) tmpreg |= (currentmode << pos);
{
GPIOx->BCR = (((uint32_t)0x01) << pinpos); if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
} {
else GPIOx->BCR = (((uint32_t)0x01) << pinpos);
{ }
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) else
{ {
GPIOx->BSHR = (((uint32_t)0x01) << pinpos); if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
} {
} GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
} }
} }
GPIOx->CFGLR = tmpreg; }
} }
GPIOx->CFGLR = tmpreg;
if(GPIO_InitStruct->GPIO_Pin > 0x00FF) }
{
tmpreg = GPIOx->CFGHR; if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
for(pinpos = 0x00; pinpos < 0x08; pinpos++) tmpreg = GPIOx->CFGHR;
{
pos = (((uint32_t)0x01) << (pinpos + 0x08)); for(pinpos = 0x00; pinpos < 0x08; pinpos++)
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); {
pos = (((uint32_t)0x01) << (pinpos + 0x08));
if(currentpin == pos) currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
{
pos = pinpos << 2; if(currentpin == pos)
pinmask = ((uint32_t)0x0F) << pos; {
tmpreg &= ~pinmask; pos = pinpos << 2;
tmpreg |= (currentmode << pos); pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) tmpreg |= (currentmode << pos);
{
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
} {
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) }
{
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
} {
} GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
} }
GPIOx->CFGHR = tmpreg; }
} }
} GPIOx->CFGHR = tmpreg;
}
/********************************************************************* }
* @fn GPIO_StructInit
* /*********************************************************************
* @brief Fills each GPIO_InitStruct member with its default * @fn GPIO_StructInit
* *
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure * @brief Fills each GPIO_InitStruct member with its default
* which will be initialized. *
* * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
* @return none * which will be initialized.
*/ *
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) * @return none
{ */
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; {
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
} GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
/********************************************************************* }
* @fn GPIO_ReadInputDataBit
* /*********************************************************************
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. * @fn GPIO_ReadInputDataBit
* *
* @param GPIO_Pin - specifies the port bit to read. * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
* This parameter can be GPIO_Pin_x where x can be (0..15). *
* * @param GPIO_Pin - specifies the port bit to read.
* @return The input port pin value. * This parameter can be GPIO_Pin_x where x can be (0..15).
*/ *
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * @return The input port pin value.
{ */
uint8_t bitstatus = 0x00; uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) uint8_t bitstatus = 0x00;
{
bitstatus = (uint8_t)Bit_SET; if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
} {
else bitstatus = (uint8_t)Bit_SET;
{ }
bitstatus = (uint8_t)Bit_RESET; else
} {
bitstatus = (uint8_t)Bit_RESET;
return bitstatus; }
}
return bitstatus;
/********************************************************************* }
* @fn GPIO_ReadInputData
* /*********************************************************************
* @brief Reads the specified GPIO input data port. * @fn GPIO_ReadInputData
* *
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral. * @brief Reads the specified GPIO input data port.
* *
* @return The input port pin value. * @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
*/ *
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) * @return The input port pin value.
{ */
return ((uint16_t)GPIOx->INDR); uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
} {
return ((uint16_t)GPIOx->INDR);
/********************************************************************* }
* @fn GPIO_ReadOutputDataBit
* /*********************************************************************
* @brief Reads the specified output data port bit. * @fn GPIO_ReadOutputDataBit
* *
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral. * @brief Reads the specified output data port bit.
* GPIO_Pin - specifies the port bit to read. *
* This parameter can be GPIO_Pin_x where x can be (0..15). * @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* * GPIO_Pin - specifies the port bit to read.
* @return none * This parameter can be GPIO_Pin_x where x can be (0..15).
*/ *
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * @return none
{ */
uint8_t bitstatus = 0x00; uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) uint8_t bitstatus = 0x00;
{
bitstatus = (uint8_t)Bit_SET; if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
} {
else bitstatus = (uint8_t)Bit_SET;
{ }
bitstatus = (uint8_t)Bit_RESET; else
} {
bitstatus = (uint8_t)Bit_RESET;
return bitstatus; }
}
return bitstatus;
/********************************************************************* }
* @fn GPIO_ReadOutputData
* /*********************************************************************
* @brief Reads the specified GPIO output data port. * @fn GPIO_ReadOutputData
* *
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral. * @brief Reads the specified GPIO output data port.
* *
* @return GPIO output port pin value. * @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*/ *
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) * @return GPIO output port pin value.
{ */
return ((uint16_t)GPIOx->OUTDR); uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
} {
return ((uint16_t)GPIOx->OUTDR);
/********************************************************************* }
* @fn GPIO_SetBits
* /*********************************************************************
* @brief Sets the selected data port bits. * @fn GPIO_SetBits
* *
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral. * @brief Sets the selected data port bits.
* GPIO_Pin - specifies the port bits to be written. *
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* * GPIO_Pin - specifies the port bits to be written.
* @return none * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*/ *
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * @return none
{ */
GPIOx->BSHR = GPIO_Pin; void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
} {
GPIOx->BSHR = GPIO_Pin;
/********************************************************************* }
* @fn GPIO_ResetBits
* /*********************************************************************
* @brief Clears the selected data port bits. * @fn GPIO_ResetBits
* *
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral. * @brief Clears the selected data port bits.
* GPIO_Pin - specifies the port bits to be written. *
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* * GPIO_Pin - specifies the port bits to be written.
* @return none * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*/ *
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * @return none
{ */
GPIOx->BCR = GPIO_Pin; void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
} {
GPIOx->BCR = GPIO_Pin;
/********************************************************************* }
* @fn GPIO_WriteBit
* /*********************************************************************
* @brief Sets or clears the selected data port bit. * @fn GPIO_WriteBit
* *
* @param GPIO_Pin - specifies the port bit to be written. * @brief Sets or clears the selected data port bit.
* This parameter can be one of GPIO_Pin_x where x can be (0..15). *
* BitVal - specifies the value to be written to the selected bit. * @param GPIO_Pin - specifies the port bit to be written.
* Bit_SetL - to clear the port pin. * This parameter can be one of GPIO_Pin_x where x can be (0..15).
* Bit_SetH - to set the port pin. * BitVal - specifies the value to be written to the selected bit.
* * Bit_RESET - to clear the port pin.
* @return none * Bit_SET - to set the port pin.
*/ *
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) * @return none
{ */
if(BitVal != Bit_RESET) void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{ {
GPIOx->BSHR = GPIO_Pin; if(BitVal != Bit_RESET)
} {
else GPIOx->BSHR = GPIO_Pin;
{ }
GPIOx->BCR = GPIO_Pin; else
} {
} GPIOx->BCR = GPIO_Pin;
}
/********************************************************************* }
* @fn GPIO_Write
* /*********************************************************************
* @brief Writes data to the specified GPIO data port. * @fn GPIO_Write
* *
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral. * @brief Writes data to the specified GPIO data port.
* PortVal - specifies the value to be written to the port output data register. *
* * @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* @return none * PortVal - specifies the value to be written to the port output data register.
*/ *
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) * @return none
{ */
GPIOx->OUTDR = PortVal; void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
} {
GPIOx->OUTDR = PortVal;
/********************************************************************* }
* @fn GPIO_PinLockConfig
* /*********************************************************************
* @brief Locks GPIO Pins configuration registers. * @fn GPIO_PinLockConfig
* *
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral. * @brief Locks GPIO Pins configuration registers.
* GPIO_Pin - specifies the port bit to be written. *
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* * GPIO_Pin - specifies the port bit to be written.
* @return none * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*/ *
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) * @return none
{ */
uint32_t tmp = 0x00010000; void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
tmp |= GPIO_Pin; uint32_t tmp = 0x00010000;
GPIOx->LCKR = tmp;
GPIOx->LCKR = GPIO_Pin; tmp |= GPIO_Pin;
GPIOx->LCKR = tmp; GPIOx->LCKR = tmp;
tmp = GPIOx->LCKR; GPIOx->LCKR = GPIO_Pin;
tmp = GPIOx->LCKR; GPIOx->LCKR = tmp;
} tmp = GPIOx->LCKR;
tmp = GPIOx->LCKR;
/********************************************************************* }
* @fn GPIO_PinRemapConfig
* /*********************************************************************
* @brief Changes the mapping of the specified pin. * @fn GPIO_PinRemapConfig
* *
* @param GPIO_Remap - selects the pin to remap. * @brief Changes the mapping of the specified pin.
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping *
* GPIO_PartialRemap_I2C1 - I2C1 Partial Alternate Function mapping * @param GPIO_Remap - selects the pin to remap.
* GPIO_PartialRemap_I2C1 - I2C1 Full Alternate Function mapping * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
* GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping * GPIO_PartialRemap_I2C1 - I2C1 Partial Alternate Function mapping
* GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping * GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping
* GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping * GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping
* GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping * GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping
* GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping * GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping * GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping * GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
* GPIO_Remap_PA12 - PA12 Alternate Function mapping * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping * GPIO_Remap_PA1_2 - PA1_2 Alternate Function mapping
* GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
* GPIO_Remap_SWJ_Disable - SDI Disabled * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
* NewState - ENABLE or DISABLE. * GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping
* * GPIO_Remap_SDI_Disable - SDI Disabled
* @return none * NewState - ENABLE or DISABLE.
*/ *
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) * @return none
{ */
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
{
tmpreg = AFIO->PCFR1; uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; tmpreg = AFIO->PCFR1;
tmp = GPIO_Remap & LSB_MASK;
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
if((GPIO_Remap & 0x10000000) == 0x10000000) tmp = GPIO_Remap & LSB_MASK;
{
tmpreg &= ~((1<<1) | (1<<22)); if((GPIO_Remap & 0x10000000) == 0x10000000)
tmpreg |= ~DBGAFR_SDI_MASK; {
if(NewState != DISABLE) tmpreg &= ~((1<<1) | (1<<22));
{ tmpreg |= ~DBGAFR_SDI_MASK;
tmpreg |= (GPIO_Remap & 0xEFFFFFFF); if(NewState != DISABLE)
} {
tmpreg |= (GPIO_Remap & 0xEFFFFFFF);
} }
else if((GPIO_Remap & 0x80000000) == 0x80000000)
{ }
tmpreg &= ~((1<<2) | (1<<21)); else if((GPIO_Remap & 0x80000000) == 0x80000000)
tmpreg |= ~DBGAFR_SDI_MASK; {
if(NewState != DISABLE) tmpreg &= ~((1<<2) | (1<<21));
{ tmpreg |= ~DBGAFR_SDI_MASK;
tmpreg |= (GPIO_Remap & 0x7FFFFFFF); if(NewState != DISABLE)
} {
tmpreg |= (GPIO_Remap & 0x7FFFFFFF);
} }
else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))/* SDI */
{ }
tmpreg &= DBGAFR_SDI_MASK; else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))/* SDI */
AFIO->PCFR1 &= DBGAFR_SDI_MASK; {
tmpreg &= DBGAFR_SDI_MASK;
if(NewState != DISABLE) AFIO->PCFR1 &= DBGAFR_SDI_MASK;
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); if(NewState != DISABLE)
} {
} tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)/* [15:0] 2bit */ }
{ }
tmp1 = ((uint32_t)0x03) << tmpmask; else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)/* [15:0] 2bit */
tmpreg &= ~tmp1; {
tmpreg |= ~DBGAFR_SDI_MASK; tmp1 = ((uint32_t)0x03) << tmpmask;
tmpreg &= ~tmp1;
if(NewState != DISABLE) tmpreg |= ~DBGAFR_SDI_MASK;
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); if(NewState != DISABLE)
} {
} tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
else/* [31:0] 1bit */ }
{ }
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); else/* [31:0] 1bit */
tmpreg |= ~DBGAFR_SDI_MASK; {
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
if(NewState != DISABLE) tmpreg |= ~DBGAFR_SDI_MASK;
{
tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10)); if(NewState != DISABLE)
} {
} tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
}
}
AFIO->PCFR1 = tmpreg;
}
AFIO->PCFR1 = tmpreg;
/********************************************************************* }
* @fn GPIO_EXTILineConfig
* /*********************************************************************
* @brief Selects the GPIO pin used as EXTI Line. * @fn GPIO_EXTILineConfig
* *
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. * @brief Selects the GPIO pin used as EXTI Line.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). *
* GPIO_PinSource - specifies the EXTI line to be configured. * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
* This parameter can be GPIO_PinSourcex where x can be (0..7). * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
* * GPIO_PinSource - specifies the EXTI line to be configured.
* @return none * This parameter can be GPIO_PinSourcex where x can be (0..7).
*/ *
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) * @return none
{ */
uint32_t tmp = 0x00; void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
tmp = ((uint32_t)(3<<(GPIO_PinSource<<1))); uint32_t tmp = 0x00;
AFIO->EXTICR &= ~tmp;
AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1))); tmp = ((uint32_t)(3<<(GPIO_PinSource<<1)));
} AFIO->EXTICR &= ~tmp;
AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1)));
}
/*********************************************************************
* @fn GPIO_IPD_Unused
*
* @brief Configure unused GPIO as input pull-up.
*
* @param none
*
* @return none
*/
void GPIO_IPD_Unused(void)
{
GPIO_InitTypeDef GPIO_InitStructure = {0};
uint32_t chip = 0;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC, ENABLE);
chip = *( uint32_t * )0x1FFFF7C4 & (~0x000000F0);
switch(chip)
{
case 0x00320500: //CH32V003A4M6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\
|GPIO_Pin_3;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
break;
}
case 0x00330500: //CH32V003J4M6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_7;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\
|GPIO_Pin_5|GPIO_Pin_6\
|GPIO_Pin_7;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
break;
}
default:
{
break;
}
}
}

1914
Peripheral/src/ch32v00x_i2c.c
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249
Peripheral/src/ch32v00x_iwdg.c
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@ -1,123 +1,126 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_iwdg.c * File Name : ch32v00x_iwdg.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2023/12/25
* Description : This file provides all the IWDG firmware functions. * Description : This file provides all the IWDG firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*******************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_iwdg.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
/* CTLR register bit mask */ #include <ch32v00x_iwdg.h>
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC) /* CTLR register bit mask */
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
/********************************************************************* #define CTLR_KEY_Enable ((uint16_t)0xCCCC)
* @fn IWDG_WriteAccessCmd
* /*********************************************************************
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. * @fn IWDG_WriteAccessCmd
* *
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
* IWDG_RLDR registers. *
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
* IWDG_RLDR registers. * IWDG_RLDR registers.
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
* and IWDG_RLDR registers. * IWDG_RLDR registers.
* * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
* @return none * and IWDG_RLDR registers.
*/ *
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) * @return none
{ */
IWDG->CTLR = IWDG_WriteAccess; void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
} {
IWDG->CTLR = IWDG_WriteAccess;
/********************************************************************* }
* @fn IWDG_SetPrescaler
* /*********************************************************************
* @brief Sets IWDG Prescaler value. * @fn IWDG_SetPrescaler
* *
* @param IWDG_Prescaler - specifies the IWDG Prescaler value. * @brief Sets IWDG Prescaler value.
* IWDG_Prescaler_4 - IWDG prescaler set to 4. *
* IWDG_Prescaler_8 - IWDG prescaler set to 8. * @param IWDG_Prescaler - specifies the IWDG Prescaler value.
* IWDG_Prescaler_16 - IWDG prescaler set to 16. * IWDG_Prescaler_4 - IWDG prescaler set to 4.
* IWDG_Prescaler_32 - IWDG prescaler set to 32. * IWDG_Prescaler_8 - IWDG prescaler set to 8.
* IWDG_Prescaler_64 - IWDG prescaler set to 64. * IWDG_Prescaler_16 - IWDG prescaler set to 16.
* IWDG_Prescaler_128 - IWDG prescaler set to 128. * IWDG_Prescaler_32 - IWDG prescaler set to 32.
* IWDG_Prescaler_256 - IWDG prescaler set to 256. * IWDG_Prescaler_64 - IWDG prescaler set to 64.
* * IWDG_Prescaler_128 - IWDG prescaler set to 128.
* @return none * IWDG_Prescaler_256 - IWDG prescaler set to 256.
*/ *
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) * @return none
{ */
IWDG->PSCR = IWDG_Prescaler; void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
} {
IWDG->PSCR = IWDG_Prescaler;
/********************************************************************* }
* @fn IWDG_SetReload
* /*********************************************************************
* @brief Sets IWDG Reload value. * @fn IWDG_SetReload
* *
* @param Reload - specifies the IWDG Reload value. * @brief Sets IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF. *
* * @param Reload - specifies the IWDG Reload value.
* @return none * This parameter must be a number between 0 and 0x0FFF.
*/ *
void IWDG_SetReload(uint16_t Reload) * @return none
{ */
IWDG->RLDR = Reload; void IWDG_SetReload(uint16_t Reload)
} {
IWDG->RLDR = Reload;
/********************************************************************* }
* @fn IWDG_ReloadCounter
* /*********************************************************************
* @brief Reloads IWDG counter with value defined in the reload register. * @fn IWDG_ReloadCounter
* *
* @return none * @brief Reloads IWDG counter with value defined in the reload register.
*/ *
void IWDG_ReloadCounter(void) * @return none
{ */
IWDG->CTLR = CTLR_KEY_Reload; void IWDG_ReloadCounter(void)
} {
IWDG->CTLR = CTLR_KEY_Reload;
/********************************************************************* }
* @fn IWDG_Enable
* /*********************************************************************
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). * @fn IWDG_Enable
* *
* @return none * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
*/ *
void IWDG_Enable(void) * @return none
{ */
IWDG->CTLR = CTLR_KEY_Enable; void IWDG_Enable(void)
} {
IWDG->CTLR = CTLR_KEY_Enable;
/********************************************************************* while ((RCC->RSTSCKR)|(0x2)!= SET);
* @fn IWDG_GetFlagStatus }
*
* @brief Checks whether the specified IWDG flag is set or not. /*********************************************************************
* * @fn IWDG_GetFlagStatus
* @param IWDG_FLAG - specifies the flag to check. *
* IWDG_FLAG_PVU - Prescaler Value Update on going. * @brief Checks whether the specified IWDG flag is set or not.
* IWDG_FLAG_RVU - Reload Value Update on going. *
* * @param IWDG_FLAG - specifies the flag to check.
* @return none * IWDG_FLAG_PVU - Prescaler Value Update on going.
*/ * IWDG_FLAG_RVU - Reload Value Update on going.
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) *
{ * @return none
FlagStatus bitstatus = RESET; */
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) {
{ FlagStatus bitstatus = RESET;
bitstatus = SET;
} if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
else {
{ bitstatus = SET;
bitstatus = RESET; }
} else
{
return bitstatus; bitstatus = RESET;
} }
return bitstatus;
}

188
Peripheral/src/ch32v00x_misc.c
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@ -1,107 +1,81 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_misc.c * File Name : ch32v00x_misc.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2023/12/25
* Description : This file provides all the miscellaneous firmware functions . * Description : This file provides all the miscellaneous firmware functions .
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
*********************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_misc.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
__IO uint32_t NVIC_Priority_Group = 0; #include <ch32v00x_misc.h>
/********************************************************************* __IO uint32_t NVIC_Priority_Group = 0;
* @fn NVIC_PriorityGroupConfig
* /*********************************************************************
* @brief Configures the priority grouping - pre-emption priority and subpriority. * @fn NVIC_PriorityGroupConfig
* *
* @param NVIC_PriorityGroup - specifies the priority grouping bits length. * @brief Configures the priority grouping - pre-emption priority and subpriority.
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority *
* 4 bits for subpriority * @param NVIC_PriorityGroup - specifies the priority grouping bits length.
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
* 3 bits for subpriority * 2 bits for subpriority
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 2 bits for subpriority * 1 bits for subpriority
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority *
* 1 bits for subpriority * @return none
* NVIC_PriorityGroup_4 - 4 bits for pre-emption priority */
* 0 bits for subpriority void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
* {
* @return none NVIC_Priority_Group = NVIC_PriorityGroup;
*/ }
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{ /*********************************************************************
NVIC_Priority_Group = NVIC_PriorityGroup; * @fn NVIC_Init
} *
* @brief Initializes the NVIC peripheral according to the specified parameters in
/********************************************************************* * the NVIC_InitStruct.
* @fn NVIC_Init *
* * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
* @brief Initializes the NVIC peripheral according to the specified parameters in * configuration information for the specified NVIC peripheral.
* the NVIC_InitStruct. * interrupt nesting enable(CSR-0x804 bit1 = 1)
* * NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the * NVIC_IRQChannelSubPriority - range from 0 to 1.
* configuration information for the specified NVIC peripheral. *
* * interrupt nesting disable(CSR-0x804 bit1 = 0)
* @return none * NVIC_IRQChannelPreemptionPriority - range is 0.
*/ * NVIC_IRQChannelSubPriority - range from 0 to 3.
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) *
{ * @return none
uint8_t tmppre = 0; */
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
if(NVIC_Priority_Group == NVIC_PriorityGroup_0) {
{ #if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
} {
else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6);
{ }
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) #else
{ if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); {
} if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
else {
{ NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); }
} else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0)
} {
else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6));
{ }
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) }
{ #endif
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
} {
else NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
{ }
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); else
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); {
} NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
} }
else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) }
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
}
else
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
}
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
else
{
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
}

162
Peripheral/src/ch32v00x_opa.c
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@ -1,80 +1,82 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_opa.c * File Name : ch32v00x_opa.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the OPA firmware functions. * Description : This file provides all the OPA firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
***************************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_opa.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_opa.h>
/*********************************************************************
* @fn OPA_DeInit
* /*********************************************************************
* @brief Deinitializes the OPA peripheral registers to their default * @fn OPA_DeInit
* reset values. *
* * @brief Deinitializes the OPA peripheral registers to their default
* @return none * reset values.
*/ *
void OPA_DeInit(void) * @return none
{ */
EXTEN->EXTEN_CTR &= ~(uint32_t)(7 << 16); void OPA_DeInit(void)
} {
EXTEN->EXTEN_CTR &= ~(uint32_t)(7 << 16);
/********************************************************************* }
* @fn OPA_Init
* /*********************************************************************
* @brief Initializes the OPA peripheral according to the specified * @fn OPA_Init
* parameters in the OPA_InitStruct. *
* * @brief Initializes the OPA peripheral according to the specified
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure * parameters in the OPA_InitStruct.
* *
* @return none * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
*/ *
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) * @return none
{ */
uint32_t tmp = 0; void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
tmp = EXTEN->EXTEN_CTR; {
tmp &= ~(uint32_t)(2<<17); uint32_t tmp = 0;
tmp |= (OPA_InitStruct->PSEL << 18) | (OPA_InitStruct->NSEL << 17); tmp = EXTEN->EXTEN_CTR;
EXTEN->EXTEN_CTR = tmp; tmp &= ~(uint32_t)(3<<17);
} tmp |= (OPA_InitStruct->PSEL << 18) | (OPA_InitStruct->NSEL << 17);
EXTEN->EXTEN_CTR = tmp;
/********************************************************************* }
* @fn OPA_StructInit
* /*********************************************************************
* @brief Fills each OPA_StructInit member with its reset value. * @fn OPA_StructInit
* *
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure * @brief Fills each OPA_StructInit member with its reset value.
* *
* @return none * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
*/ *
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) * @return none
{ */
OPA_InitStruct->PSEL = CHP0; void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
OPA_InitStruct->NSEL = CHN0; {
} OPA_InitStruct->PSEL = CHP0;
OPA_InitStruct->NSEL = CHN0;
/********************************************************************* }
* @fn OPA_Cmd
* /*********************************************************************
* @brief Enables or disables the specified OPA peripheral. * @fn OPA_Cmd
* *
* @param OPA_NUM - Select OPA * @brief Enables or disables the specified OPA peripheral.
* NewState - ENABLE or DISABLE. *
* * @param OPA_NUM - Select OPA
* @return none * NewState - ENABLE or DISABLE.
*/ *
void OPA_Cmd(FunctionalState NewState) * @return none
{ */
if(NewState == ENABLE) void OPA_Cmd(FunctionalState NewState)
{ {
EXTEN->EXTEN_CTR |= (uint32_t)(1 << 16); if(NewState == ENABLE)
} {
else EXTEN->EXTEN_CTR |= (uint32_t)(1 << 16);
{ }
EXTEN->EXTEN_CTR &= ~(uint32_t)(1 << 16); else
} {
} EXTEN->EXTEN_CTR &= ~(uint32_t)(1 << 16);
}
}

424
Peripheral/src/ch32v00x_pwr.c
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@ -1,211 +1,213 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_pwr.c * File Name : ch32v00x_pwr.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the PWR firmware functions. * Description : This file provides all the PWR firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
********************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_pwr.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#include <ch32v00x_rcc.h> *******************************************************************************/
#include <ch32v00x_pwr.h>
/* PWR registers bit mask */ #include <ch32v00x_rcc.h>
/* CTLR register bit mask */
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) /* PWR registers bit mask */
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) /* CTLR register bit mask */
#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) #define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0)
/********************************************************************* #define AWUWR_MASK ((uint32_t)0xFFFFFFC0)
* @fn PWR_DeInit
* /*********************************************************************
* @brief Deinitializes the PWR peripheral registers to their default * @fn PWR_DeInit
* reset values. *
* * @brief Deinitializes the PWR peripheral registers to their default
* @return none * reset values.
*/ *
void PWR_DeInit(void) * @return none
{ */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); void PWR_DeInit(void)
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); {
} RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
/********************************************************************* }
* @fn PWR_PVDCmd
* /*********************************************************************
* @brief Enables or disables the Power Voltage Detector(PVD). * @fn PWR_PVDCmd
* *
* @param NewState - new state of the PVD(ENABLE or DISABLE). * @brief Enables or disables the Power Voltage Detector(PVD).
* *
* @return none * @param NewState - new state of the PVD(ENABLE or DISABLE).
*/ *
void PWR_PVDCmd(FunctionalState NewState) * @return none
{ */
if(NewState) void PWR_PVDCmd(FunctionalState NewState)
{ {
PWR->CTLR |= (1 << 4); if(NewState)
} {
else PWR->CTLR |= (1 << 4);
{ }
PWR->CTLR &= ~(1 << 4); else
} {
} PWR->CTLR &= ~(1 << 4);
}
/********************************************************************* }
* @fn PWR_PVDLevelConfig
* /*********************************************************************
* @brief Configures the voltage threshold detected by the Power Voltage * @fn PWR_PVDLevelConfig
* Detector(PVD). *
* * @brief Configures the voltage threshold detected by the Power Voltage
* @param PWR_PVDLevel - specifies the PVD detection level * Detector(PVD).
* PWR_PVDLevel_2V2 - PVD detection level set to 2.2V *
* PWR_PVDLevel_2V3 - PVD detection level set to 2.3V * @param PWR_PVDLevel - specifies the PVD detection level
* PWR_PVDLevel_2V4 - PVD detection level set to 2.4V * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
* PWR_PVDLevel_2V5 - PVD detection level set to 2.5V * PWR_PVDLevel_3V1 - PVD detection level set to 3.1V
* PWR_PVDLevel_2V6 - PVD detection level set to 2.6V * PWR_PVDLevel_3V3 - PVD detection level set to 3.3V
* PWR_PVDLevel_2V7 - PVD detection level set to 2.7V * PWR_PVDLevel_3V5 - PVD detection level set to 3.5V
* PWR_PVDLevel_2V8 - PVD detection level set to 2.8V * PWR_PVDLevel_3V7 - PVD detection level set to 3.7V
* PWR_PVDLevel_2V9 - PVD detection level set to 2.9V * PWR_PVDLevel_3V9 - PVD detection level set to 3.9V
* * PWR_PVDLevel_4V1 - PVD detection level set to 4.1V
* @return none * PWR_PVDLevel_4V4 - PVD detection level set to 4.4V
*/ *
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) * @return none
{ */
uint32_t tmpreg = 0; void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
tmpreg = PWR->CTLR; {
tmpreg &= CTLR_PLS_MASK; uint32_t tmpreg = 0;
tmpreg |= PWR_PVDLevel; tmpreg = PWR->CTLR;
PWR->CTLR = tmpreg; tmpreg &= CTLR_PLS_MASK;
} tmpreg |= PWR_PVDLevel;
PWR->CTLR = tmpreg;
/********************************************************************* }
* @fn PWR_AutoWakeUpCmd
* /*********************************************************************
* @brief Enables or disables the Auto WakeUp functionality. * @fn PWR_AutoWakeUpCmd
* *
* @param NewState - new state of the Auto WakeUp functionality * @brief Enables or disables the Auto WakeUp functionality.
* (ENABLE or DISABLE). *
* * @param NewState - new state of the Auto WakeUp functionality
* @return none * (ENABLE or DISABLE).
*/ *
void PWR_AutoWakeUpCmd(FunctionalState NewState) * @return none
{ */
if(NewState) void PWR_AutoWakeUpCmd(FunctionalState NewState)
{ {
PWR->AWUCSR |= (1 << 1); if(NewState)
} {
else PWR->AWUCSR |= (1 << 1);
{ }
PWR->AWUCSR &= ~(1 << 1); else
} {
} PWR->AWUCSR &= ~(1 << 1);
}
/********************************************************************* }
* @fn PWR_AWU_SetPrescaler
* /*********************************************************************
* @brief Sets the Auto Wake up Prescaler * @fn PWR_AWU_SetPrescaler
* *
* @param AWU_Prescaler - specifies the Auto Wake up Prescaler * @brief Sets the Auto Wake up Prescaler
* PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1 *
* PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2 * @param AWU_Prescaler - specifies the Auto Wake up Prescaler
* PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4 * PWR_AWU_Prescaler_1 - AWU counter clock = LSI/1
* PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8 * PWR_AWU_Prescaler_2 - AWU counter clock = LSI/2
* PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16 * PWR_AWU_Prescaler_4 - AWU counter clock = LSI/4
* PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32 * PWR_AWU_Prescaler_8 - AWU counter clock = LSI/8
* PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64 * PWR_AWU_Prescaler_16 - AWU counter clock = LSI/16
* PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128 * PWR_AWU_Prescaler_32 - AWU counter clock = LSI/32
* PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256 * PWR_AWU_Prescaler_64 - AWU counter clock = LSI/64
* PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512 * PWR_AWU_Prescaler_128 - AWU counter clock = LSI/128
* PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024 * PWR_AWU_Prescaler_256 - AWU counter clock = LSI/256
* PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048 * PWR_AWU_Prescaler_512 - AWU counter clock = LSI/512
* PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096 * PWR_AWU_Prescaler_1024 - AWU counter clock = LSI/1024
* PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240 * PWR_AWU_Prescaler_2048 - AWU counter clock = LSI/2048
* PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440 * PWR_AWU_Prescaler_4096 - AWU counter clock = LSI/4096
* * PWR_AWU_Prescaler_10240 - AWU counter clock = LSI/10240
* @return none * PWR_AWU_Prescaler_61440 - AWU counter clock = LSI/61440
*/ *
void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler) * @return none
{ */
uint32_t tmpreg = 0; void PWR_AWU_SetPrescaler(uint32_t AWU_Prescaler)
tmpreg = PWR->AWUPSC & AWUPSC_MASK; {
tmpreg |= AWU_Prescaler; uint32_t tmpreg = 0;
PWR->AWUPSC = tmpreg; tmpreg = PWR->AWUPSC & AWUPSC_MASK;
} tmpreg |= AWU_Prescaler;
PWR->AWUPSC = tmpreg;
/********************************************************************* }
* @fn PWR_AWU_SetWindowValue
* /*********************************************************************
* @brief Sets the WWDG window value * @fn PWR_AWU_SetWindowValue
* *
* @param WindowValue - specifies the window value to be compared to the * @brief Sets the WWDG window value
* downcounter,which must be lower than 0x3F *
* * @param WindowValue - specifies the window value to be compared to the
* @return none * downcounter,which must be lower than 0x3F
*/ *
void PWR_AWU_SetWindowValue(uint8_t WindowValue) * @return none
{ */
__IO uint32_t tmpreg = 0; void PWR_AWU_SetWindowValue(uint8_t WindowValue)
{
tmpreg = PWR->AWUWR & AWUWR_MASK; __IO uint32_t tmpreg = 0;
tmpreg |= WindowValue; tmpreg = PWR->AWUWR & AWUWR_MASK;
PWR->AWUWR = tmpreg; tmpreg |= WindowValue;
}
PWR->AWUWR = tmpreg;
/********************************************************************* }
* @fn PWR_EnterSTANDBYMode
* /*********************************************************************
* @brief Enters STANDBY mode. * @fn PWR_EnterSTANDBYMode
* *
* @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction. * @brief Enters STANDBY mode.
* PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction *
* PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction * @param PWR_STANDBYEntry - specifies if STANDBY mode in entered with WFI or WFE instruction.
* * PWR_STANDBYEntry_WFI - enter STANDBY mode with WFI instruction
* @return none * PWR_STANDBYEntry_WFE - enter STANDBY mode with WFE instruction
*/ *
void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry) * @return none
{ */
PWR->CTLR &= CTLR_DS_MASK; void PWR_EnterSTANDBYMode(uint8_t PWR_STANDBYEntry)
PWR->CTLR |= PWR_CTLR_PDDS; {
PWR->CTLR &= CTLR_DS_MASK;
NVIC->SCTLR |= (1 << 2); PWR->CTLR |= PWR_CTLR_PDDS;
if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI) NVIC->SCTLR |= (1 << 2);
{
__WFI(); if(PWR_STANDBYEntry == PWR_STANDBYEntry_WFI)
} {
else __WFI();
{ }
__WFE(); else
} {
__WFE();
NVIC->SCTLR &= ~(1 << 2); }
}
NVIC->SCTLR &= ~(1 << 2);
/********************************************************************* }
* @fn PWR_GetFlagStatus
* /*********************************************************************
* @brief Checks whether the specified PWR flag is set or not. * @fn PWR_GetFlagStatus
* *
* @param PWR_FLAG - specifies the flag to check. * @brief Checks whether the specified PWR flag is set or not.
* PWR_FLAG_PVDO - PVD Output *
* * @param PWR_FLAG - specifies the flag to check.
* @return The new state of PWR_FLAG (SET or RESET). * PWR_FLAG_PVDO - PVD Output
*/ *
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) * @return The new state of PWR_FLAG (SET or RESET).
{ */
FlagStatus bitstatus = RESET; FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) FlagStatus bitstatus = RESET;
{
bitstatus = SET; if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
} {
else bitstatus = SET;
{ }
bitstatus = RESET; else
} {
return bitstatus; bitstatus = RESET;
} }
return bitstatus;
}

1505
Peripheral/src/ch32v00x_rcc.c
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1012
Peripheral/src/ch32v00x_spi.c
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4710
Peripheral/src/ch32v00x_tim.c
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1588
Peripheral/src/ch32v00x_usart.c
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280
Peripheral/src/ch32v00x_wwdg.c
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@ -1,139 +1,141 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32v00x_wwdg.c * File Name : ch32v00x_wwdg.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2022/08/08 * Date : 2022/08/08
* Description : This file provides all the WWDG firmware functions. * Description : This file provides all the WWDG firmware functions.
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. *********************************************************************************
* SPDX-License-Identifier: Apache-2.0 * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
**********************************************************************************/ * Attention: This software (modified or not) and binary are used for
#include <ch32v00x_rcc.h> * microcontroller manufactured by Nanjing Qinheng Microelectronics.
#include <ch32v00x_wwdg.h> *******************************************************************************/
#include <ch32v00x_rcc.h>
/* CTLR register bit mask */ #include <ch32v00x_wwdg.h>
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
/* CTLR register bit mask */
/* CFGR register bit mask */ #define CTLR_WDGA_Set ((uint32_t)0x00000080)
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) /* CFGR register bit mask */
#define BIT_Mask ((uint8_t)0x7F) #define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
/********************************************************************* #define BIT_Mask ((uint8_t)0x7F)
* @fn WWDG_DeInit
* /*********************************************************************
* @brief Deinitializes the WWDG peripheral registers to their default reset values * @fn WWDG_DeInit
* *
* @return none * @brief Deinitializes the WWDG peripheral registers to their default reset values
*/ *
void WWDG_DeInit(void) * @return none
{ */
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); void WWDG_DeInit(void)
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); {
} RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
/********************************************************************* }
* @fn WWDG_SetPrescaler
* /*********************************************************************
* @brief Sets the WWDG Prescaler * @fn WWDG_SetPrescaler
* *
* @param WWDG_Prescaler - specifies the WWDG Prescaler * @brief Sets the WWDG Prescaler
* WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 *
* WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 * @param WWDG_Prescaler - specifies the WWDG Prescaler
* WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
* WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
* * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
* @return none * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
*/ *
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) * @return none
{ */
uint32_t tmpreg = 0; void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; {
tmpreg |= WWDG_Prescaler; uint32_t tmpreg = 0;
WWDG->CFGR = tmpreg; tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
} tmpreg |= WWDG_Prescaler;
WWDG->CFGR = tmpreg;
/********************************************************************* }
* @fn WWDG_SetWindowValue
* /*********************************************************************
* @brief Sets the WWDG window value * @fn WWDG_SetWindowValue
* *
* @param WindowValue - specifies the window value to be compared to the * @brief Sets the WWDG window value
* downcounter,which must be lower than 0x80 *
* * @param WindowValue - specifies the window value to be compared to the
* @return none * downcounter,which must be lower than 0x80
*/ *
void WWDG_SetWindowValue(uint8_t WindowValue) * @return none
{ */
__IO uint32_t tmpreg = 0; void WWDG_SetWindowValue(uint8_t WindowValue)
{
tmpreg = WWDG->CFGR & CFGR_W_Mask; __IO uint32_t tmpreg = 0;
tmpreg |= WindowValue & (uint32_t)BIT_Mask; tmpreg = WWDG->CFGR & CFGR_W_Mask;
WWDG->CFGR = tmpreg; tmpreg |= WindowValue & (uint32_t)BIT_Mask;
}
WWDG->CFGR = tmpreg;
/********************************************************************* }
* @fn WWDG_EnableIT
* /*********************************************************************
* @brief Enables the WWDG Early Wakeup interrupt(EWI) * @fn WWDG_EnableIT
* *
* @return none * @brief Enables the WWDG Early Wakeup interrupt(EWI)
*/ *
void WWDG_EnableIT(void) * @return none
{ */
WWDG->CFGR |= (1 << 9); void WWDG_EnableIT(void)
} {
WWDG->CFGR |= (1 << 9);
/********************************************************************* }
* @fn WWDG_SetCounter
* /*********************************************************************
* @brief Sets the WWDG counter value * @fn WWDG_SetCounter
* *
* @param Counter - specifies the watchdog counter value,which must be a * @brief Sets the WWDG counter value
* number between 0x40 and 0x7F *
* * @param Counter - specifies the watchdog counter value,which must be a
* @return none * number between 0x40 and 0x7F
*/ *
void WWDG_SetCounter(uint8_t Counter) * @return none
{ */
WWDG->CTLR = Counter & BIT_Mask; void WWDG_SetCounter(uint8_t Counter)
} {
WWDG->CTLR = Counter & BIT_Mask;
/********************************************************************* }
* @fn WWDG_Enable
* /*********************************************************************
* @brief Enables WWDG and load the counter value * @fn WWDG_Enable
* *
* @param Counter - specifies the watchdog counter value,which must be a * @brief Enables WWDG and load the counter value
* number between 0x40 and 0x7F *
* @return none * @param Counter - specifies the watchdog counter value,which must be a
*/ * number between 0x40 and 0x7F
void WWDG_Enable(uint8_t Counter) * @return none
{ */
WWDG->CTLR = CTLR_WDGA_Set | Counter; void WWDG_Enable(uint8_t Counter)
} {
WWDG->CTLR = CTLR_WDGA_Set | Counter;
/********************************************************************* }
* @fn WWDG_GetFlagStatus
* /*********************************************************************
* @brief Checks whether the Early Wakeup interrupt flag is set or not * @fn WWDG_GetFlagStatus
* *
* @return The new state of the Early Wakeup interrupt flag (SET or RESET) * @brief Checks whether the Early Wakeup interrupt flag is set or not
*/ *
FlagStatus WWDG_GetFlagStatus(void) * @return The new state of the Early Wakeup interrupt flag (SET or RESET)
{ */
return (FlagStatus)(WWDG->STATR); FlagStatus WWDG_GetFlagStatus(void)
} {
return (FlagStatus)(WWDG->STATR);
/********************************************************************* }
* @fn WWDG_ClearFlag
* /*********************************************************************
* @brief Clears Early Wakeup interrupt flag * @fn WWDG_ClearFlag
* *
* @return none * @brief Clears Early Wakeup interrupt flag
*/ *
void WWDG_ClearFlag(void) * @return none
{ */
WWDG->STATR = (uint32_t)RESET; void WWDG_ClearFlag(void)
} {
WWDG->STATR = (uint32_t)RESET;
}

76
Startup/startup_ch32v00x.S
View file

@ -1,11 +1,13 @@
;/********************************** (C) COPYRIGHT ******************************* ;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v00x.s ;* File Name : startup_ch32v00x.s
;* Author : WCH ;* Author : WCH
;* Version : V1.0.0 ;* Version : V1.0.1
;* Date : 2022/08/08 ;* Date : 2023/12/11
;* Description : vector table for eclipse toolchain. ;* Description : vector table for eclipse toolchain.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. ;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* SPDX-License-Identifier: Apache-2.0 ;* Attention: This software (modified or not) and binary are used for
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
;*******************************************************************************/ ;*******************************************************************************/
.section .init, "ax", @progbits .section .init, "ax", @progbits
@ -84,34 +86,35 @@ _start:
.weak TIM1_CC_IRQHandler .weak TIM1_CC_IRQHandler
.weak TIM2_IRQHandler .weak TIM2_IRQHandler
NMI_Handler: 1: j 1b NMI_Handler:
HardFault_Handler: 1: j 1b HardFault_Handler:
SysTick_Handler: 1: j 1b SysTick_Handler:
SW_Handler: 1: j 1b SW_Handler:
WWDG_IRQHandler: 1: j 1b WWDG_IRQHandler:
PVD_IRQHandler: 1: j 1b PVD_IRQHandler:
FLASH_IRQHandler: 1: j 1b FLASH_IRQHandler:
RCC_IRQHandler: 1: j 1b RCC_IRQHandler:
EXTI7_0_IRQHandler: 1: j 1b EXTI7_0_IRQHandler:
AWU_IRQHandler: 1: j 1b AWU_IRQHandler:
DMA1_Channel1_IRQHandler: 1: j 1b DMA1_Channel1_IRQHandler:
DMA1_Channel2_IRQHandler: 1: j 1b DMA1_Channel2_IRQHandler:
DMA1_Channel3_IRQHandler: 1: j 1b DMA1_Channel3_IRQHandler:
DMA1_Channel4_IRQHandler: 1: j 1b DMA1_Channel4_IRQHandler:
DMA1_Channel5_IRQHandler: 1: j 1b DMA1_Channel5_IRQHandler:
DMA1_Channel6_IRQHandler: 1: j 1b DMA1_Channel6_IRQHandler:
DMA1_Channel7_IRQHandler: 1: j 1b DMA1_Channel7_IRQHandler:
ADC1_IRQHandler: 1: j 1b ADC1_IRQHandler:
I2C1_EV_IRQHandler: 1: j 1b I2C1_EV_IRQHandler:
I2C1_ER_IRQHandler: 1: j 1b I2C1_ER_IRQHandler:
USART1_IRQHandler: 1: j 1b USART1_IRQHandler:
SPI1_IRQHandler: 1: j 1b SPI1_IRQHandler:
TIM1_BRK_IRQHandler: 1: j 1b TIM1_BRK_IRQHandler:
TIM1_UP_IRQHandler: 1: j 1b TIM1_UP_IRQHandler:
TIM1_TRG_COM_IRQHandler: 1: j 1b TIM1_TRG_COM_IRQHandler:
TIM1_CC_IRQHandler: 1: j 1b TIM1_CC_IRQHandler:
TIM2_IRQHandler: 1: j 1b TIM2_IRQHandler:
1:
j 1b
.section .text.handle_reset, "ax", @progbits .section .text.handle_reset, "ax", @progbits
.weak handle_reset .weak handle_reset
@ -124,7 +127,7 @@ handle_reset:
1: 1:
la sp, _eusrstack la sp, _eusrstack
2: 2:
/* Load data section from flash to RAM */ /* Load data section from flash to RAM */
la a0, _data_lma la a0, _data_lma
la a1, _data_vma la a1, _data_vma
la a2, _edata la a2, _edata
@ -136,7 +139,7 @@ handle_reset:
addi a1, a1, 4 addi a1, a1, 4
bltu a1, a2, 1b bltu a1, a2, 1b
2: 2:
/* clear bss section */ /* Clear bss section */
la a0, _sbss la a0, _sbss
la a1, _ebss la a1, _ebss
bgeu a0, a1, 2f bgeu a0, a1, 2f
@ -145,12 +148,13 @@ handle_reset:
addi a0, a0, 4 addi a0, a0, 4
bltu a0, a1, 1b bltu a0, a1, 1b
2: 2:
li t0, 0x80 /* Enable global interrupt and configure privileged mode */
li t0, 0x1880
csrw mstatus, t0 csrw mstatus, t0
/* Enable interrupt nesting and hardware stack */
li t0, 0x3 li t0, 0x3
csrw 0x804, t0 csrw 0x804, t0
/* Configure the interrupt vector table recognition mode and entry address mode */
la t0, _start la t0, _start
ori t0, t0, 3 ori t0, t0, 3
csrw mtvec, t0 csrw mtvec, t0

84
User/main.c
View file

@ -7,19 +7,6 @@
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*******************************************************************************/ *******************************************************************************/
/*
*@Note
轮询收发模式例程：
Master：USART1_Tx(PD5)、USART1_Rx(PD6)。
本例程演示 USART1 收到CH341发送的数据取反发出（波特率 115200）。
注：
硬件连线：PD5 —— Rx
PD6 —— Tx
*/
#include "debug.h" #include "debug.h"
@ -27,40 +14,25 @@
/* Global Variable */ /* Global Variable */
vu8 val;
/********************************************************************* /*********************************************************************
* @fn USARTx_CFG * @fn GPIO_Toggle_INIT
* *
* @brief Initializes the USART2 & USART3 peripheral. * @brief Initializes GPIOD.4
* *
* @return none * @return none
*/ */
void USARTx_CFG(void) void GPIO_LED_Init(void) {
{ GPIO_InitTypeDef GPIO_InitStructure = {0};
GPIO_InitTypeDef GPIO_InitStructure = {0};
USART_InitTypeDef USART_InitStructure = {0};
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
/* USART1 TX-->D.5 RX-->D.6 */ GPIO_StructInit(&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure); GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
USART_Init(USART1, &USART_InitStructure);
USART_Cmd(USART1, ENABLE);
} }
/********************************************************************* /*********************************************************************
@ -70,27 +42,27 @@ void USARTx_CFG(void)
* *
* @return none * @return none
*/ */
int main(void) int main(void) {
{ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); SystemCoreClockUpdate();
Delay_Init(); Delay_Init();
#if (SDI_PRINT == SDI_PR_OPEN)
SDI_Printf_Enable();
#else
USART_Printf_Init(115200); USART_Printf_Init(115200);
printf("SystemClk:%d\r\n",SystemCoreClock); #endif
printf("SystemClk: %ld\r\n", SystemCoreClock);
printf("DeviceID: %08lx\r\n", DBGMCU_GetDEVID());
printf("ChipID: %08lx\r\n", DBGMCU_GetCHIPID());
USARTx_CFG(); GPIO_LED_Init();
while(1) while(1) {
{ Delay_Ms(1000);
printf("On\r\n");
while(USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET) GPIO_WriteBit(GPIOD, GPIO_Pin_4, Bit_SET);
{ Delay_Ms(1000);
/* waiting for receiving finish */ printf("Off\r\n");
} GPIO_WriteBit(GPIOD, GPIO_Pin_4, Bit_RESET);
val = (USART_ReceiveData(USART1));
USART_SendData(USART1, ~val);
while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)
{
/* waiting for sending finish */
}
} }
} }

20
User/system_ch32v00x.c
View file

@ -9,18 +9,18 @@
*********************************************************************************/ *********************************************************************************/
#include <ch32v00x.h> #include <ch32v00x.h>
/* /*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source). * reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source. * If none of the define below is enabled, the HSI is used as System clock source.
*/ */
//#define SYSCLK_FREQ_8MHz_HSI 8000000 //#define SYSCLK_FREQ_8MHz_HSI 8000000
//#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE //#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE
//#define SYSCLK_FREQ_48MHZ_HSI 48000000 #define SYSCLK_FREQ_48MHZ_HSI 48000000
//#define SYSCLK_FREQ_8MHz_HSE 8000000 //#define SYSCLK_FREQ_8MHz_HSE 8000000
//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE //#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE
#define SYSCLK_FREQ_48MHz_HSE 48000000 //#define SYSCLK_FREQ_48MHz_HSE 48000000
/* Clock Definitions */ /* Clock Definitions */
#ifdef SYSCLK_FREQ_8MHz_HSI #ifdef SYSCLK_FREQ_8MHz_HSI
@ -153,10 +153,10 @@ static void SetSysClock(void)
#elif defined SYSCLK_FREQ_48MHz_HSE #elif defined SYSCLK_FREQ_48MHz_HSE
SetSysClockTo_48MHz_HSE(); SetSysClockTo_48MHz_HSE();
#endif #endif
/* If none of the define above is enabled, the HSI is used as System clock£¬ /* If none of the define above is enabled, the HSI is used as System clock£¬
* source (default after reset) * source (default after reset)
*/ */
} }
@ -229,7 +229,7 @@ static void SetSysClockTo_48MHZ_HSI(void)
} }
/* Select PLL as system clock source */ /* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */ /* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{ {
@ -438,4 +438,4 @@ static void SetSysClockTo_48MHz_HSE(void)