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Merge pull request 'Update CH32V003 Template' (#1) from logan/CH32V00x:master into master

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Reviewed-on: #1
This commit is contained in:
Thomas Muller 2024-03-20 23:42:45 -04:00
commit ea84a7326e
42 changed files with 15157 additions and 14504 deletions
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18
CMakeLists.txt
View file

@ -1,11 +1,11 @@
cmake_minimum_required(VERSION 3.10)
project(main)
project(blink)
# set(CMAKE_VERBOSE_MAKEFILE ON)
set(CMAKE_C_COMPILER riscv-none-embed-gcc)
set(CMAKE_CXX_COMPILER riscv-none-embed-gcc)
set(CMAKE_OBJCOPY riscv-none-embed-objcopy)
set(CMAKE_SIZE riscv-none-embed-size)
set(CMAKE_C_COMPILER riscv-none-elf-gcc)
set(CMAKE_CXX_COMPILER riscv-none-elf-gcc)
set(CMAKE_OBJCOPY riscv-none-elf-objcopy)
set(CMAKE_SIZE riscv-none-elf-size)
set_property(SOURCE Startup/startup_ch32v00x.S PROPERTY LANGUAGE C)
@ -18,7 +18,8 @@ include_directories(Debug)
include_directories(Core)
include_directories(User)
include_directories(Peripheral/inc)
add_definitions(-march=rv32ec -mabi=ilp32e -msmall-data-limit=0 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common)
add_definitions(-Wall -Wextra -march=rv32ec_zicsr -mabi=ilp32e -msmall-data-limit=0 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common)
file(GLOB SOURCES "Debug/*.c" "Core/*.c" "User/*.c" "Peripheral/src/*.c" "Startup/*.S")
@ -31,5 +32,6 @@ add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}.siz
COMMAND ${CMAKE_SIZE}
ARGS --format=berkeley ${CMAKE_PROJECT_NAME}.elf)
add_executable(${CMAKE_PROJECT_NAME}.elf ${SOURCES} ${CMAKE_PROJECT_NAME}.hex ${CMAKE_PROJECT_NAME}.siz)
target_link_options(${CMAKE_PROJECT_NAME}.elf PRIVATE -T ${CMAKE_SOURCE_DIR}/Ld/Link.ld -march=rv32ec -mabi=ilp32e -nostartfiles -Xlinker -gc-sections --specs=nano.specs --specs=nosys.specs)
add_executable(${CMAKE_PROJECT_NAME}.elf ${SOURCES})
target_link_options(${CMAKE_PROJECT_NAME}.elf PRIVATE -T ${CMAKE_SOURCE_DIR}/Ld/Link.ld -march=rv32ec_zicsr -mabi=ilp32e -nostartfiles -Xlinker -gc-sections --specs=nano.specs --specs=nosys.specs -mcmodel=medany)

10
Core/core_riscv.c
View file

@ -1,11 +1,13 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Description : RISC-V Core Peripheral Access Layer Source File
* Version : V1.0.1
* Date : 2023/11/11
* Description : RISC-V V2 Core Peripheral Access Layer Source File for CH32V003
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <stdint.h>

117
Core/core_riscv.h
View file

@ -1,23 +1,29 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Description : RISC-V Core Peripheral Access Layer Header File
* Version : V1.0.1
* Date : 2023/12/21
* Description : RISC-V V2 Core Peripheral Access Layer Header File for CH32V003
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CORE_RISCV_H__
#define __CORE_RISCV_H__
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#define __I volatile /* defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#define __I volatile const /* defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
#define __O volatile /* defines 'write only' permissions */
#define __IO volatile /* defines 'read / write' permissions */
/* Standard Peripheral Library old types (maintained for legacy purpose) */
typedef __I uint32_t vuc32; /* Read Only */
@ -110,26 +116,28 @@ typedef struct
/*********************************************************************
* @fn __enable_irq
* This function is only used for Machine mode.
*
* @brief Enable Global Interrupt
*
* @return none
*/
RV_STATIC_INLINE void __enable_irq()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
{
__asm volatile ("csrw mstatus, %0" : : "r" (0x1888) );
__asm volatile ("csrs mstatus, %0" : : "r" (0x88) );
}
/*********************************************************************
* @fn __disable_irq
* This function is only used for Machine mode.
*
* @brief Disable Global Interrupt
*
* @return none
*/
RV_STATIC_INLINE void __disable_irq()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
__asm volatile ("csrw mstatus, %0" : : "r" (0x1800) );
__asm volatile ("csrc mstatus, %0" : : "r" (0x88) );
}
/*********************************************************************
@ -139,7 +147,7 @@ RV_STATIC_INLINE void __disable_irq()
*
* @return none
*/
RV_STATIC_INLINE void __NOP()
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
{
__asm volatile ("nop");
}
@ -147,13 +155,13 @@ RV_STATIC_INLINE void __NOP()
/*********************************************************************
* @fn NVIC_EnableIRQ
*
* @brief Disable Interrupt
* @brief Enable Interrupt
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@ -167,7 +175,7 @@ RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
*
* @return none
*/
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@ -179,10 +187,10 @@ RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - 1: Interrupt Pending Enable
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
@ -194,10 +202,10 @@ RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - 1: Interrupt Pending Enable
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
@ -211,7 +219,7 @@ RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
*
* @return none
*/
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@ -225,7 +233,7 @@ RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
*
* @return none
*/
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
@ -240,7 +248,7 @@ RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
* @return 1 - Interrupt Active
* 0 - Interrupt No Active
*/
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
@ -251,13 +259,16 @@ RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
* @brief Set Interrupt Priority
*
* @param IRQn - Interrupt Numbers
* priority: bit7 - pre-emption priority
* bit6 - subpriority
* bit[5-0] - reserved
*
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6] - Sub priority
* bit[5:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:6] - Sub priority
* bit[5:0] - Reserve
* @return none
*/
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
{
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
}
@ -275,6 +286,35 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
asm volatile ("wfi");
}
/*********************************************************************
* @fn _SEV
*
* @brief Set Event
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
{
uint32_t t;
t = NVIC->SCTLR;
NVIC->SCTLR |= (1<<3)|(1<<5);
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
}
/*********************************************************************
* @fn _WFE
*
* @brief Wait for Events
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
{
NVIC->SCTLR |= (1<<3);
asm volatile ("wfi");
}
/*********************************************************************
* @fn __WFE
*
@ -284,13 +324,9 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
{
uint32_t t;
t = NVIC->SCTLR;
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
asm volatile ("wfi");
asm volatile ("wfi");
_SEV();
_WFE();
_WFE();
}
/*********************************************************************
@ -305,7 +341,8 @@ __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
*
* @return none
*/
RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
{
if(num > 1) return ;
if (NewState != DISABLE)
@ -313,7 +350,8 @@ RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, Func
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
}
else{
else
{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
}
@ -326,7 +364,7 @@ RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, Func
*
* @return none
*/
RV_STATIC_INLINE void NVIC_SystemReset(void)
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
{
NVIC->CFGR = NVIC_KEY3|(1<<7);
}
@ -351,6 +389,9 @@ extern uint32_t __get_MIMPID(void);
extern uint32_t __get_MHARTID(void);
extern uint32_t __get_SP(void);
#ifdef __cplusplus
}
#endif
#endif/* __CORE_RISCV_H__ */

136
Debug/debug.c
View file

@ -5,14 +5,19 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for UART
* Printf , Delay functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <debug.h>
static uint8_t p_us = 0;
static uint16_t p_ms = 0;
#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE00000F4)
#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE00000F8)
/*********************************************************************
* @fn Delay_Init
*
@ -23,7 +28,31 @@ static uint16_t p_ms = 0;
void Delay_Init(void)
{
p_us = SystemCoreClock / 8000000;
p_ms = (uint16_t)p_us * 1000;
p_ms = p_us * 1000;
SysTick->CTLR &= ~0x8000001F;
SysTick->CNT = 0;
SysTick->CTLR |= (1 << 0);
}
uint64_t SysTick_Read(void)
{
uint64_t ticks;
SysTick->CTLR &= ~(1 << 0);
ticks = SysTick->CNT;
SysTick->CTLR |= (1 << 0);
return ticks;
}
uint64_t SysTick_Us(void)
{
return SysTick_Read() / p_us;
}
uint64_t SysTick_Ms(void)
{
return SysTick_Read() / p_ms;
}
/*********************************************************************
@ -42,12 +71,18 @@ void Delay_Us(uint32_t n)
SysTick->SR &= ~(1 << 0);
i = (uint32_t)n * p_us;
SysTick->CMP = SysTick_Read() + i;
while((SysTick->SR & (1 << 0)) != (1 << 0));
/*
SysTick->CMP = i;
SysTick->CNT = 0;
SysTick->CTLR |= (1 << 4);
SysTick->CTLR |= (1 << 5) | (1 << 0);
while((SysTick->SR & (1 << 0)) != (1 << 0));
SysTick->CTLR &= ~(1 << 0);
*/
}
/*********************************************************************
@ -66,12 +101,17 @@ void Delay_Ms(uint32_t n)
SysTick->SR &= ~(1 << 0);
i = (uint32_t)n * p_ms;
SysTick->CMP = SysTick_Read() + i;
while((SysTick->SR & (1 << 0)) != (1 << 0));
/*
SysTick->CMP = i;
SysTick->CNT = 0;
SysTick->CTLR |= (1 << 4);
SysTick->CTLR |= (1 << 5) | (1 << 0);
while((SysTick->SR & (1 << 0)) != (1 << 0));
SysTick->CTLR &= ~(1 << 0);
*/
}
/*********************************************************************
@ -88,6 +128,7 @@ void USART_Printf_Init(uint32_t baudrate)
GPIO_InitTypeDef GPIO_InitStructure;
USART_InitTypeDef USART_InitStructure;
#if (DEBUG == DEBUG_UART1_NoRemap)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
@ -95,6 +136,35 @@ void USART_Printf_Init(uint32_t baudrate)
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#elif (DEBUG == DEBUG_UART1_Remap1)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
GPIO_PinRemapConfig(GPIO_PartialRemap1_USART1, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#elif (DEBUG == DEBUG_UART1_Remap2)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
GPIO_PinRemapConfig(GPIO_PartialRemap2_USART1, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOD, &GPIO_InitStructure);
#elif (DEBUG == DEBUG_UART1_Remap3)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_USART1 | RCC_APB2Periph_AFIO, ENABLE);
GPIO_PinRemapConfig(GPIO_FullRemap_USART1, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOC, &GPIO_InitStructure);
#endif
USART_InitStructure.USART_BaudRate = baudrate;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
@ -106,6 +176,22 @@ void USART_Printf_Init(uint32_t baudrate)
USART_Cmd(USART1, ENABLE);
}
/*********************************************************************
* @fn SDI_Printf_Enable
*
* @brief Initializes the SDI printf Function.
*
* @param None
*
* @return None
*/
void SDI_Printf_Enable(void)
{
*(DEBUG_DATA0_ADDRESS) = 0;
Delay_Init();
Delay_Ms(1);
}
/*********************************************************************
* @fn _write
*
@ -119,14 +205,51 @@ void USART_Printf_Init(uint32_t baudrate)
__attribute__((used))
int _write(int fd, char *buf, int size)
{
int i;
int i = 0;
int writeSize = size;
#if (SDI_PRINT == SDI_PR_OPEN)
do
{
/**
* data0 data1 8 bytes
* data0 The lowest byte storage length, the maximum is 7
*
*/
while( (*(DEBUG_DATA0_ADDRESS) != 0u))
{
}
if(writeSize>7)
{
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
i += 7;
writeSize -= 7;
}
else
{
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
writeSize = 0;
}
} while (writeSize);
#else
for(i = 0; i < size; i++){
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
USART_SendData(USART1, *buf++);
}
return size;
#endif
return writeSize;
}
/*********************************************************************
@ -136,6 +259,7 @@ int _write(int fd, char *buf, int size)
*
* @return size: Data length
*/
__attribute__((used))
void *_sbrk(ptrdiff_t incr)
{
extern char _end[];

33
Debug/debug.h
View file

@ -5,24 +5,51 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for UART
* Printf , Delay functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __DEBUG_H
#define __DEBUG_H
#ifdef __cplusplus
extern "C" {
#endif
#include <ch32v00x.h>
#include <stdio.h>
/* UART Printf Definition */
#define DEBUG_UART1 1
#define DEBUG_UART1_NoRemap 1 //Tx-PD5
#define DEBUG_UART1_Remap1 2 //Tx-PD0
#define DEBUG_UART1_Remap2 3 //Tx-PD6
#define DEBUG_UART1_Remap3 4 //Tx-PC0
/* DEBUG UATR Definition */
#define DEBUG DEBUG_UART1
#ifndef DEBUG
#define DEBUG DEBUG_UART1_NoRemap
#endif
/* SDI Printf Definition */
#define SDI_PR_CLOSE 0
#define SDI_PR_OPEN 1
#ifndef SDI_PRINT
#define SDI_PRINT SDI_PR_CLOSE
#endif
void Delay_Init(void);
uint64_t SysTick_Read(void);
uint64_t SysTick_Us(void);
uint64_t SysTick_Ms(void);
void Delay_Us(uint32_t n);
void Delay_Ms(uint32_t n);
void USART_Printf_Init(uint32_t baudrate);
void SDI_Printf_Enable(void);
#ifdef __cplusplus
}
#endif
#endif /* __DEBUG_H */

2
Ld/Link.ld
View file

@ -1,6 +1,6 @@
ENTRY( _start )
__stack_size = 512;
__stack_size = 256;
PROVIDE( _stack_size = __stack_size );

469
Peripheral/inc/ch32v00x.h
View file

@ -2,10 +2,12 @@
* File Name : ch32v00x.h
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/25
* Description : CH32V00x Device Peripheral Access Layer Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_H
#define __CH32V00x_H
@ -24,6 +26,11 @@ extern "C" {
#define HSI_VALUE ((uint32_t)24000000) /* Value of the Internal oscillator in Hz */
/* CH32V00x Standard Peripheral Library version number */
#define __CH32V00x_STDPERIPH_VERSION_MAIN (0x01) /* [15:8] main version */
#define __CH32V00x_STDPERIPH_VERSION_SUB (0x07) /* [7:0] sub version */
#define __CH32V00x_STDPERIPH_VERSION ( (__CH32V00x_STDPERIPH_VERSION_MAIN << 8)\
|(__CH32V00x_STDPERIPH_VERSION_SUB << 0))
/* Interrupt Number Definition, according to the selected device */
typedef enum IRQn
@ -328,7 +335,6 @@ typedef struct
typedef struct
{
__IO uint32_t EXTEN_CTR;
__IO uint32_t EXTEN_KR;
} EXTEN_TypeDef;
/* Peripheral memory map */
@ -368,9 +374,11 @@ typedef struct
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */
#define DBGMCU_BASE ((uint32_t)0xE000D000)
#define EXTEN_BASE ((uint32_t)0x40023800)
#define VENDOR_CFG0_BASE ((uint32_t)0x1FFFF7D4)
#define CFG0_PLL_TRIM (VENDOR_CFG0_BASE)
/* Peripheral declaration */
#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
@ -397,7 +405,6 @@ typedef struct
#define RCC ((RCC_TypeDef *)RCC_BASE)
#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
#define OB ((OB_TypeDef *)OB_BASE)
#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
/******************************************************************************/
@ -437,14 +444,11 @@ typedef struct
#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */
#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */
#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */
#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */
#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */
#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */
#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */
#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */
#define ADC_CALVOLSELECT ((uint32_t)0x06000000)
#define ADC_CALVOLSELECT_0 ((uint32_t)0x02000000)
#define ADC_CALVOLSELECT_1 ((uint32_t)0x04000000)
/******************* Bit definition for ADC_CTLR2 register ********************/
#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */
@ -469,7 +473,6 @@ typedef struct
#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */
#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */
#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */
#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */
/****************** Bit definition for ADC_SAMPTR1 register *******************/
#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
@ -502,16 +505,6 @@ typedef struct
#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */
#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */
#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */
#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */
#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */
#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */
#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */
#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */
/****************** Bit definition for ADC_SAMPTR2 register *******************/
#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */
@ -564,22 +557,22 @@ typedef struct
#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */
/****************** Bit definition for ADC_IOFR1 register *******************/
#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */
#define ADC_JOFFSET1 ((uint16_t)0x03FF) /* Data offset for injected channel 1 */
/****************** Bit definition for ADC_IOFR2 register *******************/
#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */
#define ADC_JOFFSET2 ((uint16_t)0x03FF) /* Data offset for injected channel 2 */
/****************** Bit definition for ADC_IOFR3 register *******************/
#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */
#define ADC_JOFFSET3 ((uint16_t)0x03FF) /* Data offset for injected channel 3 */
/****************** Bit definition for ADC_IOFR4 register *******************/
#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */
#define ADC_JOFFSET4 ((uint16_t)0x03FF) /* Data offset for injected channel 4 */
/******************* Bit definition for ADC_WDHTR register ********************/
#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */
#define ADC_HT ((uint16_t)0x03FF) /* Analog watchdog high threshold */
/******************* Bit definition for ADC_WDLTR register ********************/
#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */
#define ADC_LT ((uint16_t)0x03FF) /* Analog watchdog low threshold */
/******************* Bit definition for ADC_RSQR1 register *******************/
#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
@ -748,8 +741,11 @@ typedef struct
#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */
/******************** Bit definition for ADC_RDATAR register ********************/
#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */
#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */
#define ADC_RDATAR_DATA ((uint32_t)0xFFFFFFFF) /* Regular data */
/******************** Bit definition for ADC_DLYR register ********************/
#define ADC_DLYR_DLYVLU ((uint32_t)0x1FF)
#define ADC_DLYR_DLYSRC ((uint32_t)0x200)
/******************************************************************************/
/* DMA Controller */
@ -1142,6 +1138,8 @@ typedef struct
#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */
#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */
#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */
#define FLASH_STATR_MODE ((uint16_t)0x4000)
#define FLASH_STATR_LOCK ((uint16_t)0x8000)
/******************* Bit definition for FLASH_CTLR register *******************/
#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */
@ -1154,10 +1152,11 @@ typedef struct
#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */
#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */
#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */
#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 64Byte */
#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 64Byte */
#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */
#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */
#define FLASH_CTLR_FLOCK ((uint16_t)0x8000)
#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 64Byte */
#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 64Byte */
#define FLASH_CTLR_BUF_LOAD ((uint32_t)0x00040000) /* Buffer Load */
#define FLASH_CTLR_BUF_RST ((uint32_t)0x00080000) /* Buffer Reset */
/******************* Bit definition for FLASH_ADDR register *******************/
#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */
@ -1168,9 +1167,12 @@ typedef struct
#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008)
#define FLASH_OBR_STANDY_RST ((uint16_t)0x0010)
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010)
#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */
#define FLASH_OBR_STATR_MODE ((uint16_t)0x0080)
#define FLASH_OBR_FIX_11 ((uint16_t)0x0300)
/****************** Bit definition for FLASH_WPR register ******************/
#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */
@ -1199,6 +1201,13 @@ typedef struct
#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
/****************** Bit definition for FLASH_MODEKEYR register ******************/
#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB)
/****************** Bit definition for FLASH__BOOT_MODEKEYR register ******************/
#define FLASH_BOOT_MODEKEYR_KEY1 ((uint32_t)0x45670123)
#define FLASH_BOOT_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB)
/******************************************************************************/
/* General Purpose and Alternate Function I/O */
@ -1273,75 +1282,6 @@ typedef struct
#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */
#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */
/******************* Bit definition for GPIO_CFGHR register *******************/
#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */
#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */
#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */
#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */
#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */
#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */
#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */
#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */
#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */
#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */
#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */
#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */
#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */
#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */
#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */
#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */
#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */
#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */
#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */
#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */
#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */
#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */
#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */
#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */
#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */
#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */
#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */
#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */
#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */
#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */
#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */
#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */
#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */
/******************* Bit definition for GPIO_INDR register *******************/
#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */
#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */
@ -1351,14 +1291,6 @@ typedef struct
#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */
#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */
#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */
#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */
#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */
#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */
#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */
#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */
#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */
#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */
#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */
/******************* Bit definition for GPIO_OUTDR register *******************/
#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */
@ -1369,14 +1301,6 @@ typedef struct
#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */
#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */
#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */
#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */
#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */
#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */
#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */
#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */
#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */
#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */
#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */
/****************** Bit definition for GPIO_BSHR register *******************/
#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */
@ -1387,14 +1311,6 @@ typedef struct
#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */
#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */
#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */
#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */
#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */
#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */
#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */
#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */
#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */
#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */
#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */
#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */
#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */
@ -1404,14 +1320,6 @@ typedef struct
#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */
#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */
#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */
#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */
#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */
#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */
#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */
#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */
#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */
#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */
#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */
/******************* Bit definition for GPIO_BCR register *******************/
#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */
@ -1422,14 +1330,6 @@ typedef struct
#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */
#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */
#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */
#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */
#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */
#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */
#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */
#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */
#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */
#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */
#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */
/****************** Bit definition for GPIO_LCKR register *******************/
#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */
@ -1440,29 +1340,12 @@ typedef struct
#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */
#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */
#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */
#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */
#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */
#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */
#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */
#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */
#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */
#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */
#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */
#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */
#define GPIO_LCKK ((uint32_t)0x00000100)
/****************** Bit definition for AFIO_PCFR1register *******************/
#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */
#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */
#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */
#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */
#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */
#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */
#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */
@ -1470,6 +1353,7 @@ typedef struct
#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP_1 ((uint32_t)0x00000080)
#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
@ -1481,78 +1365,65 @@ typedef struct
#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */
#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */
#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */
#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */
#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */
#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */
#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
#define AFIO_PCFR1_USART1_HIGH_BIT_REMAP ((uint32_t)0x00200000)
#define AFIO_PCFR1_I2C1_HIGH_BIT_REMAP ((uint32_t)0x00400000)
#define AFIO_PCFR1_TIM1_1_RM ((uint32_t)0x00800000)
#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */
#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */
#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */
#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000)
#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000)
#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000)
#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
/***************** Bit definition for AFIO_EXTICR1 register *****************/
#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */
#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */
#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */
#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */
#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x0003) /* EXTI 0 configuration */
#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x000C) /* EXTI 1 configuration */
#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0030) /* EXTI 2 configuration */
#define AFIO_EXTICR1_EXTI3 ((uint16_t)0x00C0) /* EXTI 3 configuration */
#define AFIO_EXTICR1_EXTI4 ((uint16_t)0x0300)
#define AFIO_EXTICR1_EXTI5 ((uint16_t)0x0C00)
#define AFIO_EXTICR1_EXTI6 ((uint16_t)0x3000)
#define AFIO_EXTICR1_EXTI7 ((uint16_t)0xC000)
#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */
#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */
#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */
#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */
#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */
#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */
#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */
#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */
#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */
#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */
#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */
#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */
#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */
#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */
#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0008) /* PC[1] pin */
#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x000C) /* PD[1] pin */
#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */
#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */
#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */
#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */
#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */
#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */
#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */
#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0020) /* PC[2] pin */
#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0030) /* PD[2] pin */
#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */
#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */
#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */
#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */
#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */
#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */
#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */
#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x0080) /* PC[3] pin */
#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x00C0) /* PD[3] pin */
#define AFIO_EXTICR1_EXTI4_PA ((uint16_t)0x0000)
#define AFIO_EXTICR1_EXTI4_PC ((uint16_t)0x0200)
#define AFIO_EXTICR1_EXTI4_PD ((uint16_t)0x0300)
#define AFIO_EXTICR1_EXTI5_PA ((uint16_t)0x0000)
#define AFIO_EXTICR1_EXTI5_PC ((uint16_t)0x0800)
#define AFIO_EXTICR1_EXTI5_PD ((uint16_t)0x0C00)
#define AFIO_EXTICR1_EXTI6_PA ((uint16_t)0x0000)
#define AFIO_EXTICR1_EXTI6_PC ((uint16_t)0x2000)
#define AFIO_EXTICR1_EXTI6_PD ((uint16_t)0x3000)
#define AFIO_EXTICR1_EXTI7_PA ((uint16_t)0x0000)
#define AFIO_EXTICR1_EXTI7_PC ((uint16_t)0x8000)
#define AFIO_EXTICR1_EXTI7_PD ((uint16_t)0xC000)
/******************************************************************************/
/* Independent WATCHDOG */
@ -1580,9 +1451,6 @@ typedef struct
/******************* Bit definition for I2C_CTLR1 register ********************/
#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */
#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */
#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */
#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */
#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */
#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */
#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */
@ -1591,7 +1459,6 @@ typedef struct
#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */
#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */
#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */
#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */
#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */
/******************* Bit definition for I2C_CTLR2 register ********************/
@ -1646,16 +1513,12 @@ typedef struct
#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */
#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */
#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */
#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */
#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */
/******************* Bit definition for I2C_STAR2 register ********************/
#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */
#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */
#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */
#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */
#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */
#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */
#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */
#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */
@ -1669,10 +1532,7 @@ typedef struct
/******************************************************************************/
/******************** Bit definition for PWR_CTLR register ********************/
#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */
#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */
#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */
#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */
#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */
#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
@ -1680,22 +1540,41 @@ typedef struct
#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */
#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */
#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */
#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */
#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */
#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */
#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */
#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */
#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */
#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */
#define PWR_PVDLevel_0 ((uint16_t)0x0000)
#define PWR_PVDLevel_1 ((uint16_t)0x0020)
#define PWR_PVDLevel_2 ((uint16_t)0x0040)
#define PWR_PVDLevel_3 ((uint16_t)0x0060)
#define PWR_PVDLevel_4 ((uint16_t)0x0080)
#define PWR_PVDLevel_5 ((uint16_t)0x00A0)
#define PWR_PVDLevel_6 ((uint16_t)0x00C0)
#define PWR_PVDLevel_7 ((uint16_t)0x00E0)
#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */
/******************* Bit definition for PWR_AWUCSR register ********************/
#define PWR_AWUCSR_AWUEN ((uint16_t)0x0002)
/******************* Bit definition for PWR_CSR register ********************/
#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */
#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */
#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */
#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */
/******************* Bit definition for PWR_AWUWR register ********************/
#define PWR_AWUWR ((uint16_t)0x003F)
/******************* Bit definition for PWR_AWUWR register ********************/
#define PWR_AWUPSC ((uint16_t)0x000F)
#define PWR_AWUPSC_0 ((uint16_t)0x0000)
#define PWR_AWUPSC_2 ((uint16_t)0x0002)
#define PWR_AWUPSC_4 ((uint16_t)0x0003)
#define PWR_AWUPSC_8 ((uint16_t)0x0004)
#define PWR_AWUPSC_16 ((uint16_t)0x0005)
#define PWR_AWUPSC_32 ((uint16_t)0x0006)
#define PWR_AWUPSC_64 ((uint16_t)0x0007)
#define PWR_AWUPSC_128 ((uint16_t)0x0008)
#define PWR_AWUPSC_256 ((uint16_t)0x0009)
#define PWR_AWUPSC_512 ((uint16_t)0x000A)
#define PWR_AWUPSC_1024 ((uint16_t)0x000B)
#define PWR_AWUPSC_2048 ((uint16_t)0x000C)
#define PWR_AWUPSC_4096 ((uint16_t)0x000D)
#define PWR_AWUPSC_10240 ((uint16_t)0x000E)
#define PWR_AWUPSC_61440 ((uint16_t)0x000F)
/******************************************************************************/
/* Reset and Clock Control */
@ -1750,31 +1629,12 @@ typedef struct
#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */
#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */
#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */
#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */
#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */
#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */
#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */
#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */
#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */
#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */
#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */
#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */
#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */
#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */
#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */
#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */
#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */
#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */
#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */
#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */
#define RCC_ADCPRE ((uint32_t)0x0000F800) /* ADCPRE[4:0] bits (ADC prescaler) */
#define RCC_ADCPRE_0 ((uint32_t)0x00000800) /* Bit 0 */
#define RCC_ADCPRE_1 ((uint32_t)0x00001000) /* Bit 1 */
#define RCC_ADCPRE_2 ((uint32_t)0x00002000)
#define RCC_ADCPRE_3 ((uint32_t)0x00004000)
#define RCC_ADCPRE_4 ((uint32_t)0x00008000)
#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */
#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */
@ -1782,38 +1642,9 @@ typedef struct
#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */
#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */
#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */
#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */
#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */
#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */
#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */
#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */
#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */
#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */
#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */
#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */
#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */
#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */
#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */
#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */
#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */
#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */
#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */
#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */
#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */
#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */
#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */
#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */
#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */
#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */
#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */
#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */
#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */
@ -1827,18 +1658,15 @@ typedef struct
/******************* Bit definition for RCC_INTR register ********************/
#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */
#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */
#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */
#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */
#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */
#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */
#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */
#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */
#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */
#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */
#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */
#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */
#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */
#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */
#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */
#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */
@ -1847,71 +1675,43 @@ typedef struct
/***************** Bit definition for RCC_APB2PRSTR register *****************/
#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */
#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */
#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */
#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */
#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */
#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */
#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */
#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */
#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */
#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */
#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */
/***************** Bit definition for RCC_APB1PRSTR register *****************/
#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */
#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */
#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */
#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */
#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */
#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */
#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */
#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */
#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */
#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */
#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */
#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */
#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */
/****************** Bit definition for RCC_AHBPCENR register ******************/
#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */
#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */
#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */
#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */
#define RCC_USBHD ((uint16_t)0x1000)
/****************** Bit definition for RCC_APB2PCENR register *****************/
#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */
#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */
#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */
#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */
#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */
#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */
#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */
#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */
#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */
/***************** Bit definition for RCC_APB1PCENR register ******************/
#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/
#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */
#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */
#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */
#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */
#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */
#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */
#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */
/******************* Bit definition for RCC_RSTSCKR register ********************/
#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
@ -1938,6 +1738,7 @@ typedef struct
#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */
#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */
#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080)
#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */
#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */
#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */
@ -1977,6 +1778,9 @@ typedef struct
/****************** Bit definition for SPI_TCRCR register ******************/
#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */
/****************** Bit definition for SPI_HSCR register ******************/
#define SPI_HSCR_HSRXEN ((uint16_t)0x0001)
/******************************************************************************/
/* TIM */
/******************************************************************************/
@ -2197,7 +2001,6 @@ typedef struct
#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */
#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */
#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */
#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */
/******************* Bit definition for TIM_CNT register ********************/
#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */
@ -2301,7 +2104,6 @@ typedef struct
#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */
#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */
#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */
#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */
/****************** Bit definition for USART_CTLR2 register *******************/
#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */
@ -2330,7 +2132,6 @@ typedef struct
#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */
#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */
#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */
#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */
/****************** Bit definition for USART_GPR register ******************/
#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */
@ -2385,31 +2186,11 @@ typedef struct
/******************************************************************************/
/**************************** Enhanced register *****************************/
#define EXTEN_PLLCLK_DLY ((uint32_t)0x0000000F) /* PLLCLK_DLY[3:0] */
#define EXTEN_PLLCLK_DLY_No ((uint32_t)0x00000001)
#define EXTEN_PLLCLK_DLY_6ns ((uint32_t)0x00000004)
#define EXTEN_PLLCLK_DLY_8ns ((uint32_t)0x00000005)
#define EXTEN_PLLCLK_DLY_9ns ((uint32_t)0x00000006)
#define EXTEN_PLLCLK_DLY_10ns ((uint32_t)0x00000007)
#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */
#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */
#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */
#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */
#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */
#define EXTEN_ULLDO_TRIM2 ((uint32_t)0x00000300) /* Bit [1:0] */
#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */
#define EXTEN_FLASH_CLK_TRIM ((uint32_t)0x00003800) /* FLASH_CLK_TRIM[2:0] bits */
#define EXTEN_FLASH_CLK_TRIM_0ns ((uint32_t)0x0000800)
#define EXTEN_FLASH_CLK_TRIM_1ns ((uint32_t)0x00001000)
#define EXTEN_FLASH_CLK_TRIM_2ns ((uint32_t)0x00002000)
#define EXTEN_FLASH_CLK_TRIM_3ns ((uint32_t)0x00003000)
#define EXTEN_WR_EN ((uint32_t)0x00004000)
#define EXTEN_WR_LOCK ((uint32_t)0x00008000)
#define EXTEN_OPA_EN ((uint32_t)0x00010000)
#define EXTEN_OPA_NSEL ((uint32_t)0x00020000)
#define EXTEN_OPA_PSEL ((uint32_t)0x00040000)

4
Peripheral/inc/ch32v00x_adc.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_ADC_H
#define __CH32V00x_ADC_H

6
Peripheral/inc/ch32v00x_dbgmcu.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* DBGMCU firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_DBGMCU_H
#define __CH32V00x_DBGMCU_H
@ -28,7 +30,7 @@ uint32_t DBGMCU_GetDEVID(void);
uint32_t __get_DEBUG_CR(void);
void __set_DEBUG_CR(uint32_t value);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
uint32_t DBGMCU_GetCHIPID( void );
#ifdef __cplusplus
}
#endif

4
Peripheral/inc/ch32v00x_dma.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_DMA_H
#define __CH32V00x_DMA_H

4
Peripheral/inc/ch32v00x_exti.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_EXTI_H
#define __CH32V00x_EXTI_H

22
Peripheral/inc/ch32v00x_flash.h
View file

@ -2,11 +2,13 @@
* File Name : ch32v00x_flash.h
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/25
* Description : This file contains all the functions prototypes for the FLASH
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_FLASH_H
#define __CH32V00x_FLASH_H
@ -24,7 +26,10 @@ typedef enum
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT
FLASH_TIMEOUT,
FLASH_OP_RANGE_ERROR = 0xFD,
FLASH_ALIGN_ERROR = 0xFE,
FLASH_ADR_RANGE_ERROR = 0xFF,
} FLASH_Status;
/* Flash_Latency */
@ -68,7 +73,11 @@ typedef enum
#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/
#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */
#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */
#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */
#define OB_RST_EN_DT128us ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128us */
/* Option_Bytes_Power_ON_Start_Mode */
#define OB_PowerON_Start_Mode_BOOT ((uint16_t)0x0020) /* from Boot after power on */
#define OB_PowerON_Start_Mode_USER ((uint16_t)0x0000) /* from User after power on */
/* FLASH_Interrupts */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
@ -103,7 +112,7 @@ FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY, uint16_t OB_RST);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
@ -118,6 +127,9 @@ void FLASH_BufReset(void);
void FLASH_BufLoad(uint32_t Address, uint32_t Data0);
void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address);
void SystemReset_StartMode(uint32_t Mode);
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
#ifdef __cplusplus
}

4
Peripheral/inc/ch32v00x_gpio.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_GPIO_H
#define __CH32V00x_GPIO_H

238
Peripheral/inc/ch32v00x_i2c.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* I2C firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_I2C_H
#define __CH32V00x_I2C_H
@ -118,27 +120,169 @@ typedef struct
/****************I2C Master Events (Events grouped in order of communication)********************/
/********************************************************************************************************************
* @brief Start communicate
*
* After master use I2C_GenerateSTART() function sending the START condition,the master
* has to wait for event 5(the Start condition has been correctly
* released on the I2C bus ).
*
*/
/* EVT5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/********************************************************************************************************************
* @brief Address Acknowledge
*
* When start condition correctly released on the bus(check EVT5), the
* master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
* it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will be set:
*
*
*
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set.
*
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set
*
* 3) In case of 10-Bit addressing mode, the master (after generating the START
* and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
* Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
* on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
* of the 10-bit address (LSB) . Then master should wait for event 6.
*
*
*/
/* EVT6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/*EVT9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/********************************************************************************************************************
* @brief Communication events
*
* If START condition has generated and slave address
* been acknowledged. then the master has to check one of the following events for
* communication procedures:
*
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use
* I2C_ReceiveData() function to read the data received from the slave .
*
* 2) Master Transmitter mode: The master use I2C_SendData() function to send data
* then to wait on event EVT8 or EVT8_2.
* These two events are similar:
* - EVT8 means that the data has been written in the data register and is
* being shifted out.
* - EVT8_2 means that the data has been physically shifted out and output
* on the bus.
* In most cases, using EVT8 is sufficient for the application.
* Using EVT8_2 will leads to a slower communication speed but will more reliable .
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
*
*
* Note:
* In case the user software does not guarantee that this event EVT7 is managed before
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
*
*
*/
/* Master Receive mode */
/* EVT7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master Transmitter mode*/
/* EVT8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* EVT8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/******************I2C Slave Events (Events grouped in order of communication)******************/
/********************************************************************************************************************
* @brief Start Communicate events
*
* Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a start condition of master device generate on the bus.
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
*
*
*
* a) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER).
*
* b) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set.
*
* c) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
*
*/
/* EVT1 */
/* a) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* b) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* c) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/********************************************************************************************************************
* @brief Communication events
*
* Wait on one of these events when EVT1 has already been checked :
*
* - Slave Receiver mode:
* - EVT2--The device is expecting to receive a data byte .
* - EVT4--The device is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped.
*
* - Slave Transmitter mode:
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
* the EVT3 is managed before the current byte end of transfer The second one can optionally
* be used.
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission
* shall end . The slave device has to stop sending
* data bytes and wait a Stop condition from bus.
*
* Note:
* If the user software does not guarantee that the event 2 is
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time .
* In this case the communication will be slower.
*
*/
/* Slave Receiver mode*/
/* EVT2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* EVT4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave Transmitter mode -----------------------*/
/* EVT3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/*EVT3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
void I2C_DeInit(I2C_TypeDef *I2Cx);
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
@ -166,12 +310,98 @@ void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
/****************************************************************************************
* I2C State Monitoring Functions
****************************************************************************************/
/*****************************************************************************************
*
* I2C State Monitoring Functions
*
****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring
* profit the application requirements and constraints:
*
*
* a) First way:
* Using I2C_CheckEvent() function:
* It compares the status registers (STARR1 and STAR2) content to a given event
* (can be the combination of more flags).
* If the current status registers includes the given flags will return SUCCESS.
* and if the current status registers miss flags will returns ERROR.
* - When to use:
* - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual
* (CH32V03RM).
* - It is also suitable for users who need to define their own events.
* - Limitations:
* - If an error occurs besides to the monitored error,
* the I2C_CheckEvent() function may return SUCCESS despite the communication
* in corrupted state. it is suggeted to use error interrupts to monitor the error
* events and handle them in IRQ handler.
*
*
* Note:
* The following functions are recommended for error management: :
* - I2C_ITConfig() main function of configure and enable the error interrupts.
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
* Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
* to determine which error occurred.
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
* \ I2C_GenerateStop() will be use to clear the error flag and source,
* and return to correct communication status.
*
*
* b) Second way:
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
* - When to use:
*
* - This function is suitable for the same applications above but it
* don't have the limitations of I2C_GetFlagStatus() function .
* The returned value could be compared to events already defined in the
* library (CH32V00x_i2c.h) or to custom values defined by user.
* - This function can be used to monitor the status of multiple flags simultaneously.
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to
* accept the event according to the user's needs (when all event flags are set and
* no other flags are set, or only when the required flags are set)
*
* - Limitations:
* - User may need to define his own events.
* - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and
* ignores error flags).
*
*
* c) Third way:
* Using the function I2C_GetFlagStatus() get the status of
* one single flag .
* - When to use:
* - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed .
*
* - Limitations:
* - Call this function to access the status register. Some flag bits may be cleared.
* - Function may need to be called twice or more in order to monitor one single event.
*/
/*********************************************************
*
* a) Basic state monitoring(First way)
********************************************************
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/*********************************************************
*
* b) Advanced state monitoring(Second way:)
********************************************************
*/
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/*********************************************************
*
* c) Flag-based state monitoring(Third way)
*********************************************************
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);

4
Peripheral/inc/ch32v00x_iwdg.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_IWDG_H
#define __CH32V00x_IWDG_H

46
Peripheral/inc/ch32v00x_misc.h
View file

@ -2,11 +2,13 @@
* File Name : ch32v00x_misc.h
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/26
* Description : This file contains all the functions prototypes for the
* miscellaneous firmware library functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00X_MISC_H
#define __CH32V00X_MISC_H
@ -17,7 +19,34 @@
#include <ch32v00x.h>
/* NVIC Init Structure definition */
/* CSR_INTSYSCR_INEST_definition */
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
/* Check the configuration of CSR(0x804) in the startup file(.S)
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6] - Sub priority
* bit[5:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:6] - Sub priority
* bit[5:0] - Reserve
*/
#ifndef INTSYSCR_INEST
#define INTSYSCR_INEST INTSYSCR_INEST_EN
#endif
/* NVIC Init Structure definition
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 1.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
@ -26,13 +55,12 @@ typedef struct
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Preemption_Priority_Group */
#define NVIC_PriorityGroup_0 ((uint32_t)0x00)
#define NVIC_PriorityGroup_1 ((uint32_t)0x01)
#define NVIC_PriorityGroup_2 ((uint32_t)0x02)
#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
#else
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#endif
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);

4
Peripheral/inc/ch32v00x_opa.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* OPA firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_OPA_H
#define __CH32V00x_OPA_H

4
Peripheral/inc/ch32v00x_pwr.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the PWR
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_PWR_H
#define __CH32V00x_PWR_H

28
Peripheral/inc/ch32v00x_rcc.h
View file

@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_RCC_H
#define __CH32V00x_RCC_H
@ -64,17 +66,17 @@ typedef struct
/* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00000800)
#define RCC_PCLK2_Div6 ((uint32_t)0x00001000)
#define RCC_PCLK2_Div8 ((uint32_t)0x00001800)
#define RCC_PCLK2_Div12 ((uint32_t)0x00009000)
#define RCC_PCLK2_Div16 ((uint32_t)0x00009100)
#define RCC_PCLK2_Div24 ((uint32_t)0x0000B000)
#define RCC_PCLK2_Div32 ((uint32_t)0x0000B100)
#define RCC_PCLK2_Div48 ((uint32_t)0x0000D000)
#define RCC_PCLK2_Div64 ((uint32_t)0x0000D100)
#define RCC_PCLK2_Div96 ((uint32_t)0x0000F000)
#define RCC_PCLK2_Div128 ((uint32_t)0x0000F100)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000)
#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000)
#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800)
#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800)
#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000)
#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000)
#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
@ -124,7 +126,7 @@ void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLConfig(uint32_t RCC_PLLSource);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);

7
Peripheral/inc/ch32v00x_spi.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_SPI_H
#define __CH32V00x_SPI_H
@ -86,8 +88,9 @@ typedef struct
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
/* SPI_MSB transmission */
/* SPI_MSB_LSB transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode
/* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)

15
Peripheral/inc/ch32v00x_tim.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_TIM_H
#define __CH32V00x_TIM_H
@ -40,7 +42,7 @@ typedef struct
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
@ -54,7 +56,7 @@ typedef struct
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
@ -64,15 +66,15 @@ typedef struct
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
@note This parameter is valid only for TIM1. */
} TIM_OCInitTypeDef;
/* TIM Input Capture Init structure definition */
@ -498,6 +500,7 @@ FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState);
#ifdef __cplusplus
}

4
Peripheral/inc/ch32v00x_usart.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the
* USART firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_USART_H
#define __CH32V00x_USART_H

4
Peripheral/inc/ch32v00x_wwdg.h
View file

@ -5,8 +5,10 @@
* Date : 2022/08/08
* Description : This file contains all the functions prototypes for the WWDG
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V00x_WWDG_H
#define __CH32V00x_WWDG_H

8
Peripheral/src/ch32v00x_adc.c
View file

@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the ADC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_adc.h>
#include <ch32v00x_rcc.h>
@ -789,7 +791,7 @@ void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length)
* ADC_InjectedChannel_3 - Injected Channel3 selected.
* ADC_InjectedChannel_4 - Injected Channel4 selected.
* Offset - the offset value for the selected ADC injected channel.
* This parameter must be a 12bit value.
* This parameter must be a 10bit value.
*
* @return None
*/
@ -1051,7 +1053,7 @@ void ADC_Calibration_Vol(ADC_TypeDef *ADCx, uint32_t ADC_CALVOL)
*/
void ADC_ExternalTrig_DLY(ADC_TypeDef *ADCx, uint32_t channel, uint16_t DelayTim)
{
ADCx->DLYR &= ~(uint32_t)(0x2FF);
ADCx->DLYR &= ~(uint32_t)(0x3FF);
ADCx->DLYR |= channel;
ADCx->DLYR |= DelayTim;
}

23
Peripheral/src/ch32v00x_dbgmcu.c
View file

@ -4,9 +4,11 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the DBGMCU firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
****************************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_dbgmcu.h>
@ -95,5 +97,20 @@ void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
val &= ~(uint32_t)DBGMCU_Periph;
__set_DEBUG_CR(val);
}
}
/*********************************************************************
* @fn DBGMCU_GetCHIPID
*
* @brief Returns the CHIP identifier.
*
* @return Device identifier.
* ChipID List-
* CH32V003F4P6-0x003005x0
* CH32V003F4U6-0x003105x0
* CH32V003A4M6-0x003205x0
* CH32V003J4M6-0x003305x0
*/
uint32_t DBGMCU_GetCHIPID( void )
{
return( *( uint32_t * )0x1FFFF7C4 );
}

4
Peripheral/src/ch32v00x_dma.c
View file

@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the DMA firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_dma.h>
#include <ch32v00x_rcc.h>

6
Peripheral/src/ch32v00x_exti.c
View file

@ -4,9 +4,11 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the EXTI firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
***************************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_exti.h>
/* No interrupt selected */

260
Peripheral/src/ch32v00x_flash.c
View file

@ -2,11 +2,13 @@
* File Name : ch32v00x_flash.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/25
* Description : This file provides all the FLASH firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
***************************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_flash.h>
/* Flash Access Control Register bits */
@ -25,6 +27,7 @@
#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF)
#define CR_STRT_Set ((uint32_t)0x00000040)
#define CR_LOCK_Set ((uint32_t)0x00000080)
#define CR_FLOCK_Set ((uint32_t)0x00008000)
#define CR_PAGE_PG ((uint32_t)0x00010000)
#define CR_PAGE_ER ((uint32_t)0x00020000)
#define CR_BUF_LOAD ((uint32_t)0x00040000)
@ -54,10 +57,14 @@
#define EraseTimeout ((uint32_t)0x000B0000)
#define ProgramTimeout ((uint32_t)0x00002000)
/* Flash Program Vaild Address */
/* Flash Program Valid Address */
#define ValidAddrStart (FLASH_BASE)
#define ValidAddrEnd (FLASH_BASE + 0x4000)
/* FLASH Size */
#define Size_64B 0x40
#define Size_1KB 0x400
/********************************************************************************
* @fn FLASH_SetLatency
*
@ -416,9 +423,6 @@ FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
* @param OB_IWDG - Selects the IWDG mode
* OB_IWDG_SW - Software IWDG selected
* OB_IWDG_HW - Hardware IWDG selected
* OB_STOP - Reset event when entering STOP mode.
* OB_STOP_NoRST - No reset generated when entering in STOP
* OB_STOP_RST - Reset generated when entering in STOP
* OB_STDBY - Reset event when entering Standby mode.
* OB_STDBY_NoRST - No reset generated when entering in STANDBY
* OB_STDBY_RST - Reset generated when entering in STANDBY
@ -426,12 +430,15 @@ FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
* OB_RST_NoEN - Reset IO disable (PD7)
* OB_RST_EN_DT12ms - Reset IO enable (PD7) and Ignore delay time 12ms
* OB_RST_EN_DT1ms - Reset IO enable (PD7) and Ignore delay time 1ms
* OB_RST_EN_DT128ms - Reset IO enable (PD7) and Ignore delay time 128ms
* OB_RST_EN_DT128us - Reset IO enable (PD7) and Ignore delay time 128us
* OB_PowerON_Start_Mode - Selects start mode after power on.
* OB_PowerON_Start_Mode_BOOT - from Boot after power on.
* OB_PowerON_Start_Mode_USER - from User after power on.
*
* @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
* FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
*/
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY, uint16_t OB_RST)
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STDBY, uint16_t OB_RST, uint16_t OB_PowerON_Start_Mode)
{
FLASH_Status status = FLASH_COMPLETE;
@ -443,7 +450,7 @@ FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint
{
FLASH->CTLR |= CR_OPTPG_Set;
OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | (uint16_t)(OB_RST | (uint16_t)0xE0)));
OB->USER = OB_IWDG | (uint16_t)(OB_STDBY | (uint16_t)(OB_RST | (uint16_t)(OB_PowerON_Start_Mode| (uint16_t)0xC2)));
status = FLASH_WaitForLastOperation(ProgramTimeout);
if(status != FLASH_TIMEOUT)
@ -715,15 +722,15 @@ void FLASH_Unlock_Fast(void)
}
/*********************************************************************
* @fn FLASH_Unlock_Fast
* @fn FLASH_Lock_Fast
*
* @brief Unlocks the Fast Program Erase Mode.
* @brief Locks the Fast Program Erase Mode.
*
* @return none
*/
void FLASH_Lock_Fast(void)
{
FLASH->CTLR |= CR_LOCK_Set;
FLASH->CTLR |= CR_FLOCK_Set;
}
/*********************************************************************
@ -826,9 +833,234 @@ void SystemReset_StartMode(uint32_t Mode)
FLASH->BOOT_MODEKEYR = FLASH_KEY1;
FLASH->BOOT_MODEKEYR = FLASH_KEY2;
FLASH->STATR |= (1<<15);
FLASH->STATR &= ~(1<<14);
if(Mode == Start_Mode_BOOT){
FLASH->STATR |= (1<<14);
}
FLASH_Lock();
}
/*********************************************************************
* @fn ROM_ERASE
*
* @brief Select erases a specified FLASH .
*
* @param StartAddr - Erases Flash start address(StartAddr%64 == 0).
* Cnt - Erases count.
* Erase_Size - Erases size select.The returned value can be:
* Size_1KB, Size_64B.
*
* @return none.
*/
static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size)
{
do{
if(Erase_Size == Size_1KB)
{
FLASH->CTLR |= CR_PER_Set;
}
else if(Erase_Size == Size_64B)
{
FLASH->CTLR |= CR_PAGE_ER;
}
FLASH->ADDR = StartAddr;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
if(Erase_Size == Size_1KB)
{
FLASH->CTLR &= ~CR_PER_Set;
StartAddr += Size_1KB;
}
else if(Erase_Size == Size_64B)
{
FLASH->CTLR &= ~CR_PAGE_ER;
StartAddr += Size_64B;
}
}while(--Cnt);
}
/*********************************************************************
* @fn FLASH_ROM_ERASE
*
* @brief Erases a specified FLASH .
*
* @param StartAddr - Erases Flash start address(StartAddr%64 == 0).
* Length - Erases Flash start Length(Length%64 == 0).
*
* @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR,
* FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE.
*/
FLASH_Status FLASH_ROM_ERASE( uint32_t StartAddr, uint32_t Length )
{
uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0;
FLASH_Status status = FLASH_COMPLETE;
if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd))
{
return FLASH_ADR_RANGE_ERROR;
}
if((StartAddr + Length) > ValidAddrEnd)
{
return FLASH_OP_RANGE_ERROR;
}
if((StartAddr & (Size_64B-1)) || (Length & (Size_64B-1)) || (Length == 0))
{
return FLASH_ALIGN_ERROR;
}
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
/* Fast program mode unlock */
FLASH->MODEKEYR = FLASH_KEY1;
FLASH->MODEKEYR = FLASH_KEY2;
Addr0 = StartAddr;
if(Length >= Size_1KB)
{
Length0 = Size_1KB - (Addr0 & (Size_1KB - 1));
Addr1 = StartAddr + Length0;
Length1 = Length - Length0;
}
else if(Length >= Size_64B)
{
Length0 = Length;
}
/* Erase 1KB */
if(Length0 >= Size_1KB) //front
{
Length = Length0;
if(Addr0 & (Size_1KB - 1))
{
Length0 = Size_1KB - (Addr0 & (Size_1KB - 1));
}
else
{
Length0 = 0;
}
ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 10), Size_1KB);
}
if(Length1 >= Size_1KB) //back
{
StartAddr = Addr1;
Length = Length1;
if((Addr1 + Length1) & (Size_1KB - 1))
{
Addr1 = ((StartAddr + Length1) & (~(Size_1KB - 1)));
Length1 = (StartAddr + Length1) & (Size_1KB - 1);
}
else
{
Length1 = 0;
}
ROM_ERASE(StartAddr, ((Length - Length1) >> 10), Size_1KB);
}
/* Erase 64B */
if(Length0)//front
{
ROM_ERASE(Addr0, (Length0 >> 6), Size_64B);
}
if(Length1)//back
{
ROM_ERASE(Addr1, (Length1 >> 6), Size_64B);
}
FLASH->CTLR |= CR_FLOCK_Set;
FLASH->CTLR |= CR_LOCK_Set;
return status;
}
/*********************************************************************
* @fn FLASH_ROM_WRITE
*
* @brief Writes a specified FLASH .
*
* @param StartAddr - Writes Flash start address(StartAddr%64 == 0).
* Length - Writes Flash start Length(Length%64 == 0).
* pbuf - Writes Flash value buffer.
*
* @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR,
* FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE.
*/
FLASH_Status FLASH_ROM_WRITE( uint32_t StartAddr, uint32_t *pbuf, uint32_t Length )
{
uint32_t i, adr;
uint8_t size;
FLASH_Status status = FLASH_COMPLETE;
if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd))
{
return FLASH_ADR_RANGE_ERROR;
}
if((StartAddr + Length) > ValidAddrEnd)
{
return FLASH_OP_RANGE_ERROR;
}
if((StartAddr & (Size_64B-1)) || (Length & (Size_64B-1)) || (Length == 0))
{
return FLASH_ALIGN_ERROR;
}
adr = StartAddr;
i = Length >> 6;
/* Authorize the FPEC of Bank1 Access */
FLASH->KEYR = FLASH_KEY1;
FLASH->KEYR = FLASH_KEY2;
/* Fast program mode unlock */
FLASH->MODEKEYR = FLASH_KEY1;
FLASH->MODEKEYR = FLASH_KEY2;
do{
FLASH->CTLR |= CR_PAGE_PG;
FLASH->CTLR |= CR_BUF_RST;
while(FLASH->STATR & SR_BSY)
;
size = 16;
while(size)
{
*(__IO uint32_t *)(StartAddr) = *(uint32_t *)pbuf;
FLASH->CTLR |= CR_BUF_LOAD;
while(FLASH->STATR & SR_BSY)
;
StartAddr += 4;
pbuf += 1;
size -= 1;
}
FLASH->CTLR |= CR_PAGE_PG;
FLASH->ADDR = adr;
FLASH->CTLR |= CR_STRT_Set;
while(FLASH->STATR & SR_BSY)
;
FLASH->CTLR &= ~CR_PAGE_PG;
adr += 64;
}while(--i);
FLASH->CTLR |= CR_FLOCK_Set;
FLASH->CTLR |= CR_LOCK_Set;
return status;
}

63
Peripheral/src/ch32v00x_gpio.c
View file

@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the GPIO firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_gpio.h>
#include <ch32v00x_rcc.h>
@ -283,8 +285,8 @@ void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
* @param GPIO_Pin - specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* BitVal - specifies the value to be written to the selected bit.
* Bit_SetL - to clear the port pin.
* Bit_SetH - to set the port pin.
* Bit_RESET - to clear the port pin.
* Bit_SET - to set the port pin.
*
* @return none
*/
@ -346,7 +348,7 @@ void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
* @param GPIO_Remap - selects the pin to remap.
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
* GPIO_PartialRemap_I2C1 - I2C1 Partial Alternate Function mapping
* GPIO_PartialRemap_I2C1 - I2C1 Full Alternate Function mapping
* GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping
* GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping
* GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping
* GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping
@ -356,11 +358,11 @@ void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
* GPIO_Remap_PA12 - PA12 Alternate Function mapping
* GPIO_Remap_PA1_2 - PA1_2 Alternate Function mapping
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
* GPIO_Remap_LSI_CAL - LSI calibration Alternate Function mapping
* GPIO_Remap_SWJ_Disable - SDI Disabled
* GPIO_Remap_SDI_Disable - SDI Disabled
* NewState - ENABLE or DISABLE.
*
* @return none
@ -451,6 +453,55 @@ void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
AFIO->EXTICR |= ((uint32_t)(GPIO_PortSource<<(GPIO_PinSource<<1)));
}
/*********************************************************************
* @fn GPIO_IPD_Unused
*
* @brief Configure unused GPIO as input pull-up.
*
* @param none
*
* @return none
*/
void GPIO_IPD_Unused(void)
{
GPIO_InitTypeDef GPIO_InitStructure = {0};
uint32_t chip = 0;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC, ENABLE);
chip = *( uint32_t * )0x1FFFF7C4 & (~0x000000F0);
switch(chip)
{
case 0x00320500: //CH32V003A4M6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\
|GPIO_Pin_3;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
break;
}
case 0x00330500: //CH32V003J4M6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_7;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_3\
|GPIO_Pin_5|GPIO_Pin_6\
|GPIO_Pin_7;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
break;
}
default:
{
break;
}
}
}

86
Peripheral/src/ch32v00x_i2c.c
View file

@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the I2C firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_i2c.h>
#include <ch32v00x_rcc.h>
@ -538,7 +540,10 @@ void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
* the last received byte.
* I2C_NACKPosition_Current - indicates that current byte is the
* last received byte.
*
* Note-
* This function configures the same bit (POS) as I2C_PECPositionConfig()
* but is intended to be used in I2C mode while I2C_PECPositionConfig()
* is intended to used in SMBUS mode.
* @return none
*/
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
@ -711,28 +716,28 @@ void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
*
* @param I2Cx- where x can be 1 to select the I2C peripheral.
* I2C_EVENT: specifies the event to be checked.
* I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1.
* I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2.
* I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3.
* I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2.
* I2C_EVENT_SLAVE_STOP_DETECTED - EV4.
* I2C_EVENT_MASTER_MODE_SELECT - EV5.
* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6.
* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6.
* I2C_EVENT_MASTER_BYTE_RECEIVED - EV7.
* I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8.
* I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2.
* I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9.
* I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1.
* I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1.
* I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1.
* I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1.
* I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1.
* I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2.
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2.
* I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3.
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3.
* I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2.
* I2C_EVENT_SLAVE_STOP_DETECTED - EVT4.
* I2C_EVENT_MASTER_MODE_SELECT - EVT5.
* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6.
* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6.
* I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7.
* I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8.
* I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2.
* I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9.
*
* @return none
* @return ErrorStatus - READY or NoREADY.
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
{
@ -807,7 +812,7 @@ uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
* Address matched flag (Slave mode)"ENDA".
* I2C_FLAG_SB - Start bit flag (Master mode).
*
* @return none
* @return FlagStatus - SET or RESET.
*/
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
{
@ -854,7 +859,22 @@ FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
* I2C_FLAG_AF - Acknowledge failure flag.
* I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
* I2C_FLAG_BERR - Bus error flag.
*
* Note-
* - STOPF (STOP detection) is cleared by software sequence: a read operation
* to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation
* to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral).
* - ADD10 (10-bit header sent) is cleared by software sequence: a read
* operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the
* second byte of the address in DATAR register.
* - BTF (Byte Transfer Finished) is cleared by software sequence: a read
* operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a
* read/write to I2C_DATAR register (I2C_SendData()).
* - ADDR (Address sent) is cleared by software sequence: a read operation to
* I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to
* I2C_SATR2 register ((void)(I2Cx->SR2)).
* - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1
* register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR
* register (I2C_SendData()).
* @return none
*/
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
@ -920,6 +940,22 @@ ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
* I2C_IT_AF - Acknowledge failure interrupt.
* I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
* I2C_IT_BERR - Bus error interrupt.
* Note-
* - STOPF (STOP detection) is cleared by software sequence: a read operation
* to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to
* I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral).
* - ADD10 (10-bit header sent) is cleared by software sequence: a read
* operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second
* byte of the address in I2C_DATAR register.
* - BTF (Byte Transfer Finished) is cleared by software sequence: a read
* operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a
* read/write to I2C_DATAR register (I2C_SendData()).
* - ADDR (Address sent) is cleared by software sequence: a read operation to
* I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to
* I2C_STAR2 register ((void)(I2Cx->SR2)).
* - SB (Start Bit) is cleared by software sequence: a read operation to
* I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to
* I2C_DATAR register (I2C_SendData()).
*
* @return none
*/

7
Peripheral/src/ch32v00x_iwdg.c
View file

@ -2,10 +2,12 @@
* File Name : ch32v00x_iwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/25
* Description : This file provides all the IWDG firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_iwdg.h>
@ -90,6 +92,7 @@ void IWDG_ReloadCounter(void)
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
while ((RCC->RSTSCKR)|(0x2)!= SET);
}
/*********************************************************************

68
Peripheral/src/ch32v00x_misc.c
View file

@ -2,11 +2,13 @@
* File Name : ch32v00x_misc.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/25
* Description : This file provides all the miscellaneous firmware functions .
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_misc.h>
__IO uint32_t NVIC_Priority_Group = 0;
@ -18,15 +20,9 @@ __IO uint32_t NVIC_Priority_Group = 0;
*
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
* 4 bits for subpriority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 3 bits for subpriority
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
* 2 bits for subpriority
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 1 bits for subpriority
* NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
* 0 bits for subpriority
*
* @return none
*/
@ -43,58 +39,36 @@ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
*
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
* configuration information for the specified NVIC peripheral.
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 1.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* @return none
*/
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
{
uint8_t tmppre = 0;
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6);
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
#else
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6));
}
else
else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 6));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
}
else
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
}
else
{
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
}
}
else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
}
#endif
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{

8
Peripheral/src/ch32v00x_opa.c
View file

@ -4,9 +4,11 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the OPA firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
***************************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_opa.h>
@ -37,7 +39,7 @@ void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
{
uint32_t tmp = 0;
tmp = EXTEN->EXTEN_CTR;
tmp &= ~(uint32_t)(2<<17);
tmp &= ~(uint32_t)(3<<17);
tmp |= (OPA_InitStruct->PSEL << 18) | (OPA_InitStruct->NSEL << 17);
EXTEN->EXTEN_CTR = tmp;
}

20
Peripheral/src/ch32v00x_pwr.c
View file

@ -4,9 +4,11 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the PWR firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
********************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_pwr.h>
#include <ch32v00x_rcc.h>
@ -59,14 +61,14 @@ void PWR_PVDCmd(FunctionalState NewState)
* Detector(PVD).
*
* @param PWR_PVDLevel - specifies the PVD detection level
* PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
* PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
* PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
* PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
* PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
* PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
* PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
* PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
* PWR_PVDLevel_3V1 - PVD detection level set to 3.1V
* PWR_PVDLevel_3V3 - PVD detection level set to 3.3V
* PWR_PVDLevel_3V5 - PVD detection level set to 3.5V
* PWR_PVDLevel_3V7 - PVD detection level set to 3.7V
* PWR_PVDLevel_3V9 - PVD detection level set to 3.9V
* PWR_PVDLevel_4V1 - PVD detection level set to 4.1V
* PWR_PVDLevel_4V4 - PVD detection level set to 4.4V
*
* @return none
*/

45
Peripheral/src/ch32v00x_rcc.c
View file

@ -2,10 +2,12 @@
* File Name : ch32v00x_rcc.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/25
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_rcc.h>
@ -75,6 +77,8 @@ void RCC_DeInit(void)
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFFFEFFFF;
RCC->INTR = 0x009F0000;
RCC_AdjustHSICalibrationValue(0x10);
}
/*********************************************************************
@ -86,7 +90,8 @@ void RCC_DeInit(void)
* RCC_HSE_OFF - HSE oscillator OFF.
* RCC_HSE_ON - HSE oscillator ON.
* RCC_HSE_Bypass - HSE oscillator bypassed with external clock.
*
* Note-
* HSE can not be stopped if it is used directly or through the PLL as system clock.
* @return none
*/
void RCC_HSEConfig(uint32_t RCC_HSE)
@ -114,8 +119,8 @@ void RCC_HSEConfig(uint32_t RCC_HSE)
*
* @brief Waits for HSE start-up.
*
* @return SUCCESS - HSE oscillator is stable and ready to use.
* ERROR - HSE oscillator not yet ready.
* @return READY - HSE oscillator is stable and ready to use.
* NoREADY - HSE oscillator not yet ready.
*/
ErrorStatus RCC_WaitForHSEStartUp(void)
{
@ -196,13 +201,13 @@ void RCC_HSICmd(FunctionalState NewState)
*
* @return none
*/
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
void RCC_PLLConfig(uint32_t RCC_PLLSource)
{
uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_PLL_Mask;
tmpreg |= RCC_PLLSource | RCC_PLLMul;
tmpreg |= RCC_PLLSource;
RCC->CFGR0 = tmpreg;
}
@ -210,6 +215,8 @@ void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
* @fn RCC_PLLCmd
*
* @brief Enables or disables the PLL.
* Note-The PLL can not be disabled if it is used as system clock.
*
*
* @param NewState - ENABLE or DISABLE.
*
@ -242,6 +249,21 @@ void RCC_PLLCmd(FunctionalState NewState)
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
{
uint32_t tmpreg = 0;
uint8_t tmp = 0;
tmp = *( uint8_t * )CFG0_PLL_TRIM;
if(tmp != 0xFF)
{
if((RCC_SYSCLKSource == RCC_SYSCLKSource_PLLCLK) && ((RCC->CFGR0 & (1<<16)) == RCC_PLLSource_HSI_MUL2))
{
RCC_AdjustHSICalibrationValue((tmp & 0x1F));
}
else
{
RCC_AdjustHSICalibrationValue(0x10);
}
}
tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_SW_Mask;
@ -358,6 +380,8 @@ void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
* @fn RCC_LSICmd
*
* @brief Enables or disables the Internal Low Speed oscillator (LSI).
* Note-
* LSI can not be disabled if the IWDG is running.
*
* @param NewState - ENABLE or DISABLE.
*
@ -437,6 +461,7 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency;
tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
tmp = tmp >> 11;
tmp = ((tmp & 0x18) >> 3) | ((tmp & 0x7) << 2);
if((tmp & 0x13) >= 4)
{
@ -455,6 +480,8 @@ void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
* @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
* RCC_AHBPeriph_DMA1.
* RCC_AHBPeriph_SRAM.
* Note-
* SRAM clock can be disabled only during sleep mode.
* NewState: ENABLE or DISABLE.
*
* @return none
@ -677,7 +704,9 @@ FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
* @fn RCC_ClearFlag
*
* @brief Clears the RCC reset flags.
*
* Note-
* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
* @return none
*/
void RCC_ClearFlag(void)

28
Peripheral/src/ch32v00x_spi.c
View file

@ -4,9 +4,11 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the SPI firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*********************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_rcc.h>
#include <ch32v00x_spi.h>
@ -93,6 +95,7 @@ void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
/*"SPI_FirstBit_LSB" not support SPI slave mode*/
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStruct->SPI_CRCPolynomial = 7;
}
@ -422,7 +425,15 @@ FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
* - 1 in SPI mode.
* SPI_I2S_FLAG - specifies the SPI flag to clear.
* SPI_FLAG_CRCERR - CRC Error flag.
*
* Note-
* - OVR (OverRun error) flag is cleared by software sequence: a read
* operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()).
* - UDR (UnderRun error) flag is cleared by a read operation to
* SPI_STATR register (SPI_I2S_GetFlagStatus()).
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a
* write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI).
* @return FlagStatus: SET or RESET.
*/
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
@ -478,7 +489,16 @@ ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
* - 1 in SPI mode.
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
* SPI_IT_CRCERR - CRC Error interrupt.
*
* Note-
* - OVR (OverRun Error) interrupt pending bit is cleared by software
* sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData())
* followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()).
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
* operation to SPI_STATR register (SPI_I2S_GetITStatus()).
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
* a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus())
* followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable
* the SPI).
* @return none
*/
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)

38
Peripheral/src/ch32v00x_tim.c
View file

@ -2,10 +2,12 @@
* File Name : ch32v00x_tim.c
* Author : WCH
* Version : V1.0.0
* Date : 2022/08/08
* Date : 2023/12/25
* Description : This file provides all the TIM firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_rcc.h>
#include <ch32v00x_tim.h>
@ -1054,7 +1056,7 @@ void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
* @fn TIM_CCPreloadControl
*
* @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit.
* reset values (Affects also the I2Ss).
* reset values .
* @param TIMx - where x can be 1 to 2 to select the TIM peripheral.
* NewState - ENABLE or DISABLE.
*
@ -1962,13 +1964,13 @@ uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx)
}
/*********************************************************************
* @fn TIM_GetCapture2
* @fn TIM_GetCapture3
*
* @brief Gets the TIMx Input Capture 2 value.
* @brief Gets the TIMx Input Capture 3 value.
*
* @param TIMx - where x can be 1 to 2 select the TIM peripheral.
*
* @return TIMx->CH2CVR - Capture Compare 2 Register value.
* @return TIMx->CH3CVR - Capture Compare 3 Register value.
*/
uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx)
{
@ -2334,10 +2336,32 @@ static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_
}
else
{
tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP));
tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P));
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E);
}
TIMx->CHCTLR2 = tmpccmr2;
TIMx->CCER = tmpccer;
}
/*********************************************************************
* @fn TIM_IndicateCaptureLevelCmd
*
* @brief Enables or disables the TIMx capture level indication.
*
* @param TIMx - where x can be 1 to 2 select the TIM peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState)
{
if(NewState)
{
TIMx->CTLR1 |= (1<<15);
}
else{
TIMx->CTLR1 &= ~(1<<15);
}
}

62
Peripheral/src/ch32v00x_usart.c
View file

@ -4,8 +4,10 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the USART firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_rcc.h>
#include <ch32v00x_usart.h>
@ -217,7 +219,7 @@ void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
* @fn USART_Cmd
*
* @brief Enables or disables the specified USART peripheral.
* reset values (Affects also the I2Ss).
* reset values .
*
* @param USARTx - where x can be 1 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
@ -240,11 +242,10 @@ void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
* @fn USART_ITConfig
*
* @brief Enables or disables the specified USART interrupts.
* reset values (Affects also the I2Ss).
* reset values .
*
* @param USARTx - where x can be to select the USART peripheral.
* USART_IT - specifies the USART interrupt sources to be enabled or disabled.
* USART_IT_CTS - CTS change interrupt.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TXE - Transmit Data Register empty interrupt.
* USART_IT_TC - Transmission complete interrupt.
@ -261,9 +262,6 @@ void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState Ne
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
uint32_t usartxbase = 0x00;
if(USART_IT == USART_IT_CTS)
{
}
usartxbase = (uint32_t)USARTx;
usartreg = (((uint8_t)USART_IT) >> 0x05);
@ -562,7 +560,9 @@ void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
*
* @param USARTx - where x can be 1 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* Note-
* This function has to be called before calling USART_Init()
* function in order to have correct baudrate Divider value.
* @return none
*/
void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
@ -646,7 +646,6 @@ void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
*
* @param USARTx - where x can be 1 to select the USART peripheral.
* USART_FLAG - specifies the flag to check.
* USART_FLAG_CTS - CTS Change flag.
* USART_FLAG_LBD - LIN Break detection flag.
* USART_FLAG_TXE - Transmit data register empty flag.
* USART_FLAG_TC - Transmission Complete flag.
@ -663,10 +662,6 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
{
FlagStatus bitstatus = RESET;
if(USART_FLAG == USART_FLAG_CTS)
{
}
if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
@ -685,18 +680,25 @@ FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
*
* @param USARTx - where x can be 1 to select the USART peripheral.
* USART_FLAG - specifies the flag to clear.
* USART_FLAG_CTS - CTS Change flag.
* USART_FLAG_LBD - LIN Break detection flag.
* USART_FLAG_TC - Transmission Complete flag.
* USART_FLAG_RXNE - Receive data register not empty flag.
*
* Note-
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_STATR register (USART_GetFlagStatus())
* followed by a read operation to USART_DATAR register (USART_ReceiveData()).
* - RXNE flag can be also cleared by a read to the USART_DATAR register
* (USART_ReceiveData()).
* - TC flag can be also cleared by software sequence: a read operation to
* USART_STATR register (USART_GetFlagStatus()) followed by a write operation
* to USART_DATAR register (USART_SendData()).
* - TXE flag is cleared only by a write to the USART_DATAR register
* (USART_SendData()).
* @return none
*/
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
{
if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
{
}
USARTx->STATR = (uint16_t)~USART_FLAG;
}
@ -708,7 +710,6 @@ void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
*
* @param USARTx - where x can be 1 to select the USART peripheral.
* USART_IT - specifies the USART interrupt source to check.
* USART_IT_CTS - CTS change interrupt.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TXE - Tansmit Data Register empty interrupt.
* USART_IT_TC - Transmission complete interrupt.
@ -727,10 +728,6 @@ ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
ITStatus bitstatus = RESET;
if(USART_IT == USART_IT_CTS)
{
}
usartreg = (((uint8_t)USART_IT) >> 0x05);
itmask = USART_IT & IT_Mask;
itmask = (uint32_t)0x01 << itmask;
@ -771,21 +768,28 @@ ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
*
* @param USARTx - where x can be 1 to select the USART peripheral.
* USART_IT - specifies the interrupt pending bit to clear.
* USART_IT_CTS - CTS change interrupt.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TC - Transmission complete interrupt.
* USART_IT_RXNE - Receive Data register not empty interrupt.
*
* Note-
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
* error) and IDLE (Idle line detected) pending bits are cleared by
* software sequence: a read operation to USART_STATR register
* (USART_GetITStatus()) followed by a read operation to USART_DATAR register
* (USART_ReceiveData()).
* - RXNE pending bit can be also cleared by a read to the USART_DATAR register
* (USART_ReceiveData()).
* - TC pending bit can be also cleared by software sequence: a read
* operation to USART_STATR register (USART_GetITStatus()) followed by a write
* operation to USART_DATAR register (USART_SendData()).
* - TXE pending bit is cleared only by a write to the USART_DATAR register
* (USART_SendData()).
* @return none
*/
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
{
uint16_t bitpos = 0x00, itmask = 0x00;
if(USART_IT == USART_IT_CTS)
{
}
bitpos = USART_IT >> 0x08;
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
USARTx->STATR = (uint16_t)~itmask;

6
Peripheral/src/ch32v00x_wwdg.c
View file

@ -4,9 +4,11 @@
* Version : V1.0.0
* Date : 2022/08/08
* Description : This file provides all the WWDG firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
**********************************************************************************/
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <ch32v00x_rcc.h>
#include <ch32v00x_wwdg.h>

74
Startup/startup_ch32v00x.S
View file

@ -1,11 +1,13 @@
;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v00x.s
;* Author : WCH
;* Version : V1.0.0
;* Date : 2022/08/08
;* Version : V1.0.1
;* Date : 2023/12/11
;* Description : vector table for eclipse toolchain.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* SPDX-License-Identifier: Apache-2.0
;* Attention: This software (modified or not) and binary are used for
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
;*******************************************************************************/
.section .init, "ax", @progbits
@ -84,34 +86,35 @@ _start:
.weak TIM1_CC_IRQHandler
.weak TIM2_IRQHandler
NMI_Handler: 1: j 1b
HardFault_Handler: 1: j 1b
SysTick_Handler: 1: j 1b
SW_Handler: 1: j 1b
WWDG_IRQHandler: 1: j 1b
PVD_IRQHandler: 1: j 1b
FLASH_IRQHandler: 1: j 1b
RCC_IRQHandler: 1: j 1b
EXTI7_0_IRQHandler: 1: j 1b
AWU_IRQHandler: 1: j 1b
DMA1_Channel1_IRQHandler: 1: j 1b
DMA1_Channel2_IRQHandler: 1: j 1b
DMA1_Channel3_IRQHandler: 1: j 1b
DMA1_Channel4_IRQHandler: 1: j 1b
DMA1_Channel5_IRQHandler: 1: j 1b
DMA1_Channel6_IRQHandler: 1: j 1b
DMA1_Channel7_IRQHandler: 1: j 1b
ADC1_IRQHandler: 1: j 1b
I2C1_EV_IRQHandler: 1: j 1b
I2C1_ER_IRQHandler: 1: j 1b
USART1_IRQHandler: 1: j 1b
SPI1_IRQHandler: 1: j 1b
TIM1_BRK_IRQHandler: 1: j 1b
TIM1_UP_IRQHandler: 1: j 1b
TIM1_TRG_COM_IRQHandler: 1: j 1b
TIM1_CC_IRQHandler: 1: j 1b
TIM2_IRQHandler: 1: j 1b
NMI_Handler:
HardFault_Handler:
SysTick_Handler:
SW_Handler:
WWDG_IRQHandler:
PVD_IRQHandler:
FLASH_IRQHandler:
RCC_IRQHandler:
EXTI7_0_IRQHandler:
AWU_IRQHandler:
DMA1_Channel1_IRQHandler:
DMA1_Channel2_IRQHandler:
DMA1_Channel3_IRQHandler:
DMA1_Channel4_IRQHandler:
DMA1_Channel5_IRQHandler:
DMA1_Channel6_IRQHandler:
DMA1_Channel7_IRQHandler:
ADC1_IRQHandler:
I2C1_EV_IRQHandler:
I2C1_ER_IRQHandler:
USART1_IRQHandler:
SPI1_IRQHandler:
TIM1_BRK_IRQHandler:
TIM1_UP_IRQHandler:
TIM1_TRG_COM_IRQHandler:
TIM1_CC_IRQHandler:
TIM2_IRQHandler:
1:
j 1b
.section .text.handle_reset, "ax", @progbits
.weak handle_reset
@ -136,7 +139,7 @@ handle_reset:
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* clear bss section */
/* Clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, 2f
@ -145,12 +148,13 @@ handle_reset:
addi a0, a0, 4
bltu a0, a1, 1b
2:
li t0, 0x80
/* Enable global interrupt and configure privileged mode */
li t0, 0x1880
csrw mstatus, t0
/* Enable interrupt nesting and hardware stack */
li t0, 0x3
csrw 0x804, t0
/* Configure the interrupt vector table recognition mode and entry address mode */
la t0, _start
ori t0, t0, 3
csrw mtvec, t0

82
User/main.c
View file

@ -7,19 +7,6 @@
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* SPDX-License-Identifier: Apache-2.0
*******************************************************************************/
/*
*@Note
轮询收发模式例程：
Master：USART1_Tx(PD5)、USART1_Rx(PD6)。
本例程演示 USART1 收到CH341发送的数据取反发出（波特率 115200）。
注：
硬件连线：PD5 —— Rx
PD6 —— Tx
*/
#include "debug.h"
@ -27,40 +14,25 @@
/* Global Variable */
vu8 val;
/*********************************************************************
* @fn USARTx_CFG
* @fn GPIO_Toggle_INIT
*
* @brief Initializes the USART2 & USART3 peripheral.
* @brief Initializes GPIOD.4
*
* @return none
*/
void USARTx_CFG(void)
{
void GPIO_LED_Init(void) {
GPIO_InitTypeDef GPIO_InitStructure = {0};
USART_InitTypeDef USART_InitStructure = {0};
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
/* USART1 TX-->D.5 RX-->D.6 */
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_StructInit(&GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_Init(GPIOD, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
GPIO_Init(GPIOD, &GPIO_InitStructure);
USART_InitStructure.USART_BaudRate = 115200;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
USART_Init(USART1, &USART_InitStructure);
USART_Cmd(USART1, ENABLE);
}
/*********************************************************************
@ -70,27 +42,27 @@ void USARTx_CFG(void)
*
* @return none
*/
int main(void)
{
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
int main(void) {
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
SystemCoreClockUpdate();
Delay_Init();
#if (SDI_PRINT == SDI_PR_OPEN)
SDI_Printf_Enable();
#else
USART_Printf_Init(115200);
printf("SystemClk:%d\r\n",SystemCoreClock);
#endif
printf("SystemClk: %ld\r\n", SystemCoreClock);
printf("DeviceID: %08lx\r\n", DBGMCU_GetDEVID());
printf("ChipID: %08lx\r\n", DBGMCU_GetCHIPID());
USARTx_CFG();
GPIO_LED_Init();
while(1)
{
while(USART_GetFlagStatus(USART1, USART_FLAG_RXNE) == RESET)
{
/* waiting for receiving finish */
}
val = (USART_ReceiveData(USART1));
USART_SendData(USART1, ~val);
while(USART_GetFlagStatus(USART1, USART_FLAG_TXE) == RESET)
{
/* waiting for sending finish */
}
while(1) {
Delay_Ms(1000);
printf("On\r\n");
GPIO_WriteBit(GPIOD, GPIO_Pin_4, Bit_SET);
Delay_Ms(1000);
printf("Off\r\n");
GPIO_WriteBit(GPIOD, GPIO_Pin_4, Bit_RESET);
}
}

4
User/system_ch32v00x.c
View file

@ -17,10 +17,10 @@
//#define SYSCLK_FREQ_8MHz_HSI 8000000
//#define SYSCLK_FREQ_24MHZ_HSI HSI_VALUE
//#define SYSCLK_FREQ_48MHZ_HSI 48000000
#define SYSCLK_FREQ_48MHZ_HSI 48000000
//#define SYSCLK_FREQ_8MHz_HSE 8000000
//#define SYSCLK_FREQ_24MHz_HSE HSE_VALUE
#define SYSCLK_FREQ_48MHz_HSE 48000000
//#define SYSCLK_FREQ_48MHz_HSE 48000000
/* Clock Definitions */
#ifdef SYSCLK_FREQ_8MHz_HSI