154 lines
7.2 KiB
C
154 lines
7.2 KiB
C
/********************************** (C) COPYRIGHT *******************************
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* File Name : ch32v00x_rcc.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2022/08/08
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* Description : This file provides all the RCC firmware functions.
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#ifndef __CH32V00x_RCC_H
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#define __CH32V00x_RCC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <ch32v00x.h>
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/* RCC_Exported_Types */
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typedef struct
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{
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uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
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uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
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uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
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uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
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uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
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} RCC_ClocksTypeDef;
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/* HSE_configuration */
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#define RCC_HSE_OFF ((uint32_t)0x00000000)
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#define RCC_HSE_ON ((uint32_t)0x00010000)
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#define RCC_HSE_Bypass ((uint32_t)0x00040000)
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/* PLL_entry_clock_source */
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#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
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#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
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/* System_clock_source */
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#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
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#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
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#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
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/* AHB_clock_source */
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#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
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#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
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#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020)
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#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030)
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#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040)
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#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050)
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#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060)
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#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070)
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#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
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#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0)
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#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0)
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#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
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#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
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/* RCC_Interrupt_source */
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#define RCC_IT_LSIRDY ((uint8_t)0x01)
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#define RCC_IT_HSIRDY ((uint8_t)0x04)
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#define RCC_IT_HSERDY ((uint8_t)0x08)
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#define RCC_IT_PLLRDY ((uint8_t)0x10)
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#define RCC_IT_CSS ((uint8_t)0x80)
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/* ADC_clock_source */
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#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
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#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
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#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
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#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
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#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000)
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#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000)
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#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800)
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#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800)
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#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000)
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#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000)
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#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
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#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
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/* AHB_peripheral */
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#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
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#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
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/* APB2_peripheral */
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#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
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#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
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#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
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#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
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#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
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#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
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#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
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#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
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/* APB1_peripheral */
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#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
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#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
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#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
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#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
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/* Clock_source_to_output_on_MCO_pin */
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#define RCC_MCO_NoClock ((uint8_t)0x00)
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#define RCC_MCO_SYSCLK ((uint8_t)0x04)
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#define RCC_MCO_HSI ((uint8_t)0x05)
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#define RCC_MCO_HSE ((uint8_t)0x06)
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#define RCC_MCO_PLLCLK ((uint8_t)0x07)
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/* RCC_Flag */
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#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
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#define RCC_FLAG_HSERDY ((uint8_t)0x31)
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#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
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#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
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#define RCC_FLAG_PINRST ((uint8_t)0x7A)
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#define RCC_FLAG_PORRST ((uint8_t)0x7B)
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#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
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#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
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#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
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#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
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/* SysTick_clock_source */
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#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
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#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
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void RCC_DeInit(void);
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void RCC_HSEConfig(uint32_t RCC_HSE);
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ErrorStatus RCC_WaitForHSEStartUp(void);
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void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
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void RCC_HSICmd(FunctionalState NewState);
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void RCC_PLLConfig(uint32_t RCC_PLLSource);
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void RCC_PLLCmd(FunctionalState NewState);
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void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
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uint8_t RCC_GetSYSCLKSource(void);
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void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
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void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
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void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
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void RCC_LSICmd(FunctionalState NewState);
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void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
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void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
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void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
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void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
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void RCC_MCOConfig(uint8_t RCC_MCO);
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FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
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void RCC_ClearFlag(void);
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ITStatus RCC_GetITStatus(uint8_t RCC_IT);
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void RCC_ClearITPendingBit(uint8_t RCC_IT);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CH32V00x_RCC_H */
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