Initial commit
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684eb7c858
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116
.gitignore
vendored
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116
.gitignore
vendored
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@ -0,0 +1,116 @@
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|||
# Created by https://www.toptal.com/developers/gitignore/api/cmake,c++,c,vim
|
||||
# Edit at https://www.toptal.com/developers/gitignore?templates=cmake,c++,c,vim
|
||||
|
||||
### C ###
|
||||
# Prerequisites
|
||||
*.d
|
||||
|
||||
# Object files
|
||||
*.o
|
||||
*.ko
|
||||
*.obj
|
||||
*.elf
|
||||
|
||||
# Linker output
|
||||
*.ilk
|
||||
*.map
|
||||
*.exp
|
||||
|
||||
# Precompiled Headers
|
||||
*.gch
|
||||
*.pch
|
||||
|
||||
# Libraries
|
||||
*.lib
|
||||
*.a
|
||||
*.la
|
||||
*.lo
|
||||
|
||||
# Shared objects (inc. Windows DLLs)
|
||||
*.dll
|
||||
*.so
|
||||
*.so.*
|
||||
*.dylib
|
||||
|
||||
# Executables
|
||||
*.exe
|
||||
*.out
|
||||
*.app
|
||||
*.i*86
|
||||
*.x86_64
|
||||
*.hex
|
||||
|
||||
# Debug files
|
||||
*.dSYM/
|
||||
*.su
|
||||
*.idb
|
||||
*.pdb
|
||||
|
||||
# Kernel Module Compile Results
|
||||
*.mod*
|
||||
*.cmd
|
||||
.tmp_versions/
|
||||
modules.order
|
||||
Module.symvers
|
||||
Mkfile.old
|
||||
dkms.conf
|
||||
|
||||
### C++ ###
|
||||
# Prerequisites
|
||||
|
||||
# Compiled Object files
|
||||
*.slo
|
||||
|
||||
# Precompiled Headers
|
||||
|
||||
# Compiled Dynamic libraries
|
||||
|
||||
# Fortran module files
|
||||
*.mod
|
||||
*.smod
|
||||
|
||||
# Compiled Static libraries
|
||||
*.lai
|
||||
|
||||
# Executables
|
||||
|
||||
### CMake ###
|
||||
CMakeLists.txt.user
|
||||
CMakeCache.txt
|
||||
CMakeFiles
|
||||
CMakeScripts
|
||||
Testing
|
||||
Makefile
|
||||
cmake_install.cmake
|
||||
install_manifest.txt
|
||||
compile_commands.json
|
||||
CTestTestfile.cmake
|
||||
_deps
|
||||
|
||||
### CMake Patch ###
|
||||
# External projects
|
||||
*-prefix/
|
||||
|
||||
### Vim ###
|
||||
# Swap
|
||||
[._]*.s[a-v][a-z]
|
||||
!*.svg # comment out if you don't need vector files
|
||||
[._]*.sw[a-p]
|
||||
[._]s[a-rt-v][a-z]
|
||||
[._]ss[a-gi-z]
|
||||
[._]sw[a-p]
|
||||
|
||||
# Session
|
||||
Session.vim
|
||||
Sessionx.vim
|
||||
|
||||
# Temporary
|
||||
.netrwhist
|
||||
*~
|
||||
# Auto-generated tag files
|
||||
tags
|
||||
# Persistent undo
|
||||
[._]*.un~
|
||||
|
||||
# End of https://www.toptal.com/developers/gitignore/api/cmake,c++,c,vim
|
||||
obj
|
||||
39
CMakeLists.txt
Normal file
39
CMakeLists.txt
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
cmake_minimum_required(VERSION 3.10)
|
||||
project(blink)
|
||||
|
||||
# set(CMAKE_VERBOSE_MAKEFILE ON)
|
||||
set(CMAKE_C_COMPILER riscv-none-elf-gcc)
|
||||
set(CMAKE_CXX_COMPILER riscv-none-elf-gcc)
|
||||
set(CMAKE_OBJCOPY riscv-none-elf-objcopy)
|
||||
set(CMAKE_SIZE riscv-none-elf-size)
|
||||
|
||||
set_property(SOURCE Startup/startup_ch32x035.S PROPERTY LANGUAGE C)
|
||||
|
||||
set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
|
||||
|
||||
set(CMAKE_CXX_STANDARD 17)
|
||||
set(CMAKE_CXX_STANDARD_REQUIRED True)
|
||||
|
||||
include_directories(Debug)
|
||||
include_directories(Core)
|
||||
include_directories(User)
|
||||
include_directories(Peripheral/inc)
|
||||
|
||||
add_definitions(-finline-functions-called-once -g)
|
||||
|
||||
add_definitions(-Wall -Wextra -march=rv32imac_zicsr_zifencei -mabi=ilp32 -msmall-data-limit=0 -msave-restore -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -mcmodel=medany)
|
||||
|
||||
file(GLOB SOURCES "Debug/*.c" "Core/*.c" "User/*.c" "Peripheral/src/*.c" "Startup/*.S")
|
||||
|
||||
add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}.hex
|
||||
WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
|
||||
COMMAND ${CMAKE_OBJCOPY}
|
||||
ARGS -O ihex ${CMAKE_PROJECT_NAME}.elf ${CMAKE_PROJECT_NAME}.hex)
|
||||
add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${CMAKE_PROJECT_NAME}.siz
|
||||
WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
|
||||
COMMAND ${CMAKE_SIZE}
|
||||
ARGS --format=berkeley ${CMAKE_PROJECT_NAME}.elf)
|
||||
|
||||
add_executable(${CMAKE_PROJECT_NAME}.elf ${SOURCES})
|
||||
|
||||
target_link_options(${CMAKE_PROJECT_NAME}.elf PRIVATE -T ${CMAKE_SOURCE_DIR}/Ld/Link.ld -Os -march=rv32imac_zicsr_zifencei -mabi=ilp32 -nostartfiles -Xlinker -gc-sections -static --specs=nano.specs --specs=nosys.specs -mcmodel=medany)
|
||||
307
Core/core_riscv.c
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307
Core/core_riscv.c
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|
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|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2023/11/11
|
||||
* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32X035
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/* define compiler specific symbols */
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /* asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /* inline keyword for ARM Compiler */
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /* asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /* asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /* inline keyword for GNU Compiler */
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /* asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /* inline keyword for TASKING Compiler */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSTATUS
|
||||
*
|
||||
* @brief Return the Machine Status Register
|
||||
*
|
||||
* @return mstatus value
|
||||
*/
|
||||
uint32_t __get_MSTATUS(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSTATUS
|
||||
*
|
||||
* @brief Set the Machine Status Register
|
||||
*
|
||||
* @param value - set mstatus value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSTATUS(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MISA
|
||||
*
|
||||
* @brief Return the Machine ISA Register
|
||||
*
|
||||
* @return misa value
|
||||
*/
|
||||
uint32_t __get_MISA(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MISA
|
||||
*
|
||||
* @brief Set the Machine ISA Register
|
||||
*
|
||||
* @param value - set misa value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MISA(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("csrw misa, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MTVEC
|
||||
*
|
||||
* @brief Return the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @return mtvec value
|
||||
*/
|
||||
uint32_t __get_MTVEC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MTVEC
|
||||
*
|
||||
* @brief Set the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @param value - set mtvec value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MTVEC(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSCRATCH
|
||||
*
|
||||
* @brief Return the Machine Seratch Register
|
||||
*
|
||||
* @return mscratch value
|
||||
*/
|
||||
uint32_t __get_MSCRATCH(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSCRATCH
|
||||
*
|
||||
* @brief Set the Machine Seratch Register
|
||||
*
|
||||
* @param value - set mscratch value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSCRATCH(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MEPC
|
||||
*
|
||||
* @brief Return the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
uint32_t __get_MEPC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
void __set_MEPC(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("csrw mepc, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MCAUSE
|
||||
*
|
||||
* @brief Return the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
uint32_t __get_MCAUSE(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
void __set_MCAUSE(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("csrw mcause, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MTVAL
|
||||
*
|
||||
* @brief Return the Machine Trap Value Register
|
||||
*
|
||||
* @return mtval value
|
||||
*/
|
||||
uint32_t __get_MTVAL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MTVAL
|
||||
*
|
||||
* @brief Set the Machine Trap Value Register
|
||||
*
|
||||
* @return mtval value
|
||||
*/
|
||||
void __set_MTVAL(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("csrw mtval, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MVENDORID
|
||||
*
|
||||
* @brief Return Vendor ID Register
|
||||
*
|
||||
* @return mvendorid value
|
||||
*/
|
||||
uint32_t __get_MVENDORID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MARCHID
|
||||
*
|
||||
* @brief Return Machine Architecture ID Register
|
||||
*
|
||||
* @return marchid value
|
||||
*/
|
||||
uint32_t __get_MARCHID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MIMPID
|
||||
*
|
||||
* @brief Return Machine Implementation ID Register
|
||||
*
|
||||
* @return mimpid value
|
||||
*/
|
||||
uint32_t __get_MIMPID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MHARTID
|
||||
*
|
||||
* @brief Return Hart ID Register
|
||||
*
|
||||
* @return mhartid value
|
||||
*/
|
||||
uint32_t __get_MHARTID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_SP
|
||||
*
|
||||
* @brief Return SP Register
|
||||
*
|
||||
* @return SP value
|
||||
*/
|
||||
uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ( "mv %0," "sp" : "=r"(result) : );
|
||||
return (result);
|
||||
}
|
||||
|
||||
584
Core/core_riscv.h
Normal file
584
Core/core_riscv.h
Normal file
|
|
@ -0,0 +1,584 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2023/11/11
|
||||
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32X035
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CORE_RISCV_H__
|
||||
#define __CORE_RISCV_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* IO definitions */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /* defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /* defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /* defines 'write only' permissions */
|
||||
#define __IO volatile /* defines 'read / write' permissions */
|
||||
|
||||
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||
typedef __I uint64_t vuc64; /* Read Only */
|
||||
typedef __I uint32_t vuc32; /* Read Only */
|
||||
typedef __I uint16_t vuc16; /* Read Only */
|
||||
typedef __I uint8_t vuc8; /* Read Only */
|
||||
|
||||
typedef const uint64_t uc64; /* Read Only */
|
||||
typedef const uint32_t uc32; /* Read Only */
|
||||
typedef const uint16_t uc16; /* Read Only */
|
||||
typedef const uint8_t uc8; /* Read Only */
|
||||
|
||||
typedef __I int64_t vsc64; /* Read Only */
|
||||
typedef __I int32_t vsc32; /* Read Only */
|
||||
typedef __I int16_t vsc16; /* Read Only */
|
||||
typedef __I int8_t vsc8; /* Read Only */
|
||||
|
||||
typedef const int64_t sc64; /* Read Only */
|
||||
typedef const int32_t sc32; /* Read Only */
|
||||
typedef const int16_t sc16; /* Read Only */
|
||||
typedef const int8_t sc8; /* Read Only */
|
||||
|
||||
typedef __IO uint64_t vu64;
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef uint64_t u64;
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef __IO int64_t vs64;
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef int64_t s64;
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
|
||||
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
#define RV_STATIC_INLINE static inline
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
__IO uint32_t RESERVED;
|
||||
__IO uint32_t CFGR;
|
||||
__I uint32_t GISR;
|
||||
__IO uint8_t VTFIDR[4];
|
||||
uint8_t RESERVED0[12];
|
||||
__IO uint32_t VTFADDR[4];
|
||||
uint8_t RESERVED1[0x90];
|
||||
__O uint32_t IENR[8];
|
||||
uint8_t RESERVED2[0x60];
|
||||
__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
|
||||
__IO uint32_t SCTLR;
|
||||
}PFIC_Type;
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTLR;
|
||||
__IO uint32_t SR;
|
||||
__IO uint64_t CNT;
|
||||
__IO uint64_t CMP;
|
||||
}SysTick_Type;
|
||||
|
||||
|
||||
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __enable_irq
|
||||
*
|
||||
* @brief Enable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
|
||||
{
|
||||
__asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __disable_irq
|
||||
*
|
||||
* @brief Disable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
|
||||
{
|
||||
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __NOP
|
||||
*
|
||||
* @brief nop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
|
||||
{
|
||||
__asm volatile ("nop");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_EnableIRQ
|
||||
*
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_DisableIRQ
|
||||
*
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetStatusIRQ
|
||||
*
|
||||
* @brief Get Interrupt Enable State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetPendingIRQ
|
||||
*
|
||||
* @brief Get Interrupt Pending State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPendingIRQ
|
||||
*
|
||||
* @brief Set Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_ClearPendingIRQ
|
||||
*
|
||||
* @brief Clear Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetActive
|
||||
*
|
||||
* @brief Get Interrupt Active State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Active
|
||||
* 0 - Interrupt No Active
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPriority
|
||||
*
|
||||
* @brief Set Interrupt Priority
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
* interrupt nesting enable(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||
* priority - bit[7] - Preemption Priority
|
||||
* bit[6:4] - Sub priority
|
||||
* bit[3:0] - Reserve
|
||||
* interrupt nesting disable(CSR-0x804 bit1 = 0 bit[3:2] = 0)
|
||||
* priority - bit[7:4] - Sub priority
|
||||
* bit[3:0] - Reserve
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFI
|
||||
*
|
||||
* @brief Wait for Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _SEV
|
||||
*
|
||||
* @brief Set Event
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->SCTLR;
|
||||
NVIC->SCTLR |= (1<<3)|(1<<5);
|
||||
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
|
||||
{
|
||||
NVIC->SCTLR |= (1<<3);
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
_SEV();
|
||||
_WFE();
|
||||
_WFE();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetVTFIRQ
|
||||
*
|
||||
* @brief Set VTF Interrupt
|
||||
*
|
||||
* @param addr - VTF interrupt service function base address.
|
||||
* IRQn - Interrupt Numbers
|
||||
* num - VTF Interrupt Numbers
|
||||
* NewState - DISABLE or ENABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
|
||||
{
|
||||
if(num > 3) return ;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SystemReset
|
||||
*
|
||||
* @brief Initiate a system reset request
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOADD_W
|
||||
*
|
||||
* @brief Atomic Add with 32bit value
|
||||
* Atomically ADD 32bit value with value in memory using amoadd.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ADDed
|
||||
*
|
||||
* @return return memory value + add value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoadd.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOAND_W
|
||||
*
|
||||
* @brief Atomic And with 32bit value
|
||||
* Atomically AND 32bit value with value in memory using amoand.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ANDed
|
||||
*
|
||||
* @return return memory value & and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoand.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAX_W
|
||||
*
|
||||
* @brief Atomic signed MAX with 32bit value
|
||||
* Atomically signed max compare 32bit value with value in memory using amomax.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the bigger value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amomax.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAXU_W
|
||||
*
|
||||
* @brief Atomic unsigned MAX with 32bit value
|
||||
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the bigger value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amomaxu.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMIN_W
|
||||
*
|
||||
* @brief Atomic signed MIN with 32bit value
|
||||
* Atomically signed min compare 32bit value with value in memory using amomin.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amomin.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMINU_W
|
||||
*
|
||||
* @brief Atomic unsigned MIN with 32bit value
|
||||
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amominu.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOOR_W
|
||||
*
|
||||
* @brief Atomic OR with 32bit value
|
||||
* Atomically OR 32bit value with value in memory using amoor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ORed
|
||||
*
|
||||
* @return return memory value | and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoor.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOSWAP_W
|
||||
*
|
||||
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* newval - New value to be stored into the address
|
||||
*
|
||||
* @return return the original value in memory
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amoswap.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOXOR_W
|
||||
*
|
||||
* @brief Atomic XOR with 32bit value
|
||||
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be XORed
|
||||
*
|
||||
* @return return memory value ^ and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoxor.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
249
Debug/debug.c
Normal file
249
Debug/debug.c
Normal file
|
|
@ -0,0 +1,249 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : debug.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for UART
|
||||
* Printf , Delay functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "debug.h"
|
||||
|
||||
static uint8_t p_us = 0;
|
||||
static uint16_t p_ms = 0;
|
||||
|
||||
#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380)
|
||||
#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Init
|
||||
*
|
||||
* @brief Initializes Delay Funcation.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void Delay_Init(void)
|
||||
{
|
||||
p_us = SystemCoreClock / 8000000;
|
||||
p_ms = (uint16_t)p_us * 1000;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Us
|
||||
*
|
||||
* @brief Microsecond Delay Time.
|
||||
*
|
||||
* @param n - Microsecond number.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Delay_Us(uint32_t n)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
SysTick->SR &= ~(1 << 0);
|
||||
i = (uint32_t)n * p_us;
|
||||
|
||||
SysTick->CMP = i;
|
||||
SysTick->CTLR |= (1 << 4);
|
||||
SysTick->CTLR |= (1 << 5) | (1 << 0);
|
||||
|
||||
while((SysTick->SR & (1 << 0)) != (1 << 0));
|
||||
SysTick->CTLR &= ~(1 << 0);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn Delay_Ms
|
||||
*
|
||||
* @brief Millisecond Delay Time.
|
||||
*
|
||||
* @param n - Millisecond number.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void Delay_Ms(uint32_t n)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
SysTick->SR &= ~(1 << 0);
|
||||
i = (uint32_t)n * p_ms;
|
||||
|
||||
SysTick->CMP = i;
|
||||
SysTick->CTLR |= (1 << 4);
|
||||
SysTick->CTLR |= (1 << 5) | (1 << 0);
|
||||
|
||||
while((SysTick->SR & (1 << 0)) != (1 << 0));
|
||||
SysTick->CTLR &= ~(1 << 0);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Printf_Init
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral.
|
||||
*
|
||||
* @param baudrate - USART communication baud rate.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void USART_Printf_Init(uint32_t baudrate)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
|
||||
#if(DEBUG == DEBUG_UART1)
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOB, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
#elif(DEBUG == DEBUG_UART2)
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
#elif(DEBUG == DEBUG_UART3)
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
|
||||
#endif
|
||||
|
||||
USART_InitStructure.USART_BaudRate = baudrate;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Tx;
|
||||
|
||||
#if(DEBUG == DEBUG_UART1)
|
||||
USART_Init(USART1, &USART_InitStructure);
|
||||
USART_Cmd(USART1, ENABLE);
|
||||
|
||||
#elif(DEBUG == DEBUG_UART2)
|
||||
USART_Init(USART2, &USART_InitStructure);
|
||||
USART_Cmd(USART2, ENABLE);
|
||||
|
||||
#elif(DEBUG == DEBUG_UART3)
|
||||
USART_Init(USART3, &USART_InitStructure);
|
||||
USART_Cmd(USART3, ENABLE);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SDI_Printf_Enable
|
||||
*
|
||||
* @brief Initializes the SDI printf Function.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void SDI_Printf_Enable(void)
|
||||
{
|
||||
*(DEBUG_DATA0_ADDRESS) = 0;
|
||||
Delay_Init();
|
||||
Delay_Ms(1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _write
|
||||
*
|
||||
* @brief Support Printf Function
|
||||
*
|
||||
* @param *buf - UART send Data.
|
||||
* size - Data length
|
||||
*
|
||||
* @return size - Data length
|
||||
*/
|
||||
__attribute__((used))
|
||||
int _write(int fd, char *buf, int size)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
#if (SDI_PRINT == SDI_PR_OPEN)
|
||||
int writeSize = size;
|
||||
|
||||
do
|
||||
{
|
||||
|
||||
/**
|
||||
* data0 data1 共8个字节
|
||||
* data0最低位的字节存放长度，最大为 7
|
||||
*
|
||||
*/
|
||||
|
||||
while( (*(DEBUG_DATA0_ADDRESS) != 0u))
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
if(writeSize>7)
|
||||
{
|
||||
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||
|
||||
i += 7;
|
||||
writeSize -= 7;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||
|
||||
writeSize = 0;
|
||||
}
|
||||
|
||||
} while (writeSize);
|
||||
|
||||
|
||||
#else
|
||||
for(i = 0; i < size; i++){
|
||||
#if(DEBUG == DEBUG_UART1)
|
||||
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
|
||||
USART_SendData(USART1, *buf++);
|
||||
#elif(DEBUG == DEBUG_UART2)
|
||||
while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
|
||||
USART_SendData(USART2, *buf++);
|
||||
#elif(DEBUG == DEBUG_UART3)
|
||||
while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
|
||||
USART_SendData(USART3, *buf++);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
return size;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _sbrk
|
||||
*
|
||||
* @brief Change the spatial position of data segment.
|
||||
*
|
||||
* @return size - Data length
|
||||
*/
|
||||
__attribute__((used))
|
||||
void *_sbrk(ptrdiff_t incr)
|
||||
{
|
||||
extern char _end[];
|
||||
extern char _heap_end[];
|
||||
static char *curbrk = _end;
|
||||
|
||||
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
|
||||
return NULL - 1;
|
||||
|
||||
curbrk += incr;
|
||||
return curbrk - incr;
|
||||
}
|
||||
57
Debug/debug.h
Normal file
57
Debug/debug.h
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : debug.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for UART
|
||||
* Printf , Delay functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __DEBUG_H
|
||||
#define __DEBUG_H
|
||||
|
||||
#include "stdio.h"
|
||||
#include "ch32x035.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* UART Printf Definition */
|
||||
#define DEBUG_UART1 1
|
||||
#define DEBUG_UART2 2
|
||||
#define DEBUG_UART3 3
|
||||
|
||||
/* DEBUG UATR Definition */
|
||||
#ifndef DEBUG
|
||||
#define DEBUG DEBUG_UART1
|
||||
#endif
|
||||
|
||||
/* SDI Printf Definition */
|
||||
#define SDI_PR_CLOSE 0
|
||||
#define SDI_PR_OPEN 1
|
||||
|
||||
#ifndef SDI_PRINT
|
||||
#define SDI_PRINT SDI_PR_CLOSE
|
||||
#endif
|
||||
|
||||
void Delay_Init(void);
|
||||
void Delay_Us(uint32_t n);
|
||||
void Delay_Ms(uint32_t n);
|
||||
void USART_Printf_Init(uint32_t baudrate);
|
||||
void SDI_Printf_Enable(void);
|
||||
|
||||
#if(DEBUG)
|
||||
#define PRINT(format, ...) printf(format, ##__VA_ARGS__)
|
||||
#else
|
||||
#define PRINT(X...)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1
Ld/Link.ld
Normal file
1
Ld/Link.ld
Normal file
|
|
@ -0,0 +1 @@
|
|||
ENTRY( _start )
__stack_size = 2048;
PROVIDE( _stack_size = __stack_size );
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 62K
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
}
SECTIONS
{
.init :
{
_sinit = .;
. = ALIGN(4);
KEEP(*(SORT_NONE(.init)))
. = ALIGN(4);
_einit = .;
} >FLASH AT>FLASH
.vector :
{
*(.vector);
. = ALIGN(64);
} >FLASH AT>FLASH
.text :
{
. = ALIGN(4);
*(.text)
*(.text.*)
*(.rodata)
*(.rodata*)
*(.gnu.linkonce.t.*)
. = ALIGN(4);
} >FLASH AT>FLASH
.fini :
{
KEEP(*(SORT_NONE(.fini)))
. = ALIGN(4);
} >FLASH AT>FLASH
PROVIDE( _etext = . );
PROVIDE( _eitcm = . );
.preinit_array :
{
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP (*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
} >FLASH AT>FLASH
.init_array :
{
PROVIDE_HIDDEN (__init_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
PROVIDE_HIDDEN (__init_array_end = .);
} >FLASH AT>FLASH
.fini_array :
{
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
PROVIDE_HIDDEN (__fini_array_end = .);
} >FLASH AT>FLASH
.ctors :
{
/* gcc uses crtbegin.o to find the start of
the constructors, so we make sure it is
first. Because this is a wildcard, it
doesn't matter if the user does not
actually link against crtbegin.o; the
linker won't look for a file to match a
wildcard. The wildcard also means that it
doesn't matter which directory crtbegin.o
is in. */
KEEP (*crtbegin.o(.ctors))
KEEP (*crtbegin?.o(.ctors))
/* We don't want to include the .ctor section from
the crtend.o file until after the sorted ctors.
The .ctor section from the crtend file contains the
end of ctors marker and it must be last */
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
} >FLASH AT>FLASH
.dtors :
{
KEEP (*crtbegin.o(.dtors))
KEEP (*crtbegin?.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
} >FLASH AT>FLASH
.dalign :
{
. = ALIGN(4);
PROVIDE(_data_vma = .);
} >RAM AT>FLASH
.dlalign :
{
. = ALIGN(4);
PROVIDE(_data_lma = .);
} >FLASH AT>FLASH
.data :
{
*(.gnu.linkonce.r.*)
*(.data .data.*)
*(.gnu.linkonce.d.*)
. = ALIGN(8);
PROVIDE( __global_pointer$ = . + 0x800 );
*(.sdata .sdata.*)
*(.sdata2.*)
*(.gnu.linkonce.s.*)
. = ALIGN(8);
*(.srodata.cst16)
*(.srodata.cst8)
*(.srodata.cst4)
*(.srodata.cst2)
*(.srodata .srodata.*)
. = ALIGN(4);
PROVIDE( _edata = .);
} >RAM AT>FLASH
.bss :
{
. = ALIGN(4);
PROVIDE( _sbss = .);
*(.sbss*)
*(.gnu.linkonce.sb.*)
*(.bss*)
*(.gnu.linkonce.b.*)
*(COMMON*)
. = ALIGN(4);
PROVIDE( _ebss = .);
} >RAM AT>FLASH
PROVIDE( _end = _ebss);
PROVIDE( end = . );
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
{
PROVIDE( _heap_end = . );
. = ALIGN(4);
PROVIDE(_susrstack = . );
. = . + __stack_size;
PROVIDE( _eusrstack = .);
} >RAM
}
|
||||
266
Peripheral/inc/PIOC_SFR.h
Normal file
266
Peripheral/inc/PIOC_SFR.h
Normal file
|
|
@ -0,0 +1,266 @@
|
|||
/* Define for PIOC */
|
||||
/* Website: http://wch.cn */
|
||||
/* Email: tech@wch.cn */
|
||||
/* Author: W.ch 2022.08 */
|
||||
/* V1.0 SpecialFunctionRegister */
|
||||
|
||||
// __PIOC_SFR_H__
|
||||
|
||||
#ifndef __PIOC_SFR_H__
|
||||
#define __PIOC_SFR_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// Register Bit Attribute / Bit Access Type
|
||||
// RO: Read Only (internal change)
|
||||
// RW: Read / Write
|
||||
// Attribute: master/PIOC
|
||||
|
||||
/* Register name rule:
|
||||
R32_* for 32 bits register (UINT32,ULONG)
|
||||
R16_* for 16 bits register (UINT16,USHORT)
|
||||
R8_* for 8 bits register (UINT8,UCHAR)
|
||||
RB_* for bit or bit mask of 8 bit register */
|
||||
|
||||
/* ********************************************************************************************************************* */
|
||||
|
||||
#define PIOC_SRAM_BASE (SRAM_BASE+0x4000) // PIOC code RAM base address
|
||||
|
||||
#define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address
|
||||
|
||||
#define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR
|
||||
|
||||
#define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address
|
||||
|
||||
#define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count
|
||||
|
||||
#define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit
|
||||
#define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag
|
||||
#define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag
|
||||
#define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset
|
||||
#define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset
|
||||
#define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM
|
||||
#define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2
|
||||
#define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1
|
||||
#define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0
|
||||
|
||||
#define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value
|
||||
|
||||
|
||||
#define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config
|
||||
|
||||
#define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle
|
||||
#define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output
|
||||
#define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1
|
||||
|
||||
#define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2
|
||||
|
||||
#define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode
|
||||
//#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3
|
||||
//#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2
|
||||
//#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1
|
||||
//#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0
|
||||
//#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable
|
||||
//#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable
|
||||
#define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction
|
||||
#define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction
|
||||
|
||||
#define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output
|
||||
#define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input
|
||||
#define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received
|
||||
#define RB_PORT_IN1 0x20 // RO/RO, IO1 port input
|
||||
#define RB_PORT_IN0 0x10 // RO/RO, IO0 port input
|
||||
#define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input
|
||||
#define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input
|
||||
#define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output
|
||||
#define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output
|
||||
|
||||
|
||||
#define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control
|
||||
|
||||
#define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config
|
||||
#define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect)
|
||||
#define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD
|
||||
#define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR
|
||||
#define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0
|
||||
#define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0
|
||||
#define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0
|
||||
#define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0
|
||||
#define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0
|
||||
|
||||
#define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only
|
||||
|
||||
#define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only
|
||||
|
||||
#define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange
|
||||
|
||||
|
||||
#define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3
|
||||
#define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0
|
||||
#define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1
|
||||
#define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2
|
||||
#define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3
|
||||
|
||||
#define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7
|
||||
#define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4
|
||||
#define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5
|
||||
#define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6
|
||||
#define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7
|
||||
|
||||
#define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11
|
||||
#define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8
|
||||
#define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9
|
||||
#define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10
|
||||
#define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11
|
||||
|
||||
#define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15
|
||||
#define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12
|
||||
#define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13
|
||||
#define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14
|
||||
#define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15
|
||||
|
||||
#define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19
|
||||
#define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16
|
||||
#define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17
|
||||
#define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18
|
||||
#define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19
|
||||
|
||||
#define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23
|
||||
#define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20
|
||||
#define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21
|
||||
#define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22
|
||||
#define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23
|
||||
|
||||
#define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27
|
||||
#define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24
|
||||
#define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25
|
||||
#define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26
|
||||
#define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27
|
||||
|
||||
#define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31
|
||||
#define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28
|
||||
#define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29
|
||||
#define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30
|
||||
#define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31
|
||||
|
||||
/* ******************************************************************************************************* */
|
||||
|
||||
/* PIOC Registers */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED00;
|
||||
union {
|
||||
__IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR
|
||||
struct {
|
||||
__IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address
|
||||
__IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count
|
||||
__IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit
|
||||
__IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config
|
||||
struct {
|
||||
__IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle
|
||||
__IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2
|
||||
__IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode
|
||||
__IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output
|
||||
} ;
|
||||
} ;
|
||||
uint32_t RESERVED0C;
|
||||
uint32_t RESERVED10;
|
||||
uint32_t RESERVED14;
|
||||
uint32_t RESERVED18;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_CTRL ; // RW/RW, data control
|
||||
struct {
|
||||
__IO uint8_t D8_SYS_CFG; // RW/RW, port config
|
||||
__IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only
|
||||
__IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only
|
||||
__IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0
|
||||
__IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1
|
||||
__IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2
|
||||
__IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3
|
||||
} ;
|
||||
__IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4
|
||||
__IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5
|
||||
__IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6
|
||||
__IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8
|
||||
__IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9
|
||||
__IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10
|
||||
__IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12
|
||||
__IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13
|
||||
__IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14
|
||||
__IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16
|
||||
__IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17
|
||||
__IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18
|
||||
__IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20
|
||||
__IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21
|
||||
__IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22
|
||||
__IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24
|
||||
__IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25
|
||||
__IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26
|
||||
__IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27
|
||||
} ;
|
||||
} ;
|
||||
union {
|
||||
__IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31
|
||||
struct {
|
||||
__IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28
|
||||
__IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29
|
||||
__IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30
|
||||
__IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31
|
||||
} ;
|
||||
} ;
|
||||
} PIOC_TypeDef;
|
||||
|
||||
#define PIOC ((PIOC_TypeDef *)PIOC_BASE)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif // __PIOC_SFR_H__
|
||||
2965
Peripheral/inc/ch32x035.h
Normal file
2965
Peripheral/inc/ch32x035.h
Normal file
File diff suppressed because it is too large
Load diff
210
Peripheral/inc/ch32x035_adc.h
Normal file
210
Peripheral/inc/ch32x035_adc.h
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_adc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* ADC firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_ADC_H
|
||||
#define __CH32X035_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* ADC Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
|
||||
dual mode.
|
||||
This parameter can be a value of @ref ADC_mode */
|
||||
|
||||
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
|
||||
Scan (multichannels) or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
|
||||
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align, Note:ADC_DataAlign_Left only applies to regular channels */
|
||||
|
||||
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 16. */
|
||||
|
||||
uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref ADC_OutputBuffer */
|
||||
|
||||
uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
|
||||
This parameter can be a value of @ref ADC_Pga */
|
||||
} ADC_InitTypeDef;
|
||||
|
||||
/* ADC_mode */
|
||||
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||
|
||||
/* ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000)
|
||||
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000)
|
||||
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000)
|
||||
#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000)
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x000A0000)
|
||||
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000)
|
||||
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
|
||||
|
||||
/* ADC_data_align */
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
|
||||
/* ADC_channels */
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_15)
|
||||
|
||||
/* ADC_sampling_time */
|
||||
#define ADC_SampleTime_4Cycles ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_5Cycles ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_6Cycles ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_7Cycles ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_8Cycles ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_9Cycles ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_10Cycles ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_11Cycles ((uint8_t)0x07)
|
||||
|
||||
/* ADC_external_trigger_sources_for_injected_channels_conversion */
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00004000)
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000)
|
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000)
|
||||
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
|
||||
|
||||
/* ADC_injected_channel_selection */
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||
|
||||
/* ADC_analog_watchdog_selection */
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
|
||||
/* ADC_interrupts_definition */
|
||||
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||
|
||||
/* ADC_flags_definition */
|
||||
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||
|
||||
/* ADC_analog_watchdog_reset_enable_selection */
|
||||
#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00001000)
|
||||
#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00002000)
|
||||
#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00004000)
|
||||
#define ADC_AnalogWatchdog_3_RST_EN ((uint32_t)0x00008000)
|
||||
|
||||
/* ADC_analog_watchdog_reset_flags_definition */
|
||||
#define ADC_AnalogWatchdogResetFLAG_0 ((uint32_t)0x00010000)
|
||||
#define ADC_AnalogWatchdogResetFLAG_1 ((uint32_t)0x00020000)
|
||||
#define ADC_AnalogWatchdogResetFLAG_2 ((uint32_t)0x00040000)
|
||||
#define ADC_AnalogWatchdogResetFLAG_3 ((uint32_t)0x00080000)
|
||||
|
||||
/* ADC_clock */
|
||||
#define ADC_CLK_Div4 ((uint32_t)0x00000013)
|
||||
#define ADC_CLK_Div5 ((uint32_t)0x00000014)
|
||||
#define ADC_CLK_Div6 ((uint32_t)0x00000025)
|
||||
#define ADC_CLK_Div7 ((uint32_t)0x00000026)
|
||||
#define ADC_CLK_Div8 ((uint32_t)0x00000037)
|
||||
#define ADC_CLK_Div9 ((uint32_t)0x00000038)
|
||||
#define ADC_CLK_Div10 ((uint32_t)0x00000049)
|
||||
#define ADC_CLK_Div11 ((uint32_t)0x0000004A)
|
||||
#define ADC_CLK_Div12 ((uint32_t)0x0000005B)
|
||||
#define ADC_CLK_Div13 ((uint32_t)0x0000005C)
|
||||
#define ADC_CLK_Div14 ((uint32_t)0x0000006D)
|
||||
#define ADC_CLK_Div15 ((uint32_t)0x0000006E)
|
||||
#define ADC_CLK_Div16 ((uint32_t)0x0000007F)
|
||||
|
||||
|
||||
void ADC_DeInit(ADC_TypeDef *ADCx);
|
||||
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
|
||||
uint32_t ADC_GetDualModeConversionValue(void);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
|
||||
void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState);
|
||||
void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
|
||||
void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
48
Peripheral/inc/ch32x035_awu.h
Normal file
48
Peripheral/inc/ch32x035_awu.h
Normal file
|
|
@ -0,0 +1,48 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_awu.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* AWU firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_AWU_H
|
||||
#define __CH32X035_AWU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* PWR_AWU_Prescaler */
|
||||
#define AWU_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define AWU_Prescaler_2 ((uint32_t)0x00000002)
|
||||
#define AWU_Prescaler_4 ((uint32_t)0x00000003)
|
||||
#define AWU_Prescaler_8 ((uint32_t)0x00000004)
|
||||
#define AWU_Prescaler_16 ((uint32_t)0x00000005)
|
||||
#define AWU_Prescaler_32 ((uint32_t)0x00000006)
|
||||
#define AWU_Prescaler_64 ((uint32_t)0x00000007)
|
||||
#define AWU_Prescaler_128 ((uint32_t)0x00000008)
|
||||
#define AWU_Prescaler_256 ((uint32_t)0x00000009)
|
||||
#define AWU_Prescaler_512 ((uint32_t)0x0000000A)
|
||||
#define AWU_Prescaler_1024 ((uint32_t)0x0000000B)
|
||||
#define AWU_Prescaler_2048 ((uint32_t)0x0000000C)
|
||||
#define AWU_Prescaler_4096 ((uint32_t)0x0000000D)
|
||||
#define AWU_Prescaler_10240 ((uint32_t)0x0000000E)
|
||||
#define AWU_Prescaler_61440 ((uint32_t)0x0000000F)
|
||||
|
||||
|
||||
void AutoWakeUpCmd(FunctionalState NewState);
|
||||
void AWU_SetPrescaler(uint32_t AWU_Prescaler);
|
||||
void AWU_SetWindowValue(uint8_t WindowValue);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
41
Peripheral/inc/ch32x035_dbgmcu.h
Normal file
41
Peripheral/inc/ch32x035_dbgmcu.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_dbgmcu.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* DBGMCU firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_DBGMCU_H
|
||||
#define __CH32X035_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
|
||||
#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000)
|
||||
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
uint32_t __get_DEBUG_CR(void);
|
||||
void __set_DEBUG_CR(uint32_t value);
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
uint32_t DBGMCU_GetCHIPID( void );
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
184
Peripheral/inc/ch32x035_dma.h
Normal file
184
Peripheral/inc/ch32x035_dma.h
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_dma.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* DMA firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_DMA_H
|
||||
#define __CH32X035_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* DMA Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/* DMA_data_transfer_direction */
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_peripheral_incremented_mode */
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_memory_incremented_mode */
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_peripheral_data_size */
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||
|
||||
/* DMA_memory_data_size */
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
|
||||
/* DMA_circular_normal_mode */
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_priority_level */
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_memory_to_memory */
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_interrupts_definition */
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
#define DMA1_IT_GL8 ((uint32_t)0x10000000)
|
||||
#define DMA1_IT_TC8 ((uint32_t)0x20000000)
|
||||
#define DMA1_IT_HT8 ((uint32_t)0x40000000)
|
||||
#define DMA1_IT_TE8 ((uint32_t)0x80000000)
|
||||
|
||||
/* DMA_flags_definition */
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
#define DMA1_FLAG_GL8 ((uint32_t)0x10000000)
|
||||
#define DMA1_FLAG_TC8 ((uint32_t)0x20000000)
|
||||
#define DMA1_FLAG_HT8 ((uint32_t)0x40000000)
|
||||
#define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
|
||||
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
99
Peripheral/inc/ch32x035_exti.h
Normal file
99
Peripheral/inc/ch32x035_exti.h
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_exti.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* EXTI firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_EXTI_H
|
||||
#define __CH32X035_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* EXTI mode enumeration */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
} EXTIMode_TypeDef;
|
||||
|
||||
/* EXTI Trigger enumeration */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
} EXTITrigger_TypeDef;
|
||||
|
||||
/* EXTI Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} EXTI_InitTypeDef;
|
||||
|
||||
/* EXTI_Lines */
|
||||
#define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 */
|
||||
#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 */
|
||||
#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 */
|
||||
#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 */
|
||||
#define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 */
|
||||
#define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 */
|
||||
#define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 */
|
||||
#define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 */
|
||||
#define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the PC18(SDI on) */
|
||||
#define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the PC19(SDI on) */
|
||||
#define EXTI_Line26 ((uint32_t)0x04000000) /* External interrupt line 26 Connected to the PVD Output */
|
||||
#define EXTI_Line27 ((uint32_t)0x08000000) /* External interrupt line 27 Connected to the Auto Wake-up event */
|
||||
#define EXTI_Line28 ((uint32_t)0x10000000) /* External interrupt line 28 Connected to the the USBFS Wake-up event */
|
||||
#define EXTI_Line29 ((uint32_t)0x20000000) /* External interrupt line 29 Connected to the the USB PD Wake-up event */
|
||||
|
||||
|
||||
void EXTI_DeInit(void);
|
||||
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
149
Peripheral/inc/ch32x035_flash.h
Normal file
149
Peripheral/inc/ch32x035_flash.h
Normal file
|
|
@ -0,0 +1,149 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_flash.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_FLASH_H
|
||||
#define __CH32X035_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* FLASH Status */
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_PG,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT,
|
||||
FLASH_RDP,
|
||||
FLASH_OP_RANGE_ERROR = 0xFD,
|
||||
FLASH_ALIGN_ERROR = 0xFE,
|
||||
FLASH_ADR_RANGE_ERROR = 0xFF,
|
||||
} FLASH_Status;
|
||||
|
||||
/* Flash_Latency */
|
||||
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
|
||||
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
|
||||
|
||||
/* Values to be used with devices (1page = 256Byte) */
|
||||
#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */
|
||||
#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */
|
||||
#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */
|
||||
#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */
|
||||
#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */
|
||||
#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */
|
||||
#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */
|
||||
#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */
|
||||
#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */
|
||||
#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */
|
||||
#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */
|
||||
#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */
|
||||
#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */
|
||||
#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */
|
||||
#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */
|
||||
#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */
|
||||
#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */
|
||||
#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */
|
||||
#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */
|
||||
#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */
|
||||
#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */
|
||||
#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */
|
||||
#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */
|
||||
#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */
|
||||
#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */
|
||||
#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */
|
||||
#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */
|
||||
#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */
|
||||
#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */
|
||||
#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */
|
||||
#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */
|
||||
|
||||
|
||||
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
|
||||
|
||||
/* Option_Bytes_IWatchdog */
|
||||
#define OB_IWDG_SW ((uint8_t)0x01) /* Software IWDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /* Hardware IWDG selected */
|
||||
|
||||
/* Option_Bytes_nRST_STOP */
|
||||
#define OB_STOP_NoRST ((uint8_t)0x02) /* No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /* Reset generated when entering in STOP */
|
||||
|
||||
/* Option_Bytes_nRST_STDBY */
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x04) /* No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /* Reset generated when entering in STANDBY */
|
||||
|
||||
/* Option_Bytes_RST_ENandDT */
|
||||
#define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */
|
||||
#define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */
|
||||
#define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */
|
||||
#define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */
|
||||
|
||||
/* FLASH_Interrupts */
|
||||
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
|
||||
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
|
||||
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
|
||||
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
|
||||
|
||||
/* FLASH_Flags */
|
||||
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
|
||||
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
|
||||
|
||||
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
|
||||
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
|
||||
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
|
||||
|
||||
/* System_Reset_Start_Mode */
|
||||
#define Start_Mode_USER ((uint32_t)0x00000000)
|
||||
#define Start_Mode_BOOT ((uint32_t)0x00004000)
|
||||
|
||||
|
||||
/*Functions used for all CH32V00x devices*/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_EraseAllPages(void);
|
||||
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
|
||||
FLASH_Status FLASH_EnableReadOutProtection(void);
|
||||
FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST);
|
||||
uint32_t FLASH_GetUserOptionByte(void);
|
||||
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
void FLASH_Unlock_Fast(void);
|
||||
void FLASH_Lock_Fast(void);
|
||||
void FLASH_BufReset(void);
|
||||
void FLASH_BufLoad(uint32_t Address, uint32_t Data0);
|
||||
void FLASH_ErasePage_Fast(uint32_t Page_Address);
|
||||
void FLASH_ProgramPage_Fast(uint32_t Page_Address);
|
||||
void SystemReset_StartMode(uint32_t Mode);
|
||||
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
|
||||
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
181
Peripheral/inc/ch32x035_gpio.h
Normal file
181
Peripheral/inc/ch32x035_gpio.h
Normal file
|
|
@ -0,0 +1,181 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_gpio.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* GPIO firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_GPIO_H
|
||||
#define __CH32X035_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* Output Maximum frequency selection */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_50MHz = 1,
|
||||
} GPIOSpeed_TypeDef;
|
||||
|
||||
/* Configuration Mode enumeration */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_AIN = 0x0,
|
||||
GPIO_Mode_IN_FLOATING = 0x04,
|
||||
GPIO_Mode_IPD = 0x28, /* Only PA0--PA15 and PC16--PC17 support input pull-down */
|
||||
GPIO_Mode_IPU = 0x48,
|
||||
GPIO_Mode_Out_PP = 0x10,
|
||||
GPIO_Mode_AF_PP = 0x18
|
||||
} GPIOMode_TypeDef;
|
||||
|
||||
/* GPIO Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/* Bit_SET and Bit_RESET enumeration */
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
} BitAction;
|
||||
|
||||
/* GPIO_pins_define */
|
||||
#define GPIO_Pin_0 ((uint32_t)0x000001) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint32_t)0x000002) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint32_t)0x000004) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint32_t)0x000008) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint32_t)0x000010) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint32_t)0x000020) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint32_t)0x000040) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint32_t)0x000080) /* Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint32_t)0x000100) /* Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint32_t)0x000200) /* Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint32_t)0x000400) /* Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint32_t)0x000800) /* Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint32_t)0x001000) /* Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint32_t)0x002000) /* Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint32_t)0x004000) /* Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint32_t)0x008000) /* Pin 15 selected */
|
||||
#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */
|
||||
#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */
|
||||
#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */
|
||||
#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */
|
||||
#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */
|
||||
#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */
|
||||
#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */
|
||||
#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */
|
||||
#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */
|
||||
|
||||
/* GPIO_Remap_define */
|
||||
/* PCFR1 */
|
||||
#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08000004) /* I2C1 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08000008) /* I2C1 Partial2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0800000C) /* I2C1 Partial3 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08000010) /* I2C1 Partial4 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_I2C1 ((uint32_t)0x08000014) /* I2C1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08000080) /* USART2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08000100) /* USART2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08000180) /* USART2 Partial3 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART2 ((uint32_t)0x08000200) /* USART2 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00100400) /* USART3 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_USART3 ((uint32_t)0x00100800) /* USART3 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART3 ((uint32_t)0x00100C00) /* USART3 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_USART4 ((uint32_t)0x08001000) /* USART4 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_USART4 ((uint32_t)0x08002000) /* USART4 Partial2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap3_USART4 ((uint32_t)0x08003000) /* USART4 Partial3 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap4_USART4 ((uint32_t)0x08004000) /* USART4 Partial4 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART4 ((uint32_t)0x08007000) /* USART4 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x08400001) /* TIM1 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x08400002) /* TIM1 Partial2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x08400003) /* TIM1 Partial3 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM1 ((uint32_t)0x08400004) /* TIM1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08200004) /* TIM2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08200008) /* TIM2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0820000C) /* TIM2 Partial3 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08200010) /* TIM2 Partial4 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08200014) /* TIM2 Partial5 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM2 ((uint32_t)0x08200018) /* TIM2 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00300020) /* TIM3 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00300040) /* TIM3 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM3 ((uint32_t)0x00300060) /* TIM3 Full Alternate Function mapping */
|
||||
#define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */
|
||||
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */
|
||||
|
||||
/* GPIO_Port_Sources */
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||
|
||||
/* GPIO_Pin_sources */
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
#define GPIO_PinSource16 ((uint8_t)0x10)
|
||||
#define GPIO_PinSource17 ((uint8_t)0x11)
|
||||
#define GPIO_PinSource18 ((uint8_t)0x12)
|
||||
#define GPIO_PinSource19 ((uint8_t)0x13)
|
||||
#define GPIO_PinSource20 ((uint8_t)0x14)
|
||||
#define GPIO_PinSource21 ((uint8_t)0x15)
|
||||
#define GPIO_PinSource22 ((uint8_t)0x16)
|
||||
#define GPIO_PinSource23 ((uint8_t)0x17)
|
||||
|
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef *GPIOx);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource);
|
||||
void GPIO_IPD_Unused(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
416
Peripheral/inc/ch32x035_i2c.h
Normal file
416
Peripheral/inc/ch32x035_i2c.h
Normal file
|
|
@ -0,0 +1,416 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_i2c.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* I2C firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_I2C_H
|
||||
#define __CH32X035_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* I2C Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t I2C_Mode; /* Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
} I2C_InitTypeDef;
|
||||
|
||||
/* I2C_mode */
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||
|
||||
/* I2C_duty_cycle_in_fast_mode */
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
|
||||
|
||||
/* I2C_acknowledgement */
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* I2C_transfer_direction */
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||
|
||||
/* I2C_acknowledged_address */
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||
|
||||
/* I2C_registers */
|
||||
#define I2C_Register_CTLR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CTLR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OADDR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_DATAR ((uint8_t)0x10)
|
||||
#define I2C_Register_STAR1 ((uint8_t)0x14)
|
||||
#define I2C_Register_STAR2 ((uint8_t)0x18)
|
||||
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
|
||||
#define I2C_Register_RTR ((uint8_t)0x20)
|
||||
|
||||
/* I2C_PEC_position */
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C_NACK_position */
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C_interrupts_definition */
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||
|
||||
/* I2C_interrupts_definition */
|
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||
|
||||
/* SR2 register flags */
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||
|
||||
/* SR1 register flags */
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||
|
||||
/****************I2C Master Events (Events grouped in order of communication)********************/
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Start communicate
|
||||
*
|
||||
* After master use I2C_GenerateSTART() function sending the START condition,the master
|
||||
* has to wait for event 5(the Start condition has been correctly
|
||||
* released on the I2C bus ).
|
||||
*
|
||||
*/
|
||||
/* EVT5 */
|
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* When start condition correctly released on the bus(check EVT5), the
|
||||
* master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
|
||||
* it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will be set:
|
||||
*
|
||||
*
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||
* event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||
* is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (after generating the START
|
||||
* and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
|
||||
* Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
|
||||
* on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
|
||||
* of the 10-bit address (LSB) . Then master should wait for event 6.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
/* EVT6 */
|
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
/*EVT9 */
|
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Communication events
|
||||
*
|
||||
* If START condition has generated and slave address
|
||||
* been acknowledged. then the master has to check one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use
|
||||
* I2C_ReceiveData() function to read the data received from the slave .
|
||||
*
|
||||
* 2) Master Transmitter mode: The master use I2C_SendData() function to send data
|
||||
* then to wait on event EVT8 or EVT8_2.
|
||||
* These two events are similar:
|
||||
* - EVT8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EVT8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EVT8 is sufficient for the application.
|
||||
* Using EVT8_2 will leads to a slower communication speed but will more reliable .
|
||||
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
|
||||
*
|
||||
*
|
||||
* Note:
|
||||
* In case the user software does not guarantee that this event EVT7 is managed before
|
||||
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
|
||||
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
/* Master Receive mode */
|
||||
/* EVT7 */
|
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master Transmitter mode*/
|
||||
/* EVT8 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
/* EVT8_2 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
/******************I2C Slave Events (Events grouped in order of communication)******************/
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Start Communicate events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a start condition of master device generate on the bus.
|
||||
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
|
||||
*
|
||||
*
|
||||
*
|
||||
* a) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* b) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* c) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* EVT1 */
|
||||
/* a) Case of One Single Address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* b) Case of Dual address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* c) Case of General Call enabled for the slave */
|
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
|
||||
/********************************************************************************************************************
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EVT1 has already been checked :
|
||||
*
|
||||
* - Slave Receiver mode:
|
||||
* - EVT2--The device is expecting to receive a data byte .
|
||||
* - EVT4--The device is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
|
||||
* the EVT3 is managed before the current byte end of transfer The second one can optionally
|
||||
* be used.
|
||||
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission
|
||||
* shall end . The slave device has to stop sending
|
||||
* data bytes and wait a Stop condition from bus.
|
||||
*
|
||||
* Note:
|
||||
* If the user software does not guarantee that the event 2 is
|
||||
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
|
||||
* and I2C_FLAG_BTF flag at the same time .
|
||||
* In this case the communication will be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Slave Receiver mode*/
|
||||
/* EVT2 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
/* EVT4 */
|
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||
|
||||
/* Slave Transmitter mode*/
|
||||
/* EVT3 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
/*EVT3_2 */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
|
||||
void I2C_DeInit(I2C_TypeDef *I2Cx);
|
||||
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
|
||||
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
|
||||
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
|
||||
|
||||
|
||||
/*****************************************************************************************
|
||||
*
|
||||
* I2C State Monitoring Functions
|
||||
*
|
||||
****************************************************************************************
|
||||
* This I2C driver provides three different ways for I2C state monitoring
|
||||
* profit the application requirements and constraints:
|
||||
*
|
||||
*
|
||||
* a) First way:
|
||||
* Using I2C_CheckEvent() function:
|
||||
* It compares the status registers (STARR1 and STAR2) content to a given event
|
||||
* (can be the combination of more flags).
|
||||
* If the current status registers includes the given flags will return SUCCESS.
|
||||
* and if the current status registers miss flags will returns ERROR.
|
||||
* - When to use:
|
||||
* - This function is suitable for most applications as well as for startup
|
||||
* activity since the events are fully described in the product reference manual
|
||||
* (CH64xRM).
|
||||
* - It is also suitable for users who need to define their own events.
|
||||
* - Limitations:
|
||||
* - If an error occurs besides to the monitored error,
|
||||
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||
* in corrupted state. it is suggeted to use error interrupts to monitor the error
|
||||
* events and handle them in IRQ handler.
|
||||
*
|
||||
*
|
||||
* Note:
|
||||
* The following functions are recommended for error management: :
|
||||
* - I2C_ITConfig() main function of configure and enable the error interrupts.
|
||||
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
|
||||
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
|
||||
* to determine which error occurred.
|
||||
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
|
||||
* \ I2C_GenerateStop() will be use to clear the error flag and source,
|
||||
* and return to correct communication status.
|
||||
*
|
||||
*
|
||||
* b) Second way:
|
||||
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
|
||||
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
|
||||
* - When to use:
|
||||
*
|
||||
* - This function is suitable for the same applications above but it
|
||||
* don't have the limitations of I2C_GetFlagStatus() function .
|
||||
* The returned value could be compared to events already defined in the
|
||||
* library (ch64x_i2c.h) or to custom values defined by user.
|
||||
* - This function can be used to monitor the status of multiple flags simultaneously.
|
||||
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to
|
||||
* accept the event according to the user's needs (when all event flags are set and
|
||||
* no other flags are set, or only when the required flags are set)
|
||||
*
|
||||
* - Limitations:
|
||||
* - User may need to define his own events.
|
||||
* - Same remark concerning the error management is applicable for this
|
||||
* function if user decides to check only regular communication flags (and
|
||||
* ignores error flags).
|
||||
*
|
||||
*
|
||||
* c) Third way:
|
||||
* Using the function I2C_GetFlagStatus() get the status of
|
||||
* one single flag .
|
||||
* - When to use:
|
||||
* - This function could be used for specific applications or in debug phase.
|
||||
* - It is suitable when only one flag checking is needed .
|
||||
*
|
||||
* - Limitations:
|
||||
* - Call this function to access the status register. Some flag bits may be cleared.
|
||||
* - Function may need to be called twice or more in order to monitor one single event.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*********************************************************
|
||||
*
|
||||
* a) Basic state monitoring(First way)
|
||||
********************************************************
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||
/*********************************************************
|
||||
*
|
||||
* b) Advanced state monitoring(Second way:)
|
||||
********************************************************
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||
/*********************************************************
|
||||
*
|
||||
* c) Flag-based state monitoring(Third way)
|
||||
*********************************************************
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
|
||||
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
50
Peripheral/inc/ch32x035_iwdg.h
Normal file
50
Peripheral/inc/ch32x035_iwdg.h
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_iwdg.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* IWDG firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_IWDG_H
|
||||
#define __CH32X035_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* IWDG_WriteAccess */
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* IWDG_prescaler */
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
|
||||
/* IWDG_Flag */
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
void IWDG_Enable(void);
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
45
Peripheral/inc/ch32x035_misc.h
Normal file
45
Peripheral/inc/ch32x035_misc.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_misc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* miscellaneous firmware library functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_MISC_H
|
||||
#define __CH32X035_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* NVIC Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel;
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority;
|
||||
uint8_t NVIC_IRQChannelSubPriority;
|
||||
FunctionalState NVIC_IRQChannelCmd;
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/* Preemption_Priority_Group */
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x00)
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x01)
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x02)
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
221
Peripheral/inc/ch32x035_opa.h
Normal file
221
Peripheral/inc/ch32x035_opa.h
Normal file
|
|
@ -0,0 +1,221 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_opa.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* OPA firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_OPA_H
|
||||
#define __CH32X035_OPA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* OPA_member_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
OPA1 = 0,
|
||||
OPA2
|
||||
} OPA_Num_TypeDef;
|
||||
|
||||
/* OPA_out_channel_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
OUT_IO_OUT0 = 0,
|
||||
OUT_IO_OUT1
|
||||
} OPA_Mode_TypeDef;
|
||||
|
||||
/* OPA_PSEL_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CHP0 = 0,
|
||||
CHP1,
|
||||
CHP2,
|
||||
CHP_OFF
|
||||
} OPA_PSEL_TypeDef;
|
||||
|
||||
/* OPA_FB_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
FB_OFF = 0,
|
||||
FB_ON
|
||||
} OPA_FB_TypeDef;
|
||||
|
||||
/* OPA_NSEL_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CHN0 = 0,
|
||||
CHN1,
|
||||
CHN2_PGA_16xIN,
|
||||
CHN_PGA_4xIN,
|
||||
CHN_PGA_8xIN,
|
||||
CHN_PGA_16xIN,
|
||||
CHN_PGA_32xIN,
|
||||
CHN_OFF
|
||||
} OPA_NSEL_TypeDef;
|
||||
|
||||
/* OPA_PSEL_POLL_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CHP_OPA1_OFF_OPA2_OFF = 0,
|
||||
CHP_OPA1_ON_OPA2_OFF,
|
||||
CHP_OPA1_OFF_OPA2_ON,
|
||||
CHP_OPA1_ON_OPA2_ON
|
||||
} OPA_PSEL_POLL_TypeDef;
|
||||
|
||||
/* OPA_BKIN_EN_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
BKIN_OPA1_OFF_OPA2_OFF = 0,
|
||||
BKIN_OPA1_ON_OPA2_OFF,
|
||||
BKIN_OPA1_OFF_OPA2_ON,
|
||||
BKIN_OPA1_ON_OPA2_ON
|
||||
} OPA_BKIN_EN_TypeDef;
|
||||
|
||||
/* OPA_RST_EN_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
RST_OPA1_OFF_OPA2_OFF = 0,
|
||||
RST_OPA1_ON_OPA2_OFF,
|
||||
RST_OPA1_OFF_OPA2_ON,
|
||||
RST_OPA1_ON_OPA2_ON
|
||||
} OPA_RST_EN_TypeDef;
|
||||
|
||||
/* OPA_BKIN_SEL_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
BKIN_OPA1_TIM1_OPA2_TIM2 = 0,
|
||||
BKIN_OPA1_TIM2_OPA2_TIM1
|
||||
} OPA_BKIN_SEL_TypeDef;
|
||||
|
||||
/* OPA_OUT_IE_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
OUT_IE_OPA1_OFF_OPA2_OFF = 0,
|
||||
OUT_IE_OPA1_ON_OPA2_OFF,
|
||||
OUT_IE_OPA1_OFF_OPA2_ON,
|
||||
OUT_IE_OPA1_ON_OPA2_ON
|
||||
} OPA_OUT_IE_TypeDef;
|
||||
|
||||
/* OPA_CNT_IE_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CNT_IE_OFF = 0,
|
||||
CNT_IE_ON,
|
||||
} OPA_CNT_IE_TypeDef;
|
||||
|
||||
/* OPA_NMI_IE_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
NMI_IE_OFF = 0,
|
||||
NMI_IE_ON,
|
||||
} OPA_NMI_IE_TypeDef;
|
||||
|
||||
/* OPA_PSEL_POLL_NUM_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CHP_POLL_NUM_1 = 0,
|
||||
CHP_POLL_NUM_2,
|
||||
CHP_POLL_NUM_3
|
||||
} OPA_PSEL_POLL_NUM_TypeDef;
|
||||
|
||||
|
||||
/* OPA Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us
|
||||
This parameter must range from 0 to 0x1FF.*/
|
||||
OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */
|
||||
OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */
|
||||
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
|
||||
OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */
|
||||
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
|
||||
OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */
|
||||
OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */
|
||||
OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */
|
||||
OPA_BKIN_SEL_TypeDef BKIN_SEL; /* Specifies the brake input source selection of OPA */
|
||||
OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */
|
||||
OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */
|
||||
OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */
|
||||
OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/
|
||||
} OPA_InitTypeDef;
|
||||
|
||||
/* CMP_member_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CMP1 = 0,
|
||||
CMP2,
|
||||
CMP3
|
||||
} CMP_Num_TypeDef;
|
||||
|
||||
/* CMP_out_channel_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
OUT_IO_TIM2 = 0,
|
||||
OUT_IO0
|
||||
} CMP_Mode_TypeDef;
|
||||
|
||||
/* CMP_NSEL_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CMP_CHN0 = 0,
|
||||
CMP_CHN1,
|
||||
} CMP_NSEL_TypeDef;
|
||||
|
||||
/* CMP_PSEL_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CMP_CHP1 = 0,
|
||||
CMP_CHP2,
|
||||
} CMP_PSEL_TypeDef;
|
||||
|
||||
/* CMP_HYEN_enumeration */
|
||||
typedef enum
|
||||
{
|
||||
CMP_HYEN1 = 0,
|
||||
CMP_HYEN2,
|
||||
} CMP_HYEN_TypeDef;
|
||||
|
||||
/* CMP Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */
|
||||
CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */
|
||||
CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */
|
||||
CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */
|
||||
CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */
|
||||
} CMP_InitTypeDef;
|
||||
|
||||
/* OPA_flags_definition */
|
||||
#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000)
|
||||
#define OPA_FLAG_OUT_OPA2 ((uint16_t)0x2000)
|
||||
#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000)
|
||||
|
||||
void OPA_Unlock(void);
|
||||
void OPA_Lock(void);
|
||||
void OPA_POLL_Unlock(void);
|
||||
void OPA_POLL_Lock(void);
|
||||
void OPA_CMP_Unlock(void);
|
||||
void OPA_CMP_Lock(void);
|
||||
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct);
|
||||
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct);
|
||||
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
|
||||
void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct);
|
||||
void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct);
|
||||
void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState);
|
||||
FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG);
|
||||
void OPA_ClearFlag(uint16_t OPA_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
50
Peripheral/inc/ch32x035_pwr.h
Normal file
50
Peripheral/inc/ch32x035_pwr.h
Normal file
|
|
@ -0,0 +1,50 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_pwr.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the PWR
|
||||
* firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_PWR_H
|
||||
#define __CH32X035_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* PVD_detection_level */
|
||||
#define PWR_PVDLevel_2V1 ((uint32_t)0x00000000)
|
||||
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
|
||||
#define PWR_PVDLevel_3V0 ((uint32_t)0x00000040)
|
||||
#define PWR_PVDLevel_4V0 ((uint32_t)0x00000060)
|
||||
|
||||
/* STOP_mode_entry */
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
|
||||
/* PWR_Flag */
|
||||
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||
#define PWR_FLAG_FLASH ((uint32_t)0x00000020)
|
||||
|
||||
/* PWR_VDD_Supply_Voltage */
|
||||
typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD;
|
||||
|
||||
void PWR_DeInit(void);
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
PWR_VDD PWR_VDD_SupplyVoltage(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
111
Peripheral/inc/ch32x035_rcc.h
Normal file
111
Peripheral/inc/ch32x035_rcc.h
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_rcc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the RCC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_RCC_H
|
||||
#define __CH32X035_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* RCC_Exported_Types */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
|
||||
} RCC_ClocksTypeDef;
|
||||
|
||||
/* AHB_clock_source */
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
|
||||
#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030)
|
||||
#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040)
|
||||
#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050)
|
||||
#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
|
||||
|
||||
/* AHB_peripheral */
|
||||
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
|
||||
#define RCC_AHBPeriph_IO2W ((uint32_t)0x00002000)
|
||||
#define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000)
|
||||
|
||||
/* APB2_peripheral */
|
||||
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
|
||||
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||
|
||||
/* APB1_peripheral */
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
|
||||
/* Clock_source_to_output_on_MCO_pin */
|
||||
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||
|
||||
/* RCC_Flag */
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_OPARST ((uint8_t)0x79)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
/* SysTick_clock_source */
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
|
||||
|
||||
void RCC_DeInit(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
153
Peripheral/inc/ch32x035_spi.h
Normal file
153
Peripheral/inc/ch32x035_spi.h
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_spi.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* SPI firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_SPI_H
|
||||
#define __CH32X035_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* SPI Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /* Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
|
||||
} SPI_InitTypeDef;
|
||||
|
||||
/* SPI_data_direction */
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
|
||||
/* SPI_mode */
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
|
||||
/* SPI_data_size */
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||
|
||||
/* SPI_Clock_Polarity */
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||
|
||||
/* SPI_Clock_Phase */
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
|
||||
/* SPI_Slave_Select_management */
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
|
||||
/* SPI_BaudRate_Prescaler */
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
|
||||
/* SPI_MSB_LSB_transmission */
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode
|
||||
|
||||
/* SPI_I2S_DMA_transfer_requests */
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
|
||||
/* SPI_NSS_internal_software_management */
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
|
||||
/* SPI_CRC_Transmit_Receive */
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
|
||||
/* SPI_direction_transmit_receive */
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
|
||||
/* SPI_I2S_interrupts_definition */
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||
|
||||
/* SPI_I2S_flags_definition */
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
|
||||
void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
|
||||
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
|
||||
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_TransmitCRC(SPI_TypeDef *SPIx);
|
||||
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
530
Peripheral/inc/ch32x035_tim.h
Normal file
530
Peripheral/inc/ch32x035_tim.h
Normal file
|
|
@ -0,0 +1,530 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_tim.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* TIM firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_TIM_H
|
||||
#define __CH32X035_TIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* TIM Time Base Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t TIM_CounterMode; /* Specifies the counter mode.
|
||||
This parameter can be a value of @ref TIM_Counter_Mode (TIM1 and TIM2) */
|
||||
|
||||
uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
|
||||
Auto-Reload Register at the next update event.
|
||||
This parameter must be a number between 0x0000 and 0xFFFF. */
|
||||
|
||||
uint16_t TIM_ClockDivision; /* Specifies the clock division.
|
||||
This parameter can be a value of @ref TIM_Clock_Division_CKD */
|
||||
|
||||
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
|
||||
reaches zero, an update event is generated and counting restarts
|
||||
from the RCR value (N).
|
||||
This means in PWM mode that (N+1) corresponds to:
|
||||
- the number of PWM periods in edge-aligned mode
|
||||
- the number of half PWM period in center-aligned mode
|
||||
This parameter must be a number between 0x00 and 0xFF.
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
} TIM_TimeBaseInitTypeDef;
|
||||
|
||||
/* TIM Output Compare Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_OCMode; /* Specifies the TIM mode.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||
|
||||
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_state */
|
||||
|
||||
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_state
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
|
||||
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||
|
||||
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
|
||||
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
|
||||
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
} TIM_OCInitTypeDef;
|
||||
|
||||
/* TIM Input Capture Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_Channel; /* Specifies the TIM channel.
|
||||
This parameter can be a value of @ref TIM_Channel */
|
||||
|
||||
uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint16_t TIM_ICSelection; /* Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint16_t TIM_ICFilter; /* Specifies the input capture filter.
|
||||
This parameter can be a number between 0x0 and 0xF */
|
||||
} TIM_ICInitTypeDef;
|
||||
|
||||
/* BDTR structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
|
||||
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
|
||||
uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
|
||||
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
|
||||
uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
|
||||
This parameter can be a value of @ref Lock_level */
|
||||
|
||||
uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
|
||||
switching-on of the outputs.
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
|
||||
This parameter can be a value of @ref Break_Input_enable_disable */
|
||||
|
||||
uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
|
||||
This parameter can be a value of @ref Break_Polarity */
|
||||
|
||||
uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
} TIM_BDTRInitTypeDef;
|
||||
|
||||
/* TIM_Output_Compare_and_PWM_modes */
|
||||
#define TIM_OCMode_Timing ((uint16_t)0x0000)
|
||||
#define TIM_OCMode_Active ((uint16_t)0x0010)
|
||||
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
|
||||
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
|
||||
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
|
||||
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
|
||||
|
||||
/* TIM_One_Pulse_Mode */
|
||||
#define TIM_OPMode_Single ((uint16_t)0x0008)
|
||||
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Channel */
|
||||
#define TIM_Channel_1 ((uint16_t)0x0000)
|
||||
#define TIM_Channel_2 ((uint16_t)0x0004)
|
||||
#define TIM_Channel_3 ((uint16_t)0x0008)
|
||||
#define TIM_Channel_4 ((uint16_t)0x000C)
|
||||
|
||||
/* TIM_Clock_Division_CKD */
|
||||
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
|
||||
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
|
||||
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
|
||||
|
||||
/* TIM_Counter_Mode */
|
||||
#define TIM_CounterMode_Up ((uint16_t)0x0000)
|
||||
#define TIM_CounterMode_Down ((uint16_t)0x0010)
|
||||
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
|
||||
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
|
||||
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
|
||||
|
||||
/* TIM_Output_Compare_Polarity */
|
||||
#define TIM_OCPolarity_High ((uint16_t)0x0000)
|
||||
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
|
||||
|
||||
/* TIM_Output_Compare_N_Polarity */
|
||||
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
|
||||
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
|
||||
|
||||
/* TIM_Output_Compare_state */
|
||||
#define TIM_OutputState_Disable ((uint16_t)0x0000)
|
||||
#define TIM_OutputState_Enable ((uint16_t)0x0001)
|
||||
|
||||
/* TIM_Output_Compare_N_state */
|
||||
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
|
||||
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
|
||||
|
||||
/* TIM_Capture_Compare_state */
|
||||
#define TIM_CCx_Enable ((uint16_t)0x0001)
|
||||
#define TIM_CCx_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Capture_Compare_N_state */
|
||||
#define TIM_CCxN_Enable ((uint16_t)0x0004)
|
||||
#define TIM_CCxN_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* Break_Input_enable_disable */
|
||||
#define TIM_Break_Enable ((uint16_t)0x1000)
|
||||
#define TIM_Break_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* Break_Polarity */
|
||||
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
|
||||
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
|
||||
|
||||
/* TIM_AOE_Bit_Set_Reset */
|
||||
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
|
||||
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* Lock_level */
|
||||
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
|
||||
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
|
||||
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
|
||||
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
|
||||
|
||||
/* OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
|
||||
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
|
||||
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_Idle_State */
|
||||
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
|
||||
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_N_Idle_State */
|
||||
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
|
||||
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Input_Capture_Polarity */
|
||||
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
|
||||
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
|
||||
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
|
||||
|
||||
/* TIM_Input_Capture_Selection */
|
||||
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
|
||||
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
|
||||
connected to IC2, IC1, IC4 or IC3, respectively. */
|
||||
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
|
||||
|
||||
/* TIM_Input_Capture_Prescaler */
|
||||
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
|
||||
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
|
||||
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
|
||||
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
|
||||
|
||||
/* TIM_interrupt_sources */
|
||||
#define TIM_IT_Update ((uint16_t)0x0001)
|
||||
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_IT_COM ((uint16_t)0x0020)
|
||||
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_IT_Break ((uint16_t)0x0080)
|
||||
|
||||
/* TIM_DMA_Base_address */
|
||||
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
|
||||
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
|
||||
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
|
||||
#define TIM_DMABase_DIER ((uint16_t)0x0003)
|
||||
#define TIM_DMABase_SR ((uint16_t)0x0004)
|
||||
#define TIM_DMABase_EGR ((uint16_t)0x0005)
|
||||
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
|
||||
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
|
||||
#define TIM_DMABase_CCER ((uint16_t)0x0008)
|
||||
#define TIM_DMABase_CNT ((uint16_t)0x0009)
|
||||
#define TIM_DMABase_PSC ((uint16_t)0x000A)
|
||||
#define TIM_DMABase_ARR ((uint16_t)0x000B)
|
||||
#define TIM_DMABase_RCR ((uint16_t)0x000C)
|
||||
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
|
||||
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
|
||||
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
|
||||
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
|
||||
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
|
||||
#define TIM_DMABase_DCR ((uint16_t)0x0012)
|
||||
|
||||
/* TIM_DMA_Burst_Length */
|
||||
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
|
||||
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
|
||||
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
|
||||
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
|
||||
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
|
||||
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
|
||||
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
|
||||
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
|
||||
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
|
||||
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
|
||||
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
|
||||
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
|
||||
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
|
||||
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
|
||||
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
|
||||
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
|
||||
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
|
||||
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
|
||||
|
||||
/* TIM_DMA_sources */
|
||||
#define TIM_DMA_Update ((uint16_t)0x0100)
|
||||
#define TIM_DMA_CC1 ((uint16_t)0x0200)
|
||||
#define TIM_DMA_CC2 ((uint16_t)0x0400)
|
||||
#define TIM_DMA_CC3 ((uint16_t)0x0800)
|
||||
#define TIM_DMA_CC4 ((uint16_t)0x1000)
|
||||
#define TIM_DMA_COM ((uint16_t)0x2000)
|
||||
#define TIM_DMA_Trigger ((uint16_t)0x4000)
|
||||
|
||||
/* TIM_External_Trigger_Prescaler */
|
||||
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
||||
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
||||
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
||||
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
||||
|
||||
/* TIM_Internal_Trigger_Selection */
|
||||
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
||||
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
||||
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
||||
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
||||
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
||||
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
||||
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
||||
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
||||
|
||||
/* TIM_TIx_External_Clock_Source */
|
||||
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
||||
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
||||
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
||||
|
||||
/* TIM_External_Trigger_Polarity */
|
||||
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
||||
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Prescaler_Reload_Mode */
|
||||
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
||||
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
||||
|
||||
/* TIM_Forced_Action */
|
||||
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
||||
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
||||
|
||||
/* TIM_Encoder_Mode */
|
||||
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
||||
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
||||
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
||||
|
||||
/* TIM_Event_Source */
|
||||
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
||||
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_EventSource_COM ((uint16_t)0x0020)
|
||||
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_EventSource_Break ((uint16_t)0x0080)
|
||||
|
||||
/* TIM_Update_Source */
|
||||
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
|
||||
or the setting of UG bit, or an update generation \
|
||||
through the slave mode controller. */
|
||||
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
|
||||
|
||||
/* TIM_Output_Compare_Preload_State */
|
||||
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
||||
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_Fast_State */
|
||||
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
||||
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_Clear_State */
|
||||
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
||||
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Trigger_Output_Source */
|
||||
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
||||
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
||||
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
||||
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
||||
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
||||
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
||||
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
||||
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
||||
|
||||
/* TIM_Slave_Mode */
|
||||
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
||||
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
||||
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
||||
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
||||
|
||||
/* TIM_Master_Slave_Mode */
|
||||
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
||||
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Flags */
|
||||
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
||||
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_FLAG_COM ((uint16_t)0x0020)
|
||||
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_FLAG_Break ((uint16_t)0x0080)
|
||||
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
||||
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
||||
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
||||
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
||||
|
||||
/* TIM_Legacy */
|
||||
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
|
||||
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
|
||||
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
|
||||
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
|
||||
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
|
||||
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
|
||||
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
|
||||
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
|
||||
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
|
||||
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
|
||||
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
|
||||
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
|
||||
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
|
||||
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
|
||||
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
|
||||
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
|
||||
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
|
||||
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
|
||||
|
||||
/* TIM_Supersede_Mode_OC1 */
|
||||
#define TIM_Supersede_Mode_OC1_H ((uint16_t)0x0000)
|
||||
#define TIM_Supersede_Mode_OC1_L ((uint16_t)0x0010)
|
||||
|
||||
/* TIM_Supersede_Mode_OC2 */
|
||||
#define TIM_Supersede_Mode_OC2_H ((uint16_t)0x0000)
|
||||
#define TIM_Supersede_Mode_OC2_L ((uint16_t)0x0020)
|
||||
|
||||
/* TIM_Supersede_Mode_OC3 */
|
||||
#define TIM_Supersede_Mode_OC3_H ((uint16_t)0x0000)
|
||||
#define TIM_Supersede_Mode_OC3_L ((uint16_t)0x0040)
|
||||
|
||||
/* TIM_Supersede_Mode_OC4 */
|
||||
#define TIM_Supersede_Mode_OC4_H ((uint16_t)0x0000)
|
||||
#define TIM_Supersede_Mode_OC4_L ((uint16_t)0x0080)
|
||||
|
||||
|
||||
|
||||
void TIM_DeInit(TIM_TypeDef *TIMx);
|
||||
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
|
||||
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
|
||||
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
|
||||
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
||||
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
|
||||
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct);
|
||||
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
||||
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
||||
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource);
|
||||
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
|
||||
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
|
||||
void TIM_InternalClockConfig(TIM_TypeDef *TIMx);
|
||||
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
|
||||
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
||||
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
||||
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode);
|
||||
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
|
||||
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
||||
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
||||
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
|
||||
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
||||
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource);
|
||||
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode);
|
||||
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource);
|
||||
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode);
|
||||
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode);
|
||||
void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter);
|
||||
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload);
|
||||
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1);
|
||||
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2);
|
||||
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3);
|
||||
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4);
|
||||
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD);
|
||||
uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCounter(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx);
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
|
||||
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
|
||||
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
|
||||
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
|
||||
void TIM_CaptureModeCmd(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_IndicateCaptureLevelCmd(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_OC12_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC1, uint16_t TIM_Supersede_Mode_OC2, FunctionalState NewState);
|
||||
void TIM_OC34_SupersedeModeCmd(TIM_TypeDef *TIMx, uint16_t TIM_Supersede_Mode_OC3, uint16_t TIM_Supersede_Mode_OC4, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
185
Peripheral/inc/ch32x035_usart.h
Normal file
185
Peripheral/inc/ch32x035_usart.h
Normal file
|
|
@ -0,0 +1,185 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_usart.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* USART firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_USART_H
|
||||
#define __CH32X035_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* USART Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t USART_Parity; /* Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/* USART Clock Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* USART_Word_Length */
|
||||
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||
|
||||
/* USART_Stop_Bits */
|
||||
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||
|
||||
/* USART_Parity */
|
||||
#define USART_Parity_No ((uint16_t)0x0000)
|
||||
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||
|
||||
/* USART_Mode */
|
||||
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||
|
||||
/* USART_Hardware_Flow_Control */
|
||||
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||
|
||||
/* USART_Clock */
|
||||
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||
|
||||
/* USART_Clock_Polarity */
|
||||
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||
|
||||
/* USART_Clock_Phase */
|
||||
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||
|
||||
/* USART_Last_Bit */
|
||||
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||
|
||||
/* USART_Interrupt_definition */
|
||||
#define USART_IT_PE ((uint16_t)0x0028)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||
#define USART_IT_TC ((uint16_t)0x0626)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||
#define USART_IT_ORE_RX ((uint16_t)0x0325)
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||
#define USART_IT_ORE_ER ((uint16_t)0x0360)
|
||||
#define USART_IT_NE ((uint16_t)0x0260)
|
||||
#define USART_IT_FE ((uint16_t)0x0160)
|
||||
|
||||
#define USART_IT_ORE USART_IT_ORE_ER
|
||||
|
||||
/* USART_DMA_Requests */
|
||||
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||
|
||||
/* USART_WakeUp_methods */
|
||||
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||
|
||||
/* USART_LIN_Break_Detection_Length */
|
||||
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||
|
||||
/* USART_IrDA_Low_Power */
|
||||
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||
|
||||
/* USART_Flags */
|
||||
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||
|
||||
void USART_DeInit(USART_TypeDef *USARTx);
|
||||
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
|
||||
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
|
||||
void USART_SendBreak(USART_TypeDef *USARTx);
|
||||
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
|
||||
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
522
Peripheral/inc/ch32x035_usb.h
Normal file
522
Peripheral/inc/ch32x035_usb.h
Normal file
|
|
@ -0,0 +1,522 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_usb.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the USB
|
||||
* firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_USB_H
|
||||
#define __CH32X035_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Header File */
|
||||
#include "stdint.h"
|
||||
|
||||
/*******************************************************************************/
|
||||
/* USB Communication Related Macro Definition */
|
||||
|
||||
/* USB PID */
|
||||
#ifndef USB_PID_SETUP
|
||||
#define USB_PID_NULL 0x00
|
||||
#define USB_PID_SOF 0x05
|
||||
#define USB_PID_SETUP 0x0D
|
||||
#define USB_PID_IN 0x09
|
||||
#define USB_PID_OUT 0x01
|
||||
#define USB_PID_NYET 0x06
|
||||
#define USB_PID_ACK 0x02
|
||||
#define USB_PID_NAK 0x0A
|
||||
#define USB_PID_STALL 0x0E
|
||||
#define USB_PID_DATA0 0x03
|
||||
#define USB_PID_DATA1 0x0B
|
||||
#define USB_PID_PRE 0x0C
|
||||
#endif
|
||||
|
||||
/* USB standard device request code */
|
||||
#ifndef USB_GET_DESCRIPTOR
|
||||
#define USB_GET_STATUS 0x00
|
||||
#define USB_CLEAR_FEATURE 0x01
|
||||
#define USB_SET_FEATURE 0x03
|
||||
#define USB_SET_ADDRESS 0x05
|
||||
#define USB_GET_DESCRIPTOR 0x06
|
||||
#define USB_SET_DESCRIPTOR 0x07
|
||||
#define USB_GET_CONFIGURATION 0x08
|
||||
#define USB_SET_CONFIGURATION 0x09
|
||||
#define USB_GET_INTERFACE 0x0A
|
||||
#define USB_SET_INTERFACE 0x0B
|
||||
#define USB_SYNCH_FRAME 0x0C
|
||||
#endif
|
||||
|
||||
#define DEF_STRING_DESC_LANG 0x00
|
||||
#define DEF_STRING_DESC_MANU 0x01
|
||||
#define DEF_STRING_DESC_PROD 0x02
|
||||
#define DEF_STRING_DESC_SERN 0x03
|
||||
|
||||
/* USB hub class request code */
|
||||
#ifndef HUB_GET_DESCRIPTOR
|
||||
#define HUB_GET_STATUS 0x00
|
||||
#define HUB_CLEAR_FEATURE 0x01
|
||||
#define HUB_GET_STATE 0x02
|
||||
#define HUB_SET_FEATURE 0x03
|
||||
#define HUB_GET_DESCRIPTOR 0x06
|
||||
#define HUB_SET_DESCRIPTOR 0x07
|
||||
#endif
|
||||
|
||||
/* USB HID class request code */
|
||||
#ifndef HID_GET_REPORT
|
||||
#define HID_GET_REPORT 0x01
|
||||
#define HID_GET_IDLE 0x02
|
||||
#define HID_GET_PROTOCOL 0x03
|
||||
#define HID_SET_REPORT 0x09
|
||||
#define HID_SET_IDLE 0x0A
|
||||
#define HID_SET_PROTOCOL 0x0B
|
||||
#endif
|
||||
|
||||
/* Bit Define for USB Request Type */
|
||||
#ifndef USB_REQ_TYP_MASK
|
||||
#define USB_REQ_TYP_IN 0x80
|
||||
#define USB_REQ_TYP_OUT 0x00
|
||||
#define USB_REQ_TYP_READ 0x80
|
||||
#define USB_REQ_TYP_WRITE 0x00
|
||||
#define USB_REQ_TYP_MASK 0x60
|
||||
#define USB_REQ_TYP_STANDARD 0x00
|
||||
#define USB_REQ_TYP_CLASS 0x20
|
||||
#define USB_REQ_TYP_VENDOR 0x40
|
||||
#define USB_REQ_TYP_RESERVED 0x60
|
||||
#define USB_REQ_RECIP_MASK 0x1F
|
||||
#define USB_REQ_RECIP_DEVICE 0x00
|
||||
#define USB_REQ_RECIP_INTERF 0x01
|
||||
#define USB_REQ_RECIP_ENDP 0x02
|
||||
#define USB_REQ_RECIP_OTHER 0x03
|
||||
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
|
||||
#define USB_REQ_FEAT_ENDP_HALT 0x00
|
||||
#endif
|
||||
|
||||
/* USB Descriptor Type */
|
||||
#ifndef USB_DESCR_TYP_DEVICE
|
||||
#define USB_DESCR_TYP_DEVICE 0x01
|
||||
#define USB_DESCR_TYP_CONFIG 0x02
|
||||
#define USB_DESCR_TYP_STRING 0x03
|
||||
#define USB_DESCR_TYP_INTERF 0x04
|
||||
#define USB_DESCR_TYP_ENDP 0x05
|
||||
#define USB_DESCR_TYP_QUALIF 0x06
|
||||
#define USB_DESCR_TYP_SPEED 0x07
|
||||
#define USB_DESCR_TYP_OTG 0x09
|
||||
#define USB_DESCR_TYP_BOS 0X0F
|
||||
#define USB_DESCR_TYP_HID 0x21
|
||||
#define USB_DESCR_TYP_REPORT 0x22
|
||||
#define USB_DESCR_TYP_PHYSIC 0x23
|
||||
#define USB_DESCR_TYP_CS_INTF 0x24
|
||||
#define USB_DESCR_TYP_CS_ENDP 0x25
|
||||
#define USB_DESCR_TYP_HUB 0x29
|
||||
#endif
|
||||
|
||||
/* USB Device Class */
|
||||
#ifndef USB_DEV_CLASS_HUB
|
||||
#define USB_DEV_CLASS_RESERVED 0x00
|
||||
#define USB_DEV_CLASS_AUDIO 0x01
|
||||
#define USB_DEV_CLASS_COMMUNIC 0x02
|
||||
#define USB_DEV_CLASS_HID 0x03
|
||||
#define USB_DEV_CLASS_MONITOR 0x04
|
||||
#define USB_DEV_CLASS_PHYSIC_IF 0x05
|
||||
#define USB_DEV_CLASS_POWER 0x06
|
||||
#define USB_DEV_CLASS_PRINTER 0x07
|
||||
#define USB_DEV_CLASS_STORAGE 0x08
|
||||
#define USB_DEV_CLASS_HUB 0x09
|
||||
#define USB_DEV_CLASS_VEN_SPEC 0xFF
|
||||
#endif
|
||||
|
||||
/* USB Hub Class Request */
|
||||
#ifndef HUB_GET_HUB_DESCRIPTOR
|
||||
#define HUB_CLEAR_HUB_FEATURE 0x20
|
||||
#define HUB_CLEAR_PORT_FEATURE 0x23
|
||||
#define HUB_GET_BUS_STATE 0xA3
|
||||
#define HUB_GET_HUB_DESCRIPTOR 0xA0
|
||||
#define HUB_GET_HUB_STATUS 0xA0
|
||||
#define HUB_GET_PORT_STATUS 0xA3
|
||||
#define HUB_SET_HUB_DESCRIPTOR 0x20
|
||||
#define HUB_SET_HUB_FEATURE 0x20
|
||||
#define HUB_SET_PORT_FEATURE 0x23
|
||||
#endif
|
||||
|
||||
/* Hub Class Feature Selectors */
|
||||
#ifndef HUB_PORT_RESET
|
||||
#define HUB_C_HUB_LOCAL_POWER 0
|
||||
#define HUB_C_HUB_OVER_CURRENT 1
|
||||
#define HUB_PORT_CONNECTION 0
|
||||
#define HUB_PORT_ENABLE 1
|
||||
#define HUB_PORT_SUSPEND 2
|
||||
#define HUB_PORT_OVER_CURRENT 3
|
||||
#define HUB_PORT_RESET 4
|
||||
#define HUB_PORT_POWER 8
|
||||
#define HUB_PORT_LOW_SPEED 9
|
||||
#define HUB_C_PORT_CONNECTION 16
|
||||
#define HUB_C_PORT_ENABLE 17
|
||||
#define HUB_C_PORT_SUSPEND 18
|
||||
#define HUB_C_PORT_OVER_CURRENT 19
|
||||
#define HUB_C_PORT_RESET 20
|
||||
#endif
|
||||
|
||||
/* USB HID Class Request Code */
|
||||
#ifndef HID_GET_REPORT
|
||||
#define HID_GET_REPORT 0x01
|
||||
#define HID_GET_IDLE 0x02
|
||||
#define HID_GET_PROTOCOL 0x03
|
||||
#define HID_SET_REPORT 0x09
|
||||
#define HID_SET_IDLE 0x0A
|
||||
#define HID_SET_PROTOCOL 0x0B
|
||||
#endif
|
||||
|
||||
/* USB UDisk */
|
||||
#ifndef USB_BO_CBW_SIZE
|
||||
#define USB_BO_CBW_SIZE 0x1F
|
||||
#define USB_BO_CSW_SIZE 0x0D
|
||||
#endif
|
||||
#ifndef USB_BO_CBW_SIG0
|
||||
#define USB_BO_CBW_SIG0 0x55
|
||||
#define USB_BO_CBW_SIG1 0x53
|
||||
#define USB_BO_CBW_SIG2 0x42
|
||||
#define USB_BO_CBW_SIG3 0x43
|
||||
#define USB_BO_CSW_SIG0 0x55
|
||||
#define USB_BO_CSW_SIG1 0x53
|
||||
#define USB_BO_CSW_SIG2 0x42
|
||||
#define USB_BO_CSW_SIG3 0x53
|
||||
#endif
|
||||
|
||||
/* USB CDC Class request code */
|
||||
#ifndef CDC_GET_LINE_CODING
|
||||
#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */
|
||||
#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
|
||||
#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */
|
||||
#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */
|
||||
#endif
|
||||
/*******************************************************************************/
|
||||
/* USBFS Related Register Macro Definition */
|
||||
|
||||
/* R8_USB_CTRL */
|
||||
#define USBFS_UC_HOST_MODE 0x80
|
||||
#define USBFS_UC_LOW_SPEED 0x40
|
||||
#define USBFS_UC_DEV_PU_EN 0x20
|
||||
#define USBFS_UC_SYS_CTRL_MASK 0x30
|
||||
#define USBFS_UC_SYS_CTRL0 0x00
|
||||
#define USBFS_UC_SYS_CTRL1 0x10
|
||||
#define USBFS_UC_SYS_CTRL2 0x20
|
||||
#define USBFS_UC_SYS_CTRL3 0x30
|
||||
#define USBFS_UC_INT_BUSY 0x08
|
||||
#define USBFS_UC_RESET_SIE 0x04
|
||||
#define USBFS_UC_CLR_ALL 0x02
|
||||
#define USBFS_UC_DMA_EN 0x01
|
||||
|
||||
/* R8_USB_INT_EN */
|
||||
#define USBFS_UIE_DEV_SOF 0x80
|
||||
#define USBFS_UIE_DEV_NAK 0x40
|
||||
#define USBFS_UIE_FIFO_OV 0x10
|
||||
#define USBFS_UIE_HST_SOF 0x08
|
||||
#define USBFS_UIE_SUSPEND 0x04
|
||||
#define USBFS_UIE_TRANSFER 0x02
|
||||
#define USBFS_UIE_DETECT 0x01
|
||||
#define USBFS_UIE_BUS_RST 0x01
|
||||
|
||||
/* R8_USB_DEV_AD */
|
||||
#define USBFS_UDA_GP_BIT 0x80
|
||||
#define USBFS_USB_ADDR_MASK 0x7F
|
||||
|
||||
/* R8_USB_MIS_ST */
|
||||
#define USBFS_UMS_SOF_PRES 0x80
|
||||
#define USBFS_UMS_SOF_ACT 0x40
|
||||
#define USBFS_UMS_SIE_FREE 0x20
|
||||
#define USBFS_UMS_R_FIFO_RDY 0x10
|
||||
#define USBFS_UMS_BUS_RESET 0x08
|
||||
#define USBFS_UMS_SUSPEND 0x04
|
||||
#define USBFS_UMS_DM_LEVEL 0x02
|
||||
#define USBFS_UMS_DEV_ATTACH 0x01
|
||||
|
||||
/* R8_USB_INT_FG */
|
||||
#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
|
||||
#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||
#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
|
||||
#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
|
||||
#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
|
||||
|
||||
/* R8_USB_INT_ST */
|
||||
#define USBFS_SETUP_ACT 0x80 // RO, indicate current USB transfer SETUP is complete
|
||||
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
|
||||
#define USBFS_UIS_TOKEN_OUT 0x00
|
||||
#define USBFS_UIS_TOKEN_SOF 0x10
|
||||
#define USBFS_UIS_TOKEN_IN 0x20
|
||||
#define USBFS_UIS_TOKEN_SETUP 0x30
|
||||
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
|
||||
// 00: OUT token PID received
|
||||
// 01: SOF token PID received
|
||||
// 10: IN token PID received
|
||||
// 11: SETUP token PID received
|
||||
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
|
||||
#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
|
||||
|
||||
/* R8_UDEV_CTRL */
|
||||
#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||
#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||
#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||
#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
|
||||
#define USBFS_UD_GP_BIT 0x02 // general purpose bit
|
||||
#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
|
||||
|
||||
/* R8_UEP4_1_MOD */
|
||||
#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
|
||||
#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
|
||||
#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
|
||||
// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
|
||||
// 0 0 x: disable endpoint and disable buffer
|
||||
// 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
|
||||
// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
|
||||
// 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
|
||||
// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
|
||||
// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
|
||||
// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
|
||||
#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
|
||||
#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
|
||||
// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
|
||||
// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
||||
// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
|
||||
// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
|
||||
// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
|
||||
// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
|
||||
#define USBFS_UEP4_BUF_MOD 0x01
|
||||
|
||||
/* R8_UEP2_3_MOD */
|
||||
#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
|
||||
#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
|
||||
#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
|
||||
#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
|
||||
#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
|
||||
#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
|
||||
|
||||
/* R8_UEP567_MOD */
|
||||
|
||||
#define USBFS_UEP5_RX_EN 0x02 // enable USB endpoint 5 receiving (OUT)
|
||||
#define USBFS_UEP5_TX_EN 0x01 // enable USB endpoint 5 transmittal (IN)
|
||||
#define USBFS_UEP6_RX_EN 0x08 // enable USB endpoint 6 receiving (OUT)
|
||||
#define USBFS_UEP6_TX_EN 0x04 // enable USB endpoint 6 transmittal (IN)
|
||||
#define USBFS_UEP7_RX_EN 0x20 // enable USB endpoint 7 receiving (OUT)
|
||||
#define USBFS_UEP7_TX_EN 0x10 // enable USB endpoint 7 transmittal (IN)
|
||||
|
||||
/* R8_UEPn_TX_CTRL */
|
||||
#define USBFS_UEP_T_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UEP_T_TOG (1<<6) // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UEP_T_RES_MASK (3<<0) // bit mask of handshake response type for USB endpoint X transmittal (IN)
|
||||
#define USBFS_UEP_T_RES_ACK (0<<1)
|
||||
#define USBFS_UEP_T_RES_NONE (1<<0)
|
||||
#define USBFS_UEP_T_RES_NAK (1<<1)
|
||||
#define USBFS_UEP_T_RES_STALL (3<<0)
|
||||
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
|
||||
// 00: DATA0 or DATA1 then expecting ACK (ready)
|
||||
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
|
||||
// 10: NAK (busy)
|
||||
// 11: STALL (error)
|
||||
// host aux setup
|
||||
|
||||
/* R8_UEPn_RX_CTRL, n=0-7 */
|
||||
#define USBFS_UEP_R_AUTO_TOG (1<<4) // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UEP_R_TOG (1<<7) // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UEP_R_RES_MASK (3<<2) // bit mask of handshake response type for USB endpoint X receiving (OUT)
|
||||
#define USBFS_UEP_R_RES_ACK (0<<3)
|
||||
#define USBFS_UEP_R_RES_NONE (1<<2)
|
||||
#define USBFS_UEP_R_RES_NAK (1<<3)
|
||||
#define USBFS_UEP_R_RES_STALL (3<<2)
|
||||
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
|
||||
// 00: ACK (ready)
|
||||
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
|
||||
// 10: NAK (busy)
|
||||
// 11: STALL (error)
|
||||
|
||||
/* R8_UHOST_CTRL */
|
||||
#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||
#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||
#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||
#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
|
||||
#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
|
||||
#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
|
||||
|
||||
/* R32_UH_EP_MOD */
|
||||
#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
|
||||
#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
|
||||
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
|
||||
// 0 x: disable endpoint and disable buffer
|
||||
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
|
||||
#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
|
||||
#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
|
||||
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
|
||||
// 0 x: disable endpoint and disable buffer
|
||||
// 1 0: 64 bytes buffer for receiving (IN endpoint)
|
||||
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
|
||||
|
||||
/* R8_UH_SETUP */
|
||||
#define USBFS_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub
|
||||
#define USBFS_UH_SOF_EN 0x40 // USB host automatic SOF enable
|
||||
|
||||
/* R8_UH_EP_PID */
|
||||
#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer
|
||||
#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer
|
||||
|
||||
/* R8_UH_RX_CTRL */
|
||||
#define USBFS_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UH_R_TOG (1<<7) // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
|
||||
|
||||
/* R8_UH_TX_CTRL */
|
||||
#define USBFS_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||
#define USBFS_UH_T_TOG (1<<6) // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
|
||||
#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
|
||||
|
||||
|
||||
/*******************************************************************************/
|
||||
/* Struct Definition */
|
||||
|
||||
/* USB Setup Request */
|
||||
typedef struct __attribute__((packed)) _USB_SETUP_REQ
|
||||
{
|
||||
uint8_t bRequestType;
|
||||
uint8_t bRequest;
|
||||
uint16_t wValue;
|
||||
uint16_t wIndex;
|
||||
uint16_t wLength;
|
||||
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
|
||||
|
||||
/* USB Device Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdUSB;
|
||||
uint8_t bDeviceClass;
|
||||
uint8_t bDeviceSubClass;
|
||||
uint8_t bDeviceProtocol;
|
||||
uint8_t bMaxPacketSize0;
|
||||
uint16_t idVendor;
|
||||
uint16_t idProduct;
|
||||
uint16_t bcdDevice;
|
||||
uint8_t iManufacturer;
|
||||
uint8_t iProduct;
|
||||
uint8_t iSerialNumber;
|
||||
uint8_t bNumConfigurations;
|
||||
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
|
||||
|
||||
/* USB Configuration Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t wTotalLength;
|
||||
uint8_t bNumInterfaces;
|
||||
uint8_t bConfigurationValue;
|
||||
uint8_t iConfiguration;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t MaxPower;
|
||||
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
|
||||
|
||||
/* USB Interface Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bInterfaceNumber;
|
||||
uint8_t bAlternateSetting;
|
||||
uint8_t bNumEndpoints;
|
||||
uint8_t bInterfaceClass;
|
||||
uint8_t bInterfaceSubClass;
|
||||
uint8_t bInterfaceProtocol;
|
||||
uint8_t iInterface;
|
||||
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
|
||||
|
||||
/* USB Endpoint Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bEndpointAddress;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t wMaxPacketSizeL;
|
||||
uint8_t wMaxPacketSizeH;
|
||||
uint8_t bInterval;
|
||||
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
|
||||
|
||||
/* USB Configuration Descriptor Set */
|
||||
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
|
||||
{
|
||||
USB_CFG_DESCR cfg_descr;
|
||||
USB_ITF_DESCR itf_descr;
|
||||
USB_ENDP_DESCR endp_descr[ 1 ];
|
||||
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
|
||||
|
||||
/* USB HUB Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_HUB_DESCR
|
||||
{
|
||||
uint8_t bDescLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bNbrPorts;
|
||||
uint8_t wHubCharacteristicsL;
|
||||
uint8_t wHubCharacteristicsH;
|
||||
uint8_t bPwrOn2PwrGood;
|
||||
uint8_t bHubContrCurrent;
|
||||
uint8_t DeviceRemovable;
|
||||
uint8_t PortPwrCtrlMask;
|
||||
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
|
||||
|
||||
/* USB HID Descriptor */
|
||||
typedef struct __attribute__((packed)) _USB_HID_DESCR
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdHID;
|
||||
uint8_t bCountryCode;
|
||||
uint8_t bNumDescriptors;
|
||||
uint8_t bDescriptorTypeX;
|
||||
uint8_t wDescriptorLengthL;
|
||||
uint8_t wDescriptorLengthH;
|
||||
} USB_HID_DESCR, *PUSB_HID_DESCR;
|
||||
|
||||
/* USB UDisk */
|
||||
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
|
||||
{
|
||||
uint32_t mCBW_Sig;
|
||||
uint32_t mCBW_Tag;
|
||||
uint32_t mCBW_DataLen;
|
||||
uint8_t mCBW_Flag;
|
||||
uint8_t mCBW_LUN;
|
||||
uint8_t mCBW_CB_Len;
|
||||
uint8_t mCBW_CB_Buf[ 16 ];
|
||||
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
|
||||
|
||||
/* USB UDisk */
|
||||
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
|
||||
{
|
||||
uint32_t mCBW_Sig;
|
||||
uint32_t mCBW_Tag;
|
||||
uint32_t mCSW_Residue;
|
||||
uint8_t mCSW_Status;
|
||||
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32X035_USB_H */
|
||||
412
Peripheral/inc/ch32x035_usbpd.h
Normal file
412
Peripheral/inc/ch32x035_usbpd.h
Normal file
|
|
@ -0,0 +1,412 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_usbpd.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the USBPD
|
||||
* firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_USBPD_H
|
||||
#define __CH32X035_USBPD_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
#ifndef VOID
|
||||
#define VOID void
|
||||
#endif
|
||||
#ifndef CONST
|
||||
#define CONST const
|
||||
#endif
|
||||
#ifndef BOOL
|
||||
typedef unsigned char BOOL;
|
||||
#endif
|
||||
#ifndef BOOLEAN
|
||||
typedef unsigned char BOOLEAN;
|
||||
#endif
|
||||
#ifndef CHAR
|
||||
typedef char CHAR;
|
||||
#endif
|
||||
#ifndef INT8
|
||||
typedef char INT8;
|
||||
#endif
|
||||
#ifndef INT16
|
||||
typedef short INT16;
|
||||
#endif
|
||||
#ifndef INT32
|
||||
typedef long INT32;
|
||||
#endif
|
||||
#ifndef UINT8
|
||||
typedef unsigned char UINT8;
|
||||
#endif
|
||||
#ifndef UINT16
|
||||
typedef unsigned short UINT16;
|
||||
#endif
|
||||
#ifndef UINT32
|
||||
typedef unsigned long UINT32;
|
||||
#endif
|
||||
#ifndef UINT8V
|
||||
typedef unsigned char volatile UINT8V;
|
||||
#endif
|
||||
#ifndef UINT16V
|
||||
typedef unsigned short volatile UINT16V;
|
||||
#endif
|
||||
#ifndef UINT32V
|
||||
typedef unsigned long volatile UINT32V;
|
||||
#endif
|
||||
|
||||
#ifndef PVOID
|
||||
typedef void *PVOID;
|
||||
#endif
|
||||
#ifndef PCHAR
|
||||
typedef char *PCHAR;
|
||||
#endif
|
||||
#ifndef PCHAR
|
||||
typedef const char *PCCHAR;
|
||||
#endif
|
||||
#ifndef PINT8
|
||||
typedef char *PINT8;
|
||||
#endif
|
||||
#ifndef PINT16
|
||||
typedef short *PINT16;
|
||||
#endif
|
||||
#ifndef PINT32
|
||||
typedef long *PINT32;
|
||||
#endif
|
||||
#ifndef PUINT8
|
||||
typedef unsigned char *PUINT8;
|
||||
#endif
|
||||
#ifndef PUINT16
|
||||
typedef unsigned short *PUINT16;
|
||||
#endif
|
||||
#ifndef PUINT32
|
||||
typedef unsigned long *PUINT32;
|
||||
#endif
|
||||
#ifndef PUINT8V
|
||||
typedef volatile unsigned char *PUINT8V;
|
||||
#endif
|
||||
#ifndef PUINT16V
|
||||
typedef volatile unsigned short *PUINT16V;
|
||||
#endif
|
||||
#ifndef PUINT32V
|
||||
typedef volatile unsigned long *PUINT32V;
|
||||
#endif
|
||||
|
||||
/******************************************************************************/
|
||||
/* Related macro definitions */
|
||||
|
||||
/* Define the return value of the function */
|
||||
#ifndef SUCCESS
|
||||
#define SUCCESS 0
|
||||
#endif
|
||||
#ifndef FAIL
|
||||
#define FAIL 0xFF
|
||||
#endif
|
||||
|
||||
/* Register Bit Definition */
|
||||
/* USBPD->CONFIG */
|
||||
#define PD_FILT_ED (1<<0) /* PD pin input filter enable */
|
||||
#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */
|
||||
#define CC_SEL (1<<2) /* Select PD communication port */
|
||||
#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */
|
||||
#define PD_RST_EN (1<<4) /* PD mode reset command enable */
|
||||
#define WAKE_POLAR (1<<5) /* PD port wake-up level */
|
||||
#define IE_PD_IO (1<<10) /* PD IO interrupt enable */
|
||||
#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */
|
||||
#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */
|
||||
#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */
|
||||
#define IE_RX_RESET (1<<14) /* Reset interrupt enable */
|
||||
#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */
|
||||
|
||||
/* USBPD->CONTROL */
|
||||
#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */
|
||||
#define BMC_START (1<<1) /* BMC send start signal */
|
||||
#define RX_STATE_0 (1<<2) /* PD received state bit 0 */
|
||||
#define RX_STATE_1 (1<<3) /* PD received state bit 1 */
|
||||
#define RX_STATE_2 (1<<4) /* PD received state bit 2 */
|
||||
#define DATA_FLAG (1<<5) /* Cache data valid flag bit */
|
||||
#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */
|
||||
#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */
|
||||
|
||||
/* USBPD->TX_SEL */
|
||||
#define TX_SEL1 (0<<0)
|
||||
#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */
|
||||
#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */
|
||||
#define TX_SEL2_Mask (3<<2)
|
||||
#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */
|
||||
#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */
|
||||
#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */
|
||||
#define TX_SEL3_Mask (3<<4)
|
||||
#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */
|
||||
#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */
|
||||
#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */
|
||||
#define TX_SEL4_Mask (3<<6)
|
||||
#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */
|
||||
#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */
|
||||
#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */
|
||||
|
||||
/* USBPD->STATUS */
|
||||
#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */
|
||||
#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */
|
||||
#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */
|
||||
#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */
|
||||
#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */
|
||||
#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */
|
||||
#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */
|
||||
#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */
|
||||
#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */
|
||||
#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */
|
||||
#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */
|
||||
|
||||
/* USBPD->PORT_CC1 */
|
||||
/* USBPD->PORT_CC2 */
|
||||
#define PA_CC_AI (1<<0) /* CC port comparator analogue input */
|
||||
#define CC_PD (1<<1) /* CC port pull-down resistor enable */
|
||||
#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */
|
||||
#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */
|
||||
#define CC_PU_330 (1<<2) /* 01-330uA */
|
||||
#define CC_PU_180 (2<<2) /* 10-180uA */
|
||||
#define CC_PU_80 (3<<2) /* 11-80uA */
|
||||
#define CC_LVE (1<<4) /* CC port output low voltage enable */
|
||||
#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/
|
||||
#define CC_NO_CMP (0<<5) /* 000-closed */
|
||||
#define CC_CMP_22 (2<<5) /* 010-0.22V */
|
||||
#define CC_CMP_45 (3<<5) /* 011-0.45V */
|
||||
#define CC_CMP_55 (4<<5) /* 100-0.55V */
|
||||
#define CC_CMP_66 (5<<5) /* 101-0.66V */
|
||||
#define CC_CMP_95 (6<<5) /* 110-0.95V */
|
||||
#define CC_CMP_123 (7<<5) /* 111-1.23V */
|
||||
#define USBPD_IN_HVT (1<<9)
|
||||
/*********************************************************
|
||||
* PD pin PC14/PC15 high threshold input mode:
|
||||
* 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication
|
||||
* 0-Normal GPIO threshold input
|
||||
* *******************************************************/
|
||||
#define USBPD_PHY_V33 (1<<8)
|
||||
/**********************************************************
|
||||
* PD transceiver PHY pull-up limit configuration bits:
|
||||
* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V
|
||||
* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V
|
||||
* ********************************************************/
|
||||
|
||||
/* Control Message Types */
|
||||
#define DEF_TYPE_RESERVED 0x00
|
||||
#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */
|
||||
#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_PING 0x05 /* Send By: Source */
|
||||
#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */
|
||||
#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */
|
||||
#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */
|
||||
#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */
|
||||
#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */
|
||||
#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */
|
||||
#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */
|
||||
#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */
|
||||
#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */
|
||||
|
||||
/* Data Message Types */
|
||||
#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */
|
||||
#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */
|
||||
#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */
|
||||
#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */
|
||||
#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */
|
||||
#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */
|
||||
#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */
|
||||
#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */
|
||||
#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */
|
||||
#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */
|
||||
|
||||
/* Vendor Define Message Command */
|
||||
#define DEF_VDM_DISC_IDENT 0x01
|
||||
#define DEF_VDM_DISC_SVID 0x02
|
||||
#define DEF_VDM_DISC_MODE 0x03
|
||||
#define DEF_VDM_ENTER_MODE 0x04
|
||||
#define DEF_VDM_EXIT_MODE 0x05
|
||||
#define DEF_VDM_ATTENTION 0x06
|
||||
#define DEF_VDM_DP_S_UPDATE 0x10
|
||||
#define DEF_VDM_DP_CONFIG 0x11
|
||||
|
||||
/* PD Revision */
|
||||
#define DEF_PD_REVISION_10 0x00
|
||||
#define DEF_PD_REVISION_20 0x01
|
||||
#define DEF_PD_REVISION_30 0x02
|
||||
|
||||
|
||||
/* PD PHY Channel */
|
||||
#define DEF_PD_CC1 0x00
|
||||
#define DEF_PD_CC2 0x01
|
||||
|
||||
#define PIN_CC1 GPIO_Pin_14
|
||||
#define PIN_CC2 GPIO_Pin_15
|
||||
|
||||
/* PD Tx Status */
|
||||
#define DEF_PD_TX_OK 0x00
|
||||
#define DEF_PD_TX_FAIL 0x01
|
||||
|
||||
/* PDO INDEX */
|
||||
#define PDO_INDEX_1 1
|
||||
#define PDO_INDEX_2 2
|
||||
#define PDO_INDEX_3 3
|
||||
#define PDO_INDEX_4 4
|
||||
#define PDO_INDEX_5 5
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */
|
||||
#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */
|
||||
#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */
|
||||
#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */
|
||||
#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */
|
||||
#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */
|
||||
|
||||
#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */
|
||||
#define PD_RX_SOP0 0x01 /* SOP0 received */
|
||||
#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */
|
||||
#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */
|
||||
|
||||
#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */
|
||||
#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */
|
||||
#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */
|
||||
#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/
|
||||
#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/
|
||||
|
||||
|
||||
#define bCC_CMP_22 0X01
|
||||
#define bCC_CMP_45 0X02
|
||||
#define bCC_CMP_55 0X04
|
||||
#define bCC_CMP_66 0X08
|
||||
#define bCC_CMP_95 0X10
|
||||
#define bCC_CMP_123 0X20
|
||||
#define bCC_CMP_220 0X40
|
||||
|
||||
/******************************************************************************/
|
||||
/* PD State Machine */
|
||||
typedef enum
|
||||
{
|
||||
STA_IDLE = 0, /* 0: No task status */
|
||||
STA_DISCONNECT, /* 1: Disconnection */
|
||||
STA_SRC_CONNECT, /* 2: SRC connect */
|
||||
STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */
|
||||
STA_RX_SRC_CAP, /* 4: SRC_CAP received */
|
||||
STA_TX_REQ, /* 5: Send REQUEST */
|
||||
STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */
|
||||
STA_RX_ACCEPT, /* 7: ACCEPT received */
|
||||
STA_RX_REJECT, /* 8: REJECT received */
|
||||
STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */
|
||||
STA_RX_PS_RDY, /* 10: PS_RDY received */
|
||||
STA_SINK_CONNECT, /* 11: SNK access */
|
||||
STA_TX_SRC_CAP, /* 12: Send SRC_CAP */
|
||||
STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */
|
||||
STA_RX_REQ, /* 14: REQUEST received */
|
||||
STA_TX_ACCEPT, /* 15: Send ACCEPT */
|
||||
STA_TX_REJECT, /* 16: Send REJECT */
|
||||
STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */
|
||||
STA_TX_PS_RDY, /* 18: Send PS_RDY */
|
||||
STA_TX_DR_SWAP, /* 19: Send DR_SWAP */
|
||||
STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */
|
||||
STA_TX_PR_SWAP, /* 21: Send PR_SWAP */
|
||||
STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */
|
||||
STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */
|
||||
STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */
|
||||
STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */
|
||||
STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */
|
||||
STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */
|
||||
STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */
|
||||
STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */
|
||||
STA_MODE_SWITCH, /* 30: Mode switching */
|
||||
STA_TX_SOFTRST, /* 31: Sending a software reset */
|
||||
STA_TX_HRST, /* 32: Send hardware reset */
|
||||
STA_PHY_RST, /* 33: PHY reset */
|
||||
STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */
|
||||
} CC_STATUS;
|
||||
|
||||
/******************************************************************************/
|
||||
/* PD Message Header Struct */
|
||||
typedef union
|
||||
{
|
||||
struct _Message_Header
|
||||
{
|
||||
UINT8 MsgType: 5; /* Message Type */
|
||||
UINT8 PDRole: 1; /* 0-UFP; 1-DFP */
|
||||
UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */
|
||||
UINT8 PRRole: 1; /* 0-Sink; 1-Source */
|
||||
UINT8 MsgID: 3;
|
||||
UINT8 NumDO: 3;
|
||||
UINT8 Ext: 1;
|
||||
}Message_Header;
|
||||
UINT16 Data;
|
||||
}_Message_Header;
|
||||
|
||||
/******************************************************************************/
|
||||
/* Bit definition */
|
||||
typedef union
|
||||
{
|
||||
struct _BITS_
|
||||
{
|
||||
UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */
|
||||
UINT8 Connected: 1; /* PD Physical Layer Connected Flag */
|
||||
UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */
|
||||
UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */
|
||||
UINT8 PR_Role: 1; /* 0-Sink; 1-Source */
|
||||
UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */
|
||||
UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */
|
||||
UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */
|
||||
UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */
|
||||
UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */
|
||||
UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */
|
||||
UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */
|
||||
UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */
|
||||
UINT8 Recv: 3;
|
||||
}Bit;
|
||||
UINT16 Bit_Flag;
|
||||
}_BIT_FLAG;
|
||||
|
||||
/* PD control-related structures */
|
||||
typedef struct _PD_CONTROL
|
||||
{
|
||||
CC_STATUS PD_State; /* PD communication status machine */
|
||||
CC_STATUS PD_State_Last; /* PD communication status machine (last value) */
|
||||
UINT8 Msg_ID; /* ID of the message sent */
|
||||
UINT8 Det_Timer; /* PD connection status detection timing */
|
||||
UINT8 Det_Cnt; /* Number of PD connection status detections */
|
||||
UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */
|
||||
UINT8 HPD_Det_Timer; /* HPD connection detection timing */
|
||||
UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */
|
||||
UINT16 PD_Comm_Timer; /* PD shared timing variables */
|
||||
UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */
|
||||
UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */
|
||||
UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */
|
||||
UINT8 Err_Op_Cnt; /* Exception operation count */
|
||||
UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */
|
||||
_BIT_FLAG Flag; /* Flag byte bit definition */
|
||||
}PD_CONTROL, *pPD_CONTROL;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
41
Peripheral/inc/ch32x035_wwdg.h
Normal file
41
Peripheral/inc/ch32x035_wwdg.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_wwdg.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains all the functions prototypes for the WWDG
|
||||
* firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_WWDG_H
|
||||
#define __CH32X035_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32x035.h"
|
||||
|
||||
/* WWDG_Prescaler */
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
|
||||
void WWDG_DeInit(void);
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
1125
Peripheral/src/ch32x035_adc.c
Normal file
1125
Peripheral/src/ch32x035_adc.c
Normal file
File diff suppressed because it is too large
Load diff
92
Peripheral/src/ch32x035_awu.c
Normal file
92
Peripheral/src/ch32x035_awu.c
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_awu.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the AWU firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_awu.h"
|
||||
|
||||
/* PSC registers bit mask */
|
||||
#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0)
|
||||
|
||||
/* WR register bit mask */
|
||||
#define AWUWR_MASK ((uint32_t)0xFFFFFFC0)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn AutoWakeUpCmd
|
||||
*
|
||||
* @brief Enables or disables the Auto WakeUp functionality.
|
||||
*
|
||||
* @param NewState - new state of the Auto WakeUp functionality
|
||||
* (ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void AutoWakeUpCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
AWU->CSR |= (1 << 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
AWU->CSR &= ~(1 << 1);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn AWU_SetPrescaler
|
||||
*
|
||||
* @brief Sets the Auto Wake up Prescaler
|
||||
*
|
||||
* @param AWU_Prescaler - specifies the Auto Wake up Prescaler
|
||||
* AWU_Prescaler_1 - AWU counter clock = LSI/1
|
||||
* AWU_Prescaler_2 - AWU counter clock = LSI/2
|
||||
* AWU_Prescaler_4 - AWU counter clock = LSI/4
|
||||
* AWU_Prescaler_8 - AWU counter clock = LSI/8
|
||||
* AWU_Prescaler_16 - AWU counter clock = LSI/16
|
||||
* AWU_Prescaler_32 - AWU counter clock = LSI/32
|
||||
* AWU_Prescaler_64 - AWU counter clock = LSI/64
|
||||
* AWU_Prescaler_128 - AWU counter clock = LSI/128
|
||||
* AWU_Prescaler_256 - AWU counter clock = LSI/256
|
||||
* AWU_Prescaler_512 - AWU counter clock = LSI/512
|
||||
* AWU_Prescaler_1024 - AWU counter clock = LSI/1024
|
||||
* AWU_Prescaler_2048 - AWU counter clock = LSI/2048
|
||||
* AWU_Prescaler_4096 - AWU counter clock = LSI/4096
|
||||
* AWU_Prescaler_10240 - AWU counter clock = LSI/10240
|
||||
* AWU_Prescaler_61440 - AWU counter clock = LSI/61440
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void AWU_SetPrescaler(uint32_t AWU_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = AWU->PSC & AWUPSC_MASK;
|
||||
tmpreg |= AWU_Prescaler;
|
||||
AWU->PSC = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn AWU_SetWindowValue
|
||||
*
|
||||
* @brief Sets the WWDG window value
|
||||
*
|
||||
* @param WindowValue - specifies the window value to be compared to the
|
||||
* downcounter,which must be lower than 0x3F
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void AWU_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = AWU->WR & AWUWR_MASK;
|
||||
tmpreg |= WindowValue;
|
||||
|
||||
AWU->WR = tmpreg;
|
||||
}
|
||||
120
Peripheral/src/ch32x035_dbgmcu.c
Normal file
120
Peripheral/src/ch32x035_dbgmcu.c
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_dbgmcu.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the DBGMCU firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_dbgmcu.h"
|
||||
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_GetREVID
|
||||
*
|
||||
* @brief Returns the device revision identifier.
|
||||
*
|
||||
* @return Revision identifier.
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return ((*(uint32_t *)0x1FFFF704) >> 16);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_GetDEVID
|
||||
*
|
||||
* @brief Returns the device identifier.
|
||||
*
|
||||
* @return Device identifier.
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_DEBUG_CR
|
||||
*
|
||||
* @brief Return the DEBUGE Control Register
|
||||
*
|
||||
* @return DEBUGE Control value
|
||||
*/
|
||||
uint32_t __get_DEBUG_CR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile("csrr %0,""0x7C0" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_DEBUG_CR
|
||||
*
|
||||
* @brief Set the DEBUGE Control Register
|
||||
*
|
||||
* @param value - set DEBUGE Control value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_DEBUG_CR(uint32_t value)
|
||||
{
|
||||
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_Config
|
||||
*
|
||||
* @brief Configures the specified peripheral and low power mode behavior
|
||||
* when the MCU under Debug mode.
|
||||
*
|
||||
* @param DBGMCU_Periph - specifies the peripheral and low power mode.
|
||||
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
|
||||
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
|
||||
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
|
||||
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
|
||||
* DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
__set_DEBUG_CR(DBGMCU_Periph);
|
||||
}
|
||||
else
|
||||
{
|
||||
val = __get_DEBUG_CR();
|
||||
val &= ~(uint32_t)DBGMCU_Periph;
|
||||
__set_DEBUG_CR(val);
|
||||
}
|
||||
|
||||
}
|
||||
/*********************************************************************
|
||||
* @fn DBGMCU_GetCHIPID
|
||||
*
|
||||
* @brief Returns the CHIP identifier.
|
||||
*
|
||||
* @return Device identifier.
|
||||
* ChipID List-
|
||||
* CH32X035R8T6-0x035006x1
|
||||
* CH32X035C8T6-0x035106x1
|
||||
* CH32X035F8U6-0x035E06x1
|
||||
* CH32X035G8U6-0x035606x1
|
||||
* CH32X035G8R6-0x035B06x1
|
||||
* CH32X035F7P6-0x035706x1
|
||||
* CH32X033F8P6-0x035A06x1
|
||||
*/
|
||||
uint32_t DBGMCU_GetCHIPID( void )
|
||||
{
|
||||
return( *( uint32_t * )0x1FFFF704 );
|
||||
}
|
||||
432
Peripheral/src/ch32x035_dma.c
Normal file
432
Peripheral/src/ch32x035_dma.c
Normal file
|
|
@ -0,0 +1,432 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_dma.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the DMA firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_dma.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
|
||||
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
|
||||
#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
|
||||
|
||||
/* DMA2 FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_DeInit
|
||||
*
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
|
||||
* 1 to 8 for DMA1 to select the DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||
{
|
||||
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||
DMAy_Channelx->CFGR = 0;
|
||||
DMAy_Channelx->CNTR = 0;
|
||||
DMAy_Channelx->PADDR = 0;
|
||||
DMAy_Channelx->MADDR = 0;
|
||||
if(DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel8)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel8_IT_Mask;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_Init
|
||||
*
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitStruct.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
|
||||
* 1 to 8 for DMA1 to select the DMA Channel.
|
||||
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = DMAy_Channelx->CFGR;
|
||||
tmpreg &= CFGR_CLEAR_Mask;
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
DMAy_Channelx->CFGR = tmpreg;
|
||||
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
|
||||
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_StructInit
|
||||
*
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
|
||||
* 1 to 8 for DMA1 to select the DMA Channel.
|
||||
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
|
||||
* 1 to 8 for DMA1 to select the DMA Channel.
|
||||
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
|
||||
* 1 to 8 for DMA1 to select the DMA Channel.
|
||||
* DMA_IT - specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* DMA_IT_TC - Transfer complete interrupt mask
|
||||
* DMA_IT_HT - Half transfer interrupt mask
|
||||
* DMA_IT_TE - Transfer error interrupt mask
|
||||
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
DMAy_Channelx->CFGR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMAy_Channelx->CFGR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_SetCurrDataCounter
|
||||
*
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
|
||||
* 1 to 8 for DMA1 to select the DMA Channel.
|
||||
* DataNumber - The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
DMAy_Channelx->CNTR = DataNumber;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetCurrDataCounter
|
||||
*
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
|
||||
* 1 to 8 for DMA1 to select the DMA Channel.
|
||||
*
|
||||
* @return DataNumber - The number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||
{
|
||||
return ((uint16_t)(DMAy_Channelx->CNTR));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
*
|
||||
* @param DMAy_FLAG - specifies the flag to check.
|
||||
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA1_FLAG_GL8 - DMA1 Channel8 global flag.
|
||||
* DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag.
|
||||
* DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag.
|
||||
* DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag.
|
||||
|
||||
* @return The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = DMA1->INTFR;
|
||||
|
||||
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ClearFlag
|
||||
*
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
*
|
||||
* @param DMAy_FLAG - specifies the flag to check.
|
||||
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA1_FLAG_GL8 - DMA1 Channel8 global flag.
|
||||
* DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag.
|
||||
* DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag.
|
||||
* DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag.
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
DMA1->INTFCR = DMAy_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has
|
||||
* occurred or not.
|
||||
*
|
||||
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA1_IT_GL8 - DMA1 Channel8 global flag.
|
||||
* DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag.
|
||||
* DMA1_IT_HT8 - DMA1 Channel8 half transfer flag.
|
||||
* DMA1_IT_TE8 - DMA1 Channel8 transfer error flag.
|
||||
* @return The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = DMA1->INTFR;
|
||||
|
||||
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
*
|
||||
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA1_IT_GL8 - DMA1 Channel8 global flag.
|
||||
* DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag.
|
||||
* DMA1_IT_HT8 - DMA1 Channel8 half transfer flag.
|
||||
* DMA1_IT_TE8 - DMA1 Channel8 transfer error flag.
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
DMA1->INTFCR = DMAy_IT;
|
||||
}
|
||||
182
Peripheral/src/ch32x035_exti.c
Normal file
182
Peripheral/src/ch32x035_exti.c
Normal file
|
|
@ -0,0 +1,182 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_exti.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the EXTI firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_exti.h"
|
||||
|
||||
/* No interrupt selected */
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_DeInit
|
||||
*
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->INTENR = 0x00000000;
|
||||
EXTI->EVENR = 0x00000000;
|
||||
EXTI->RTENR = 0x00000000;
|
||||
EXTI->FTENR = 0x00000000;
|
||||
EXTI->INTFR = 0x000FFFFF;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_Init
|
||||
*
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
*
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_StructInit
|
||||
*
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
*
|
||||
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_GenerateSWInterrupt
|
||||
*
|
||||
* @brief Generates a Software interrupt.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return none.
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
EXTI->SWIEVR |= EXTI_Line;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_ClearFlag
|
||||
*
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
EXTI->INTFR = EXTI_Line;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
enablestatus = EXTI->INTENR & EXTI_Line;
|
||||
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn EXTI_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
*
|
||||
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
EXTI->INTFR = EXTI_Line;
|
||||
}
|
||||
1040
Peripheral/src/ch32x035_flash.c
Normal file
1040
Peripheral/src/ch32x035_flash.c
Normal file
File diff suppressed because it is too large
Load diff
737
Peripheral/src/ch32x035_gpio.c
Normal file
737
Peripheral/src/ch32x035_gpio.c
Normal file
|
|
@ -0,0 +1,737 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_gpio.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/11/06
|
||||
* Description : This file provides all the GPIO firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_gpio.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* MASK */
|
||||
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||
#define DBGAFR_TIM1RP_MASK ((uint32_t)0x00400000)
|
||||
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||
|
||||
volatile uint32_t CFGHR_tmpA = 0x44444444;
|
||||
volatile uint32_t CFGHR_tmpB = 0x44444444;
|
||||
volatile uint32_t CFGHR_tmpC = 0x44444444;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_DeInit
|
||||
*
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_AFIODeInit
|
||||
*
|
||||
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||
* and EXTI configuration) registers to their default reset values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_AFIODeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_Init
|
||||
*
|
||||
* @brief GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
* Note - Only PA0--PA15 and PC16--PC17 support input pull-down
|
||||
*
|
||||
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||
|
||||
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||
|
||||
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||
{
|
||||
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||
}
|
||||
|
||||
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x0000FF)) != 0x00)
|
||||
{
|
||||
tmpreg = GPIOx->CFGLR;
|
||||
|
||||
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if(currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
tmpreg |= (currentmode << pos);
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CFGLR = tmpreg;
|
||||
}
|
||||
|
||||
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF00)) != 0x00)
|
||||
{
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
tmpreg = CFGHR_tmpA;
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
tmpreg = CFGHR_tmpB;
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
tmpreg = CFGHR_tmpC;
|
||||
}
|
||||
|
||||
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||
|
||||
if(currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
tmpreg |= (currentmode << pos);
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CFGHR = tmpreg;
|
||||
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
CFGHR_tmpA = tmpreg;
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
CFGHR_tmpB = tmpreg;
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
CFGHR_tmpC = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Pin > 0x00FFFF)
|
||||
{
|
||||
tmpreg = GPIOx->CFGXR;
|
||||
|
||||
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x10));
|
||||
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||
|
||||
if(currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
tmpreg |= (currentmode << pos);
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x10));
|
||||
}
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSXR = (((uint32_t)0x01) << (pinpos));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CFGXR = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_StructInit
|
||||
*
|
||||
* @brief Fills each GPIO_InitStruct member with its default
|
||||
*
|
||||
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadInputDataBit
|
||||
*
|
||||
* @brief GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
*
|
||||
* @param GPIO_Pin - specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..23).
|
||||
*
|
||||
* @return The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadInputData
|
||||
*
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
*
|
||||
* @return The output port pin value.
|
||||
*/
|
||||
uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = ( uint32_t )GPIOx->INDR;
|
||||
|
||||
return ( val );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadOutputDataBit
|
||||
*
|
||||
* @brief Reads the specified output data port bit.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..23).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadOutputData
|
||||
*
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
*
|
||||
* @return GPIO output port pin value.
|
||||
*/
|
||||
uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
val = ( uint32_t )GPIOx->OUTDR;
|
||||
|
||||
return ( val );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_SetBits
|
||||
*
|
||||
* @brief Sets the selected data port bits.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..23).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF);
|
||||
GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ResetBits
|
||||
*
|
||||
* @brief Clears the selected data port bits.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..23).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
GPIOx->BCR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_WriteBit
|
||||
*
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @param GPIO_Pin - specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..23).
|
||||
* BitVal - specifies the value to be written to the selected bit.
|
||||
* Bit_RESET - to clear the port pin.
|
||||
* Bit_SET - to set the port pin.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
if(BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSHR = (GPIO_Pin & (uint32_t)0x0000FFFF);
|
||||
GPIOx->BSXR = ((GPIO_Pin & (uint32_t)0xFFFF0000) >> 0x10);
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BCR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_Write
|
||||
*
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
* PortVal - specifies the value to be written to the port output data register.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal)
|
||||
{
|
||||
GPIOx->OUTDR = PortVal;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_PinLockConfig
|
||||
*
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..C) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..23).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin)
|
||||
{
|
||||
uint32_t tmp = 0x01000000;
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
GPIOx->LCKR = tmp;
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
GPIOx->LCKR = tmp;
|
||||
tmp = GPIOx->LCKR;
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_PinRemapConfig
|
||||
*
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
*
|
||||
* @param GPIO_Remap - selects the pin to remap.
|
||||
* GPIO_Remap_SPI1 - SPI1 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_SPI1 - SPI1 Partial2 Alternate Function mapping
|
||||
* GPIO_FullRemap_SPI1 - SPI1 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_I2C1 - I2C1 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_I2C1 - I2C1 Partial2 Alternate Function mapping
|
||||
* GPIO_PartialRemap3_I2C1 - I2C1 Partial3 Alternate Function mapping
|
||||
* GPIO_PartialRemap4_I2C1 - I2C1 Partial4 Alternate Function mapping
|
||||
* GPIO_FullRemap_I2C1 - I2C1 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_USART1 - USART1 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_USART1 - USART1 Partial2 Alternate Function mapping
|
||||
* GPIO_FullRemap_USART1 - USART1 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_USART2 - USART2 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_USART2 - USART2 Partial2 Alternate Function mapping
|
||||
* GPIO_PartialRemap3_USART2 - USART2 Partial3 Alternate Function mapping
|
||||
* GPIO_FullRemap_USART2 - USART2 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_USART3 - USART3 Partial2 Alternate Function mapping
|
||||
* GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_USART4 - USART4 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_USART4 - USART4 Partial2 Alternate Function mapping
|
||||
* GPIO_PartialRemap3_USART4 - USART4 Partial3 Alternate Function mapping
|
||||
* GPIO_PartialRemap4_USART4 - USART4 Partial4 Alternate Function mapping
|
||||
* GPIO_PartialRemap5_USART4 - USART4 Partial5 Alternate Function mapping
|
||||
* GPIO_PartialRemap6_USART4 - USART4 Partial6 Alternate Function mapping
|
||||
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_TIM1 - TIM1 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_TIM1 - TIM1 Partial2 Alternate Function mapping
|
||||
* GPIO_PartialRemap3_TIM1 - TIM1 Partial3 Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
|
||||
* GPIO_PartialRemap3_TIM2 - TIM2 Partial3 Alternate Function mapping
|
||||
* GPIO_PartialRemap4_TIM2 - TIM2 Partial4 Alternate Function mapping
|
||||
* GPIO_PartialRemap5_TIM2 - TIM2 Partial5 Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_TIM3 - TIM3 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_TIM3 - TIM3 Partial2 Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
|
||||
* GPIO_Remap_PIOC - PIOC Alternate Function mapping
|
||||
* GPIO_Remap_SWJ_Disable - SDI Disabled (SDI)
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||
|
||||
tmpreg = AFIO->PCFR1;
|
||||
|
||||
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||
tmp = GPIO_Remap & LSB_MASK;
|
||||
|
||||
/* Clear bit */
|
||||
if((GPIO_Remap & 0x08000000) == 0x08000000) /* 3bit */
|
||||
{
|
||||
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] SDI */
|
||||
{
|
||||
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else if((GPIO_Remap & DBGAFR_TIM1RP_MASK) == DBGAFR_TIM1RP_MASK) /* [31:16] 3bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x07) << 15;
|
||||
tmpreg &= ~tmp1;
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (tmp << 15);
|
||||
}
|
||||
|
||||
AFIO->PCFR1 = tmpreg;
|
||||
return;
|
||||
}
|
||||
else if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == DBGAFR_LOCATION_MASK) /* [31:16] 3bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x07) << (tmpmask + 0x10);
|
||||
tmpreg &= ~tmp1;
|
||||
}
|
||||
else /* [15:0] 3bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x07) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
|
||||
tmpreg &= ~tmp1;
|
||||
}
|
||||
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
}
|
||||
else /* [31:0] 1bit */
|
||||
{
|
||||
tmpreg &= ~(tmp << (((GPIO_Remap & 0x00FFFFFF ) >> 0x15) * 0x10));
|
||||
}
|
||||
}
|
||||
|
||||
/* Set bit */
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (tmp << (((GPIO_Remap & 0x00FFFFFF )>> 0x15) * 0x10));
|
||||
}
|
||||
|
||||
AFIO->PCFR1 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_EXTILineConfig
|
||||
*
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
*
|
||||
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..C).
|
||||
* GPIO_PinSource - specifies the EXTI line to be configured.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..23).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
tmp = ((uint32_t)0x03) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F));
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x04] &= ~tmp;
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x04] |= (((uint32_t)GPIO_PortSource) << (0x02 * (GPIO_PinSource & (uint8_t)0x0F)));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_IPD_Unused
|
||||
*
|
||||
* @brief Configure unused GPIO as input pull-up.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_IPD_Unused(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||
uint32_t chip = 0;
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
|
||||
chip = *( uint32_t * )0x1FFFF704 & (~0x000000F1);
|
||||
switch(chip)
|
||||
{
|
||||
case 0x03510600: //CH32X035C8T6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_14|GPIO_Pin_15\
|
||||
|GPIO_Pin_16|GPIO_Pin_17\
|
||||
|GPIO_Pin_18|GPIO_Pin_19\
|
||||
|GPIO_Pin_20|GPIO_Pin_21;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x03560600: //CH32X035G8U6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\
|
||||
|GPIO_Pin_17|GPIO_Pin_18\
|
||||
|GPIO_Pin_19|GPIO_Pin_20\
|
||||
|GPIO_Pin_21|GPIO_Pin_22\
|
||||
|GPIO_Pin_23|GPIO_Pin_14\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15\
|
||||
|GPIO_Pin_16|GPIO_Pin_17\
|
||||
|GPIO_Pin_18|GPIO_Pin_19\
|
||||
|GPIO_Pin_20|GPIO_Pin_21;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x035B0600: //CH32X035G8R6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\
|
||||
|GPIO_Pin_17|GPIO_Pin_18\
|
||||
|GPIO_Pin_19|GPIO_Pin_20\
|
||||
|GPIO_Pin_21|GPIO_Pin_22\
|
||||
|GPIO_Pin_23|GPIO_Pin_14\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15\
|
||||
|GPIO_Pin_16|GPIO_Pin_17\
|
||||
|GPIO_Pin_18|GPIO_Pin_19\
|
||||
|GPIO_Pin_20|GPIO_Pin_21;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x035E0600: //CH32X035F8U6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\
|
||||
|GPIO_Pin_17|GPIO_Pin_18\
|
||||
|GPIO_Pin_19|GPIO_Pin_20\
|
||||
|GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13|GPIO_Pin_14;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_9\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_10\
|
||||
|GPIO_Pin_16|GPIO_Pin_15\
|
||||
|GPIO_Pin_14|GPIO_Pin_13\
|
||||
|GPIO_Pin_17|GPIO_Pin_18\
|
||||
|GPIO_Pin_19|GPIO_Pin_20|GPIO_Pin_21;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x03570600: //CH32X035F7P6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15\
|
||||
|GPIO_Pin_16|GPIO_Pin_17\
|
||||
|GPIO_Pin_18|GPIO_Pin_19\
|
||||
|GPIO_Pin_20|GPIO_Pin_21\
|
||||
|GPIO_Pin_22|GPIO_Pin_23;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\
|
||||
|GPIO_Pin_3|GPIO_Pin_4\
|
||||
|GPIO_Pin_5|GPIO_Pin_6\
|
||||
|GPIO_Pin_7|GPIO_Pin_8\
|
||||
|GPIO_Pin_9|GPIO_Pin_10\
|
||||
|GPIO_Pin_11|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15\
|
||||
|GPIO_Pin_16|GPIO_Pin_17\
|
||||
|GPIO_Pin_18|GPIO_Pin_19\
|
||||
|GPIO_Pin_20|GPIO_Pin_21;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
case 0x03117000: //CH32X033F8P6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_16|GPIO_Pin_15\
|
||||
|GPIO_Pin_17|GPIO_Pin_18\
|
||||
|GPIO_Pin_19|GPIO_Pin_20\
|
||||
|GPIO_Pin_21|GPIO_Pin_22|GPIO_Pin_23\
|
||||
|GPIO_Pin_8|GPIO_Pin_12\
|
||||
|GPIO_Pin_13|GPIO_Pin_14;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5|GPIO_Pin_6\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15\
|
||||
|GPIO_Pin_16|GPIO_Pin_17\
|
||||
|GPIO_Pin_18|GPIO_Pin_19\
|
||||
|GPIO_Pin_20|GPIO_Pin_21\
|
||||
|GPIO_Pin_22|GPIO_Pin_23;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_12|GPIO_Pin_13\
|
||||
|GPIO_Pin_14|GPIO_Pin_15\
|
||||
|GPIO_Pin_20|GPIO_Pin_21\
|
||||
|GPIO_Pin_22|GPIO_Pin_23;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
967
Peripheral/src/ch32x035_i2c.c
Normal file
967
Peripheral/src/ch32x035_i2c.c
Normal file
|
|
@ -0,0 +1,967 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_i2c.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the I2C firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_i2c.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* I2C SPE mask */
|
||||
#define CTLR1_PE_Set ((uint16_t)0x0001)
|
||||
#define CTLR1_PE_Reset ((uint16_t)0xFFFE)
|
||||
|
||||
/* I2C START mask */
|
||||
#define CTLR1_START_Set ((uint16_t)0x0100)
|
||||
#define CTLR1_START_Reset ((uint16_t)0xFEFF)
|
||||
|
||||
/* I2C STOP mask */
|
||||
#define CTLR1_STOP_Set ((uint16_t)0x0200)
|
||||
#define CTLR1_STOP_Reset ((uint16_t)0xFDFF)
|
||||
|
||||
/* I2C ACK mask */
|
||||
#define CTLR1_ACK_Set ((uint16_t)0x0400)
|
||||
#define CTLR1_ACK_Reset ((uint16_t)0xFBFF)
|
||||
|
||||
/* I2C ENGC mask */
|
||||
#define CTLR1_ENGC_Set ((uint16_t)0x0040)
|
||||
#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF)
|
||||
|
||||
/* I2C SWRST mask */
|
||||
#define CTLR1_SWRST_Set ((uint16_t)0x8000)
|
||||
#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF)
|
||||
|
||||
/* I2C PEC mask */
|
||||
#define CTLR1_PEC_Set ((uint16_t)0x1000)
|
||||
#define CTLR1_PEC_Reset ((uint16_t)0xEFFF)
|
||||
|
||||
/* I2C ENPEC mask */
|
||||
#define CTLR1_ENPEC_Set ((uint16_t)0x0020)
|
||||
#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF)
|
||||
|
||||
/* I2C ENARP mask */
|
||||
#define CTLR1_ENARP_Set ((uint16_t)0x0010)
|
||||
#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF)
|
||||
|
||||
/* I2C NOSTRETCH mask */
|
||||
#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080)
|
||||
#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
|
||||
|
||||
/* I2C registers Masks */
|
||||
#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5)
|
||||
|
||||
/* I2C DMAEN mask */
|
||||
#define CTLR2_DMAEN_Set ((uint16_t)0x0800)
|
||||
#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF)
|
||||
|
||||
/* I2C LAST mask */
|
||||
#define CTLR2_LAST_Set ((uint16_t)0x1000)
|
||||
#define CTLR2_LAST_Reset ((uint16_t)0xEFFF)
|
||||
|
||||
/* I2C FREQ mask */
|
||||
#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0)
|
||||
|
||||
/* I2C ADD0 mask */
|
||||
#define OADDR1_ADD0_Set ((uint16_t)0x0001)
|
||||
#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE)
|
||||
|
||||
/* I2C ENDUAL mask */
|
||||
#define OADDR2_ENDUAL_Set ((uint16_t)0x0001)
|
||||
#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE)
|
||||
|
||||
/* I2C ADD2 mask */
|
||||
#define OADDR2_ADD2_Reset ((uint16_t)0xFF01)
|
||||
|
||||
/* I2C F/S mask */
|
||||
#define CKCFGR_FS_Set ((uint16_t)0x8000)
|
||||
|
||||
/* I2C CCR mask */
|
||||
#define CKCFGR_CCR_Set ((uint16_t)0x0FFF)
|
||||
|
||||
/* I2C FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x00FFFFFF)
|
||||
|
||||
/* I2C Interrupt Enable mask */
|
||||
#define ITEN_Mask ((uint32_t)0x07000000)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DeInit
|
||||
*
|
||||
* @brief Deinitializes the I2Cx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DeInit(I2C_TypeDef *I2Cx)
|
||||
{
|
||||
if(I2Cx == I2C1)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_Init
|
||||
*
|
||||
* @brief Initializes the I2Cx peripheral according to the specified
|
||||
* parameters in the I2C_InitStruct.
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_InitStruct - pointer to a I2C_InitTypeDef structure that
|
||||
* contains the configuration information for the specified I2C peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0, freqrange = 0;
|
||||
uint16_t result = 0x04;
|
||||
uint32_t pclk1 = 8000000;
|
||||
|
||||
RCC_ClocksTypeDef rcc_clocks;
|
||||
|
||||
tmpreg = I2Cx->CTLR2;
|
||||
tmpreg &= CTLR2_FREQ_Reset;
|
||||
RCC_GetClocksFreq(&rcc_clocks);
|
||||
pclk1 = rcc_clocks.PCLK1_Frequency;
|
||||
freqrange = (uint16_t)(pclk1 / 1000000);
|
||||
tmpreg |= freqrange;
|
||||
I2Cx->CTLR2 = tmpreg;
|
||||
|
||||
I2Cx->CTLR1 &= CTLR1_PE_Reset;
|
||||
tmpreg = 0;
|
||||
|
||||
if(I2C_InitStruct->I2C_ClockSpeed <= 100000)
|
||||
{
|
||||
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
|
||||
|
||||
if(result < 0x04)
|
||||
{
|
||||
result = 0x04;
|
||||
}
|
||||
|
||||
tmpreg |= result;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
|
||||
{
|
||||
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
|
||||
}
|
||||
else
|
||||
{
|
||||
result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
|
||||
result |= I2C_DutyCycle_16_9;
|
||||
}
|
||||
|
||||
if((result & CKCFGR_CCR_Set) == 0)
|
||||
{
|
||||
result |= (uint16_t)0x0001;
|
||||
}
|
||||
|
||||
tmpreg |= (uint16_t)(result | CKCFGR_FS_Set);
|
||||
}
|
||||
|
||||
I2Cx->CKCFGR = tmpreg;
|
||||
I2Cx->CTLR1 |= CTLR1_PE_Set;
|
||||
|
||||
tmpreg = I2Cx->CTLR1;
|
||||
tmpreg &= CTLR1_CLEAR_Mask;
|
||||
tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
|
||||
I2Cx->CTLR1 = tmpreg;
|
||||
|
||||
I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_StructInit
|
||||
*
|
||||
* @brief Fills each I2C_InitStruct member with its default value.
|
||||
*
|
||||
* @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
|
||||
{
|
||||
I2C_InitStruct->I2C_ClockSpeed = 5000;
|
||||
I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
|
||||
I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
|
||||
I2C_InitStruct->I2C_OwnAddress1 = 0;
|
||||
I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
|
||||
I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C peripheral.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_PE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_PE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DMACmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C DMA requests.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DMALastTransferCmd
|
||||
*
|
||||
* @brief Specifies if the next DMA transfer will be the last one.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR2 |= CTLR2_LAST_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR2 &= CTLR2_LAST_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GenerateSTART
|
||||
*
|
||||
* @brief Generates I2Cx communication START condition.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_START_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_START_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GenerateSTOP
|
||||
*
|
||||
* @brief Generates I2Cx communication STOP condition.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_STOP_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_STOP_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_AcknowledgeConfig
|
||||
*
|
||||
* @brief Enables or disables the specified I2C acknowledge feature.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ACK_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ACK_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_OwnAddress2Config
|
||||
*
|
||||
* @brief Configures the specified I2C own address2.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* Address - specifies the 7bit I2C own address2.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
tmpreg = I2Cx->OADDR2;
|
||||
tmpreg &= OADDR2_ADD2_Reset;
|
||||
tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
|
||||
I2Cx->OADDR2 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_DualAddressCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C dual addressing mode.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GeneralCallCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C general call feature.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ENGC_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified I2C interrupts.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_IT - specifies the I2C interrupts sources to be enabled or disabled.
|
||||
* I2C_IT_BUF - Buffer interrupt mask.
|
||||
* I2C_IT_EVT - Event interrupt mask.
|
||||
* I2C_IT_ERR - Error interrupt mask.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR2 |= I2C_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR2 &= (uint16_t)~I2C_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_SendData
|
||||
*
|
||||
* @brief Sends a data byte through the I2Cx peripheral.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* Data - Byte to be transmitted.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
|
||||
{
|
||||
I2Cx->DATAR = Data;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ReceiveData
|
||||
*
|
||||
* @brief Returns the most recent received data by the I2Cx peripheral.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return The value of the received data.
|
||||
*/
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint8_t)I2Cx->DATAR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_Send7bitAddress
|
||||
*
|
||||
* @brief Transmits the address byte to select the slave device.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* Address - specifies the slave address which will be transmitted.
|
||||
* I2C_Direction - specifies whether the I2C device will be a
|
||||
* Transmitter or a Receiver.
|
||||
* I2C_Direction_Transmitter - Transmitter mode.
|
||||
* I2C_Direction_Receiver - Receiver mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
|
||||
{
|
||||
if(I2C_Direction != I2C_Direction_Transmitter)
|
||||
{
|
||||
Address |= OADDR1_ADD0_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
Address &= OADDR1_ADD0_Reset;
|
||||
}
|
||||
|
||||
I2Cx->DATAR = Address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ReadRegister
|
||||
*
|
||||
* @brief Reads the specified I2C register and returns its value.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_Register - specifies the register to read.
|
||||
* I2C_Register_CTLR1.
|
||||
* I2C_Register_CTLR2.
|
||||
* I2C_Register_OADDR1.
|
||||
* I2C_Register_OADDR2.
|
||||
* I2C_Register_DATAR.
|
||||
* I2C_Register_STAR1.
|
||||
* I2C_Register_STAR2.
|
||||
* I2C_Register_CKCFGR.
|
||||
* I2C_Register_RTR.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
tmp = (uint32_t)I2Cx;
|
||||
tmp += I2C_Register;
|
||||
|
||||
return (*(__IO uint16_t *)tmp);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_SoftwareResetCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C software reset.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_SWRST_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_NACKPositionConfig
|
||||
*
|
||||
* @brief Selects the specified I2C NACK position in master receiver mode.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_NACKPosition - specifies the NACK position.
|
||||
* I2C_NACKPosition_Next - indicates that the next byte will be
|
||||
* the last received byte.
|
||||
* I2C_NACKPosition_Current - indicates that current byte is the
|
||||
* last received byte.
|
||||
* Note-
|
||||
* This function configures the same bit (POS) as I2C_PECPositionConfig()
|
||||
* but is intended to be used in I2C mode while I2C_PECPositionConfig()
|
||||
* is intended to used in SMBUS mode.
|
||||
* @return none
|
||||
*/
|
||||
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
|
||||
{
|
||||
if(I2C_NACKPosition == I2C_NACKPosition_Next)
|
||||
{
|
||||
I2Cx->CTLR1 |= I2C_NACKPosition_Next;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= I2C_NACKPosition_Current;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_TransmitPEC
|
||||
*
|
||||
* @brief Enables or disables the specified I2C PEC transfer.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_PEC_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_PEC_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_PECPositionConfig
|
||||
*
|
||||
* @brief Selects the specified I2C PEC position.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_PECPosition - specifies the PEC position.
|
||||
* I2C_PECPosition_Next - indicates that the next byte is PEC.
|
||||
* I2C_PECPosition_Current - indicates that current byte is PEC.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
|
||||
{
|
||||
if(I2C_PECPosition == I2C_PECPosition_Next)
|
||||
{
|
||||
I2Cx->CTLR1 |= I2C_PECPosition_Next;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= I2C_PECPosition_Current;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_CalculatePEC
|
||||
*
|
||||
* @brief Enables or disables the PEC value calculation of the transferred bytes.
|
||||
*
|
||||
* @param I2Cx- where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetPEC
|
||||
*
|
||||
* @brief Returns the PEC value for the specified I2C.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return The PEC value.
|
||||
*/
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((I2Cx->STAR2) >> 8);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ARPCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C ARP.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return The PEC value.
|
||||
*/
|
||||
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_ENARP_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_StretchClockCmd
|
||||
*
|
||||
* @brief Enables or disables the specified I2C Clock stretching.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState == DISABLE)
|
||||
{
|
||||
I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_FastModeDutyCycleConfig
|
||||
*
|
||||
* @brief Selects the specified I2C fast mode duty cycle.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_DutyCycle - specifies the fast mode duty cycle.
|
||||
* I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2.
|
||||
* I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
|
||||
{
|
||||
if(I2C_DutyCycle != I2C_DutyCycle_16_9)
|
||||
{
|
||||
I2Cx->CKCFGR &= I2C_DutyCycle_2;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_CheckEvent
|
||||
*
|
||||
* @brief Checks whether the last I2Cx Event is equal to the one passed
|
||||
* as parameter.
|
||||
*
|
||||
* @param I2Cx- where x can be 1 to select the I2C peripheral.
|
||||
* I2C_EVENT: specifies the event to be checked.
|
||||
* I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1.
|
||||
* I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1.
|
||||
* I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1.
|
||||
* I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1.
|
||||
* I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1.
|
||||
* I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2.
|
||||
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2.
|
||||
* (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2.
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3.
|
||||
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3.
|
||||
* (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3.
|
||||
* I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2.
|
||||
* I2C_EVENT_SLAVE_STOP_DETECTED - EVT4.
|
||||
* I2C_EVENT_MASTER_MODE_SELECT - EVT5.
|
||||
* I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6.
|
||||
* I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6.
|
||||
* I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7.
|
||||
* I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8.
|
||||
* I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2.
|
||||
* I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9.
|
||||
*
|
||||
* @return ErrorStatus - READY or NoREADY.
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
|
||||
{
|
||||
uint32_t lastevent = 0;
|
||||
uint32_t flag1 = 0, flag2 = 0;
|
||||
ErrorStatus status = NoREADY;
|
||||
|
||||
flag1 = I2Cx->STAR1;
|
||||
flag2 = I2Cx->STAR2;
|
||||
flag2 = flag2 << 16;
|
||||
|
||||
lastevent = (flag1 | flag2) & FLAG_Mask;
|
||||
|
||||
if((lastevent & I2C_EVENT) == I2C_EVENT)
|
||||
{
|
||||
status = READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = NoREADY;
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetLastEvent
|
||||
*
|
||||
* @brief Returns the last I2Cx Event.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
|
||||
{
|
||||
uint32_t lastevent = 0;
|
||||
uint32_t flag1 = 0, flag2 = 0;
|
||||
|
||||
flag1 = I2Cx->STAR1;
|
||||
flag2 = I2Cx->STAR2;
|
||||
flag2 = flag2 << 16;
|
||||
lastevent = (flag1 | flag2) & FLAG_Mask;
|
||||
|
||||
return lastevent;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the last I2Cx Event is equal to the one passed
|
||||
* as parameter.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_FLAG - specifies the flag to check.
|
||||
* I2C_FLAG_DUALF - Dual flag (Slave mode).
|
||||
* I2C_FLAG_GENCALL - General call header flag (Slave mode).
|
||||
* I2C_FLAG_TRA - Transmitter/Receiver flag.
|
||||
* I2C_FLAG_BUSY - Bus busy flag.
|
||||
* I2C_FLAG_MSL - Master/Slave flag.
|
||||
* I2C_FLAG_PECERR - PEC error in reception flag.
|
||||
* I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
|
||||
* I2C_FLAG_AF - Acknowledge failure flag.
|
||||
* I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
|
||||
* I2C_FLAG_BERR - Bus error flag.
|
||||
* I2C_FLAG_TXE - Data register empty flag (Transmitter).
|
||||
* I2C_FLAG_RXNE- Data register not empty (Receiver) flag.
|
||||
* I2C_FLAG_STOPF - Stop detection flag (Slave mode).
|
||||
* I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode).
|
||||
* I2C_FLAG_BTF - Byte transfer finished flag.
|
||||
* I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL"
|
||||
* Address matched flag (Slave mode)"ENDA".
|
||||
* I2C_FLAG_SB - Start bit flag (Master mode).
|
||||
*
|
||||
* @return FlagStatus - SET or RESET.
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
__IO uint32_t i2creg = 0, i2cxbase = 0;
|
||||
|
||||
i2cxbase = (uint32_t)I2Cx;
|
||||
i2creg = I2C_FLAG >> 28;
|
||||
I2C_FLAG &= FLAG_Mask;
|
||||
|
||||
if(i2creg != 0)
|
||||
{
|
||||
i2cxbase += 0x14;
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
|
||||
i2cxbase += 0x18;
|
||||
}
|
||||
|
||||
if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ClearFlag
|
||||
*
|
||||
* @brief Clears the I2Cx's pending flags.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_FLAG - specifies the flag to clear.
|
||||
* I2C_FLAG_PECERR - PEC error in reception flag.
|
||||
* I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
|
||||
* I2C_FLAG_AF - Acknowledge failure flag.
|
||||
* I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
|
||||
* I2C_FLAG_BERR - Bus error flag.
|
||||
* Note-
|
||||
* - STOPF (STOP detection) is cleared by software sequence: a read operation
|
||||
* to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation
|
||||
* to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral).
|
||||
* - ADD10 (10-bit header sent) is cleared by software sequence: a read
|
||||
* operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the
|
||||
* second byte of the address in DATAR register.
|
||||
* - BTF (Byte Transfer Finished) is cleared by software sequence: a read
|
||||
* operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a
|
||||
* read/write to I2C_DATAR register (I2C_SendData()).
|
||||
* - ADDR (Address sent) is cleared by software sequence: a read operation to
|
||||
* I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to
|
||||
* I2C_SATR2 register ((void)(I2Cx->SR2)).
|
||||
* - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1
|
||||
* register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR
|
||||
* register (I2C_SendData()).
|
||||
* @return none
|
||||
*/
|
||||
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
|
||||
{
|
||||
uint32_t flagpos = 0;
|
||||
|
||||
flagpos = I2C_FLAG & FLAG_Mask;
|
||||
I2Cx->STAR1 = (uint16_t)~flagpos;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified I2C interrupt has occurred or not.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* II2C_IT - specifies the interrupt source to check.
|
||||
* I2C_IT_PECERR - PEC error in reception flag.
|
||||
* I2C_IT_OVR - Overrun/Underrun flag (Slave mode).
|
||||
* I2C_IT_AF - Acknowledge failure flag.
|
||||
* I2C_IT_ARLO - Arbitration lost flag (Master mode).
|
||||
* I2C_IT_BERR - Bus error flag.
|
||||
* I2C_IT_TXE - Data register empty flag (Transmitter).
|
||||
* I2C_IT_RXNE - Data register not empty (Receiver) flag.
|
||||
* I2C_IT_STOPF - Stop detection flag (Slave mode).
|
||||
* I2C_IT_ADD10 - 10-bit header sent flag (Master mode).
|
||||
* I2C_IT_BTF - Byte transfer finished flag.
|
||||
* I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched
|
||||
* flag (Slave mode)"ENDAD".
|
||||
* I2C_IT_SB - Start bit flag (Master mode).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2));
|
||||
I2C_IT &= FLAG_Mask;
|
||||
|
||||
if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn I2C_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the I2Cx interrupt pending bits.
|
||||
*
|
||||
* @param I2Cx - where x can be 1 to select the I2C peripheral.
|
||||
* I2C_IT - specifies the interrupt pending bit to clear.
|
||||
* I2C_IT_PECERR - PEC error in reception interrupt.
|
||||
* I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode).
|
||||
* I2C_IT_AF - Acknowledge failure interrupt.
|
||||
* I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
|
||||
* I2C_IT_BERR - Bus error interrupt.
|
||||
* Note-
|
||||
* - STOPF (STOP detection) is cleared by software sequence: a read operation
|
||||
* to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to
|
||||
* I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral).
|
||||
* - ADD10 (10-bit header sent) is cleared by software sequence: a read
|
||||
* operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second
|
||||
* byte of the address in I2C_DATAR register.
|
||||
* - BTF (Byte Transfer Finished) is cleared by software sequence: a read
|
||||
* operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a
|
||||
* read/write to I2C_DATAR register (I2C_SendData()).
|
||||
* - ADDR (Address sent) is cleared by software sequence: a read operation to
|
||||
* I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to
|
||||
* I2C_STAR2 register ((void)(I2Cx->SR2)).
|
||||
* - SB (Start Bit) is cleared by software sequence: a read operation to
|
||||
* I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to
|
||||
* I2C_DATAR register (I2C_SendData()).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
|
||||
{
|
||||
uint32_t flagpos = 0;
|
||||
|
||||
flagpos = I2C_IT & FLAG_Mask;
|
||||
I2Cx->STAR1 = (uint16_t)~flagpos;
|
||||
}
|
||||
122
Peripheral/src/ch32x035_iwdg.c
Normal file
122
Peripheral/src/ch32x035_iwdg.c
Normal file
|
|
@ -0,0 +1,122 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_iwdg.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the IWDG firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_iwdg.h"
|
||||
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
|
||||
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_WriteAccessCmd
|
||||
*
|
||||
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
|
||||
*
|
||||
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
|
||||
* IWDG_RLDR registers.
|
||||
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
|
||||
* IWDG_RLDR registers.
|
||||
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
|
||||
* and IWDG_RLDR registers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
IWDG->CTLR = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_SetPrescaler
|
||||
*
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
*
|
||||
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
|
||||
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
|
||||
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
|
||||
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
|
||||
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
|
||||
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
|
||||
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
|
||||
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
IWDG->PSCR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_SetReload
|
||||
*
|
||||
* @brief Sets IWDG Reload value.
|
||||
*
|
||||
* @param Reload - specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_SetReload(uint16_t Reload)
|
||||
{
|
||||
IWDG->RLDR = Reload;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_ReloadCounter
|
||||
*
|
||||
* @brief Reloads IWDG counter with value defined in the reload register.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->CTLR = CTLR_KEY_Reload;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_Enable
|
||||
*
|
||||
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->CTLR = CTLR_KEY_Enable;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn IWDG_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
*
|
||||
* @param IWDG_FLAG - specifies the flag to check.
|
||||
* IWDG_FLAG_PVU - Prescaler Value Update on going.
|
||||
* IWDG_FLAG_RVU - Reload Value Update on going.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
109
Peripheral/src/ch32x035_misc.c
Normal file
109
Peripheral/src/ch32x035_misc.c
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_misc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the miscellaneous firmware functions .
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_misc.h"
|
||||
|
||||
__IO uint32_t NVIC_Priority_Group = 0;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_PriorityGroupConfig
|
||||
*
|
||||
* @brief Configures the priority grouping - pre-emption priority and subpriority.
|
||||
*
|
||||
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
|
||||
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
|
||||
* 2 bits for subpriority
|
||||
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
|
||||
* 1 bits for subpriority
|
||||
* NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
|
||||
* 0 bits for subpriority
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
NVIC_Priority_Group = NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_Init
|
||||
*
|
||||
* @brief Initializes the NVIC peripheral according to the specified parameters in
|
||||
* the NVIC_InitStruct.
|
||||
*
|
||||
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
|
||||
* configuration information for the specified NVIC peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
|
||||
{
|
||||
uint8_t tmppre = 0;
|
||||
|
||||
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
|
||||
}
|
||||
else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
|
||||
{
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
|
||||
}
|
||||
}
|
||||
else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
|
||||
{
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
|
||||
{
|
||||
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
|
||||
}
|
||||
}
|
||||
else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
|
||||
{
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
|
||||
{
|
||||
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
|
||||
}
|
||||
}
|
||||
else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
|
||||
}
|
||||
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||
}
|
||||
}
|
||||
320
Peripheral/src/ch32x035_opa.c
Normal file
320
Peripheral/src/ch32x035_opa.c
Normal file
|
|
@ -0,0 +1,320 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_opa.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the OPA firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_opa.h"
|
||||
|
||||
|
||||
/* FLASH Keys */
|
||||
#define OPA_KEY1 ((uint32_t)0x45670123)
|
||||
#define OPA_KEY2 ((uint32_t)0xCDEF89AB)
|
||||
|
||||
volatile uint32_t CTLR2_tmp = 0;
|
||||
|
||||
/********************************************************************************
|
||||
* @fn OPA_Unlock
|
||||
*
|
||||
* @brief Unlocks the OPA Controller.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void OPA_Unlock(void)
|
||||
{
|
||||
OPA->OPAKEY = OPA_KEY1;
|
||||
OPA->OPAKEY = OPA_KEY2;
|
||||
}
|
||||
|
||||
/********************************************************************************
|
||||
* @fn OPA_Lock
|
||||
*
|
||||
* @brief Locks the OPA Controller.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void OPA_Lock(void)
|
||||
{
|
||||
OPA->CTLR1 |= (1<<31);
|
||||
}
|
||||
|
||||
/********************************************************************************
|
||||
* @fn OPA_POLL_Unlock
|
||||
*
|
||||
* @brief Unlocks the OPA POLL Controller.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void OPA_POLL_Unlock(void)
|
||||
{
|
||||
OPA->POLLKEY = OPA_KEY1;
|
||||
OPA->POLLKEY = OPA_KEY2;
|
||||
}
|
||||
|
||||
/********************************************************************************
|
||||
* @fn OPA_POLL_Lock
|
||||
*
|
||||
* @brief Locks the OPA POLL Controller.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void OPA_POLL_Lock(void)
|
||||
{
|
||||
OPA->CFGR1 |= (1<<7);
|
||||
}
|
||||
|
||||
/********************************************************************************
|
||||
* @fn OPA_CMP_Unlock
|
||||
*
|
||||
* @brief Unlocks the CMP Controller.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void OPA_CMP_Unlock(void)
|
||||
{
|
||||
OPA->CMPKEY = OPA_KEY1;
|
||||
OPA->CMPKEY = OPA_KEY2;
|
||||
}
|
||||
|
||||
/********************************************************************************
|
||||
* @fn OPA_CMP_Lock
|
||||
*
|
||||
* @brief Locks the CMP Controller.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void OPA_CMP_Lock(void)
|
||||
{
|
||||
CTLR2_tmp |= (1<<31);
|
||||
OPA->CTLR2 = CTLR2_tmp;
|
||||
CTLR2_tmp &= ~(1<<31);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_Init
|
||||
*
|
||||
* @brief Initializes the OPA peripheral according to the specified
|
||||
* parameters in the OPA_InitStruct.
|
||||
*
|
||||
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
|
||||
{
|
||||
uint16_t tmp0 = 0, tmp1 = 0;
|
||||
uint32_t tmp2 = 0;
|
||||
|
||||
tmp0 = OPA->CFGR1;
|
||||
tmp1 = OPA->CFGR2;
|
||||
tmp2 = OPA->CTLR1;
|
||||
|
||||
if(OPA_InitStruct->OPA_NUM == OPA1)
|
||||
{
|
||||
tmp1 &= 0xFCFF;
|
||||
tmp2 &= 0xFFFF0001;
|
||||
|
||||
tmp1 |= (OPA_InitStruct->POLL_NUM << 9);
|
||||
tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 3)
|
||||
| (OPA_InitStruct->FB << 5) | (OPA_InitStruct->NSEL << 6);
|
||||
}
|
||||
else if(OPA_InitStruct->OPA_NUM == OPA2)
|
||||
{
|
||||
tmp1 &= 0xF3FF;
|
||||
tmp2 &= 0x0001FFFF;
|
||||
|
||||
tmp1 |= (OPA_InitStruct->POLL_NUM << 11);
|
||||
tmp2 |= (OPA_InitStruct->Mode << 17) | (OPA_InitStruct->PSEL << 19)
|
||||
| (OPA_InitStruct->FB << 21) | (OPA_InitStruct->NSEL << 22);
|
||||
}
|
||||
|
||||
tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2)
|
||||
| (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->BKIN_SEL << 6)
|
||||
| (OPA_InitStruct->OUT_IE << 8) | (OPA_InitStruct->CNT_IE << 10)
|
||||
| (OPA_InitStruct->NMI_IE << 11);
|
||||
tmp1 &= 0xFF00;
|
||||
tmp1 |= OPA_InitStruct->OPA_POLL_Interval;
|
||||
|
||||
OPA->CFGR1 = tmp0;
|
||||
OPA->CFGR2 = tmp1;
|
||||
OPA->CTLR1 = tmp2;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_StructInit
|
||||
*
|
||||
* @brief Fills each OPA_StructInit member with its reset value.
|
||||
*
|
||||
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
|
||||
{
|
||||
OPA_InitStruct->OPA_POLL_Interval = 0;
|
||||
OPA_InitStruct->OPA_NUM = OPA1;
|
||||
OPA_InitStruct->Mode = OUT_IO_OUT0;
|
||||
OPA_InitStruct->PSEL = CHP0;
|
||||
OPA_InitStruct->FB = FB_OFF;
|
||||
OPA_InitStruct->NSEL = CHN0;
|
||||
OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF_OPA2_OFF;
|
||||
OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF_OPA2_OFF;
|
||||
OPA_InitStruct->RST_EN = RST_OPA1_OFF_OPA2_OFF;
|
||||
OPA_InitStruct->BKIN_SEL = BKIN_OPA1_TIM1_OPA2_TIM2;
|
||||
OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF_OPA2_OFF;
|
||||
OPA_InitStruct->CNT_IE = CNT_IE_OFF;
|
||||
OPA_InitStruct->NMI_IE = NMI_IE_OFF;
|
||||
OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified OPA peripheral.
|
||||
*
|
||||
* @param OPA_NUM - Select OPA
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16));
|
||||
}
|
||||
else
|
||||
{
|
||||
OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16));
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_CMP_Init
|
||||
*
|
||||
* @brief Initializes the CMP peripheral according to the specified
|
||||
* parameters in the CMP_InitTypeDef.
|
||||
*
|
||||
* @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct)
|
||||
{
|
||||
uint32_t tmp1 = 0;
|
||||
|
||||
tmp1 = CTLR2_tmp;
|
||||
|
||||
if(CMP_InitStruct->CMP_NUM == CMP1)
|
||||
{
|
||||
tmp1 &= 0xFFFFFFE1;
|
||||
tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 2)
|
||||
| (CMP_InitStruct->PSEL << 3) | (CMP_InitStruct->HYEN << 4);
|
||||
}
|
||||
else if(CMP_InitStruct->CMP_NUM == CMP2)
|
||||
{
|
||||
tmp1 &= 0xFFFFFC3F;
|
||||
tmp1 |= (CMP_InitStruct->Mode << 6) | (CMP_InitStruct->NSEL << 7)
|
||||
| (CMP_InitStruct->PSEL << 8) | (CMP_InitStruct->HYEN << 9);
|
||||
}
|
||||
else if(CMP_InitStruct->CMP_NUM == CMP3)
|
||||
{
|
||||
tmp1 &= 0xFFFF87FF;
|
||||
tmp1 |= (CMP_InitStruct->Mode << 11) | (CMP_InitStruct->NSEL << 12)
|
||||
| (CMP_InitStruct->PSEL << 13) | (CMP_InitStruct->HYEN << 14);
|
||||
}
|
||||
|
||||
CTLR2_tmp = tmp1;
|
||||
OPA->CTLR2 = tmp1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_CMP_StructInit
|
||||
*
|
||||
* @brief Fills each OPA_CMP_StructInit member with its reset value.
|
||||
*
|
||||
* @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct)
|
||||
{
|
||||
CMP_InitStruct->CMP_NUM = CMP1;
|
||||
CMP_InitStruct->Mode = OUT_IO_TIM2;
|
||||
CMP_InitStruct->NSEL = CMP_CHN0;
|
||||
CMP_InitStruct->PSEL = CMP_CHP1;
|
||||
CMP_InitStruct->HYEN = CMP_HYEN1;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_CMP_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified CMP peripheral.
|
||||
*
|
||||
* @param CMP_NUM - Select CMP
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState)
|
||||
{
|
||||
if(NewState == ENABLE)
|
||||
{
|
||||
CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*5));
|
||||
}
|
||||
else
|
||||
{
|
||||
CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*5));
|
||||
}
|
||||
|
||||
OPA->CTLR2 = CTLR2_tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the OPA flag is set or not.
|
||||
*
|
||||
* @param OPA_FLAG - specifies the SPI/I2S flag to check.
|
||||
* OPA_FLAG_OUT_OPA1 - OPA1 out flag
|
||||
* OPA_FLAG_OUT_OPA2 - OPA2 out flag
|
||||
* OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data
|
||||
*
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn OPA_ClearFlag
|
||||
*
|
||||
* @brief Clears the OPA flag.
|
||||
*
|
||||
* @param OPA_FLAG - specifies the OPA flag to clear.
|
||||
* OPA_FLAG_OUT_OPA1 - OPA1 out flag
|
||||
* OPA_FLAG_OUT_OPA2 - OPA2 out flag
|
||||
* OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data
|
||||
* @return none
|
||||
*/
|
||||
void OPA_ClearFlag(uint16_t OPA_FLAG)
|
||||
{
|
||||
OPA->CFGR1 &= (uint16_t)~OPA_FLAG;
|
||||
}
|
||||
156
Peripheral/src/ch32x035_pwr.c
Normal file
156
Peripheral/src/ch32x035_pwr.c
Normal file
|
|
@ -0,0 +1,156 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_pwr.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the PWR firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_pwr.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* PWR registers bit mask */
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
|
||||
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF9F)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_DeInit
|
||||
*
|
||||
* @brief Deinitializes the PWR peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_PVDLevelConfig
|
||||
*
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage
|
||||
* Detector(PVD).
|
||||
*
|
||||
* @param PWR_PVDLevel - specifies the PVD detection level
|
||||
* PWR_PVDLevel_2V1 - PVD detection level set to 2.1V
|
||||
* PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
|
||||
* PWR_PVDLevel_3V0 - PVD detection level set to 3.0V
|
||||
* PWR_PVDLevel_4V0 - PVD detection level set to 4.0V
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
tmpreg &= CTLR_PLS_MASK;
|
||||
tmpreg |= PWR_PVDLevel;
|
||||
PWR->CTLR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTOPMode
|
||||
*
|
||||
* @brief Enters STOP mode.
|
||||
*
|
||||
* @param PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
|
||||
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = PWR->CTLR;
|
||||
tmpreg &= CTLR_DS_MASK;
|
||||
PWR->CTLR = tmpreg;
|
||||
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
__WFE();
|
||||
}
|
||||
|
||||
NVIC->SCTLR &= ~(1 << 2);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_EnterSTANDBYMode
|
||||
*
|
||||
* @brief Enters STANDBY mode.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
PWR->CTLR |= PWR_CTLR_PDDS;
|
||||
NVIC->SCTLR |= (1 << 2);
|
||||
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
*
|
||||
* @param PWR_FLAG - specifies the flag to check.
|
||||
* PWR_FLAG_PVDO - PVD Output
|
||||
* PWR_FLAG_FLASH - Flash low power flag
|
||||
*
|
||||
* @return The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn PWR_VDD_SupplyVoltage
|
||||
*
|
||||
* @brief Checks VDD Supply Voltage.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return PWR_VDD - VDD Supply Voltage.
|
||||
* PWR_VDD_5V - VDD = 5V
|
||||
* PWR_VDD_3V3 - VDD = 3.3V
|
||||
*/
|
||||
PWR_VDD PWR_VDD_SupplyVoltage(void)
|
||||
{
|
||||
|
||||
PWR_VDD VDD_Voltage = PWR_VDD_3V3;
|
||||
Delay_Init();
|
||||
RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE);
|
||||
PWR_PVDLevelConfig(PWR_PVDLevel_4V0);
|
||||
Delay_Us(10);
|
||||
if( PWR_GetFlagStatus(PWR_FLAG_PVDO) == (uint32_t)RESET)
|
||||
{
|
||||
VDD_Voltage = PWR_VDD_5V;
|
||||
}
|
||||
PWR_PVDLevelConfig(PWR_PVDLevel_2V1);
|
||||
|
||||
return VDD_Voltage;
|
||||
}
|
||||
411
Peripheral/src/ch32x035_rcc.c
Normal file
411
Peripheral/src/ch32x035_rcc.c
Normal file
|
|
@ -0,0 +1,411 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_rcc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the RCC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* RCC registers bit mask */
|
||||
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
|
||||
|
||||
/* CFGR0 register bit mask */
|
||||
#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
|
||||
#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
|
||||
|
||||
/* RSTSCKR register bit mask */
|
||||
#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
|
||||
|
||||
/* RCC Flag Mask */
|
||||
#define FLAG_Mask ((uint8_t)0x1F)
|
||||
|
||||
/* CFGR0 register byte 4 (Bits[31:24]) base address */
|
||||
#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
|
||||
|
||||
|
||||
static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_DeInit
|
||||
*
|
||||
* @brief Resets the RCC clock configuration to the default reset state.
|
||||
* Note-
|
||||
* HSE can not be stopped if it is used directly or through the PLL as system clock.
|
||||
* @return none
|
||||
*/
|
||||
void RCC_DeInit(void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 |= (uint32_t)0x00000050;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FFFF5F;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_AdjustHSICalibrationValue
|
||||
*
|
||||
* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
|
||||
*
|
||||
* @param HSICalibrationValue - specifies the calibration trimming value.
|
||||
* This parameter must be a number between 0 and 0x1F.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CTLR;
|
||||
tmpreg &= CTLR_HSITRIM_Mask;
|
||||
tmpreg |= (uint32_t)HSICalibrationValue << 3;
|
||||
RCC->CTLR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_HSICmd
|
||||
*
|
||||
* @brief Enables or disables the Internal High Speed oscillator (HSI).
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_HSICmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
RCC->CTLR |= (1<<0);
|
||||
}
|
||||
else{
|
||||
RCC->CTLR &= ~(1<<0);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_HCLKConfig
|
||||
*
|
||||
* @brief Configures the AHB clock (HCLK).
|
||||
*
|
||||
* @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
|
||||
* the system clock (SYSCLK).
|
||||
* RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
|
||||
* RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
|
||||
* RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3.
|
||||
* RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
|
||||
* RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5.
|
||||
* RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6.
|
||||
* RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7.
|
||||
* RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
|
||||
* RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
|
||||
* RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32.
|
||||
* RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
|
||||
* RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
|
||||
* RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CFGR0;
|
||||
tmpreg &= CFGR0_HPRE_Reset_Mask;
|
||||
tmpreg |= RCC_SYSCLK;
|
||||
RCC->CFGR0 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_GetClocksFreq
|
||||
*
|
||||
* @brief The result of this function could be not correct when using
|
||||
* fractional value for HSE crystal.
|
||||
*
|
||||
* @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
|
||||
* the clocks frequencies.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
|
||||
{
|
||||
uint32_t tmp = 0, presc = 0;
|
||||
|
||||
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
||||
|
||||
tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
|
||||
tmp = tmp >> 4;
|
||||
presc = APBAHBPrescTable[tmp];
|
||||
|
||||
if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8)
|
||||
{
|
||||
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
|
||||
}
|
||||
|
||||
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency;
|
||||
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_AHBPeriphClockCmd
|
||||
*
|
||||
* @brief Enables or disables the AHB peripheral clock.
|
||||
*
|
||||
* @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
|
||||
* RCC_AHBPeriph_DMA1.
|
||||
* RCC_AHBPeriph_SRAM.
|
||||
* RCC_AHBPeriph_USBFS.
|
||||
* RCC_AHBPeriph_USBPD
|
||||
* Note-
|
||||
* SRAM clock can be disabled only during sleep mode.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RCC->AHBPCENR |= RCC_AHBPeriph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->AHBPCENR &= ~RCC_AHBPeriph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB2PeriphClockCmd
|
||||
*
|
||||
* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
|
||||
*
|
||||
* @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
|
||||
* RCC_APB2Periph_AFIO.
|
||||
* RCC_APB2Periph_GPIOA.
|
||||
* RCC_APB2Periph_GPIOB.
|
||||
* RCC_APB2Periph_GPIOC.
|
||||
* RCC_APB2Periph_ADC1.
|
||||
* RCC_APB2Periph_TIM1.
|
||||
* RCC_APB2Periph_SPI1.
|
||||
* RCC_APB2Periph_USART1.
|
||||
* NewState - ENABLE or DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RCC->APB2PCENR |= RCC_APB2Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB2PCENR &= ~RCC_APB2Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB1PeriphClockCmd
|
||||
*
|
||||
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
|
||||
*
|
||||
* @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
|
||||
* RCC_APB1Periph_TIM2.
|
||||
* RCC_APB1Periph_TIM3.
|
||||
* RCC_APB1Periph_WWDG.
|
||||
* RCC_APB1Periph_USART2.
|
||||
* RCC_APB1Periph_USART3.
|
||||
* RCC_APB1Periph_USART4
|
||||
* RCC_APB1Periph_I2C1.
|
||||
* RCC_APB1Periph_PWR.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RCC->APB1PCENR |= RCC_APB1Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB1PCENR &= ~RCC_APB1Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_AHBPeriphResetCmd
|
||||
*
|
||||
* @brief Forces or releases AHB peripheral reset.
|
||||
*
|
||||
* @param RCC_AHBPeriph - specifies the AHB peripheral to reset.
|
||||
* RCC_AHBPeriph_USBFS.
|
||||
* RCC_AHBPeriph_IO2W.
|
||||
* RCC_AHBPeriph_USBPD.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RCC->AHBPCENR |= RCC_AHBPeriph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->AHBPCENR &= ~RCC_AHBPeriph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB2PeriphResetCmd
|
||||
*
|
||||
* @brief Forces or releases APB (APB2) peripheral reset.
|
||||
*
|
||||
* @param RCC_APB2Periph - specifies the APB2 peripheral to reset.
|
||||
* RCC_APB2Periph_AFIO.
|
||||
* RCC_APB2Periph_GPIOA.
|
||||
* RCC_APB2Periph_GPIOB.
|
||||
* RCC_APB2Periph_GPIOC.
|
||||
* RCC_APB2Periph_ADC1.
|
||||
* RCC_APB2Periph_TIM1.
|
||||
* RCC_APB2Periph_SPI1.
|
||||
* RCC_APB2Periph_USART1.
|
||||
* NewState - ENABLE or DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RCC->APB2PRSTR |= RCC_APB2Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB2PRSTR &= ~RCC_APB2Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB1PeriphResetCmd
|
||||
*
|
||||
* @brief Forces or releases APB (APB1) peripheral reset.
|
||||
*
|
||||
* @param RCC_APB1Periph - specifies the APB1 peripheral to reset.
|
||||
* RCC_APB1Periph_TIM2.
|
||||
* RCC_APB1Periph_TIM3.
|
||||
* RCC_APB1Periph_WWDG.
|
||||
* RCC_APB1Periph_USART2.
|
||||
* RCC_APB1Periph_USART3.
|
||||
* RCC_APB1Periph_USART4
|
||||
* RCC_APB1Periph_I2C1.
|
||||
* RCC_APB1Periph_PWR.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
RCC->APB1PRSTR |= RCC_APB1Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB1PRSTR &= ~RCC_APB1Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_MCOConfig
|
||||
*
|
||||
* @brief Selects the clock source to output on MCO pin.
|
||||
*
|
||||
* @param RCC_MCO - specifies the clock source to output.
|
||||
* RCC_MCO_NoClock - No clock selected.
|
||||
* RCC_MCO_SYSCLK - System clock selected.
|
||||
* RCC_MCO_HSI - HSI oscillator clock selected.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_MCOConfig(uint8_t RCC_MCO)
|
||||
{
|
||||
*(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified RCC flag is set or not.
|
||||
*
|
||||
* @param RCC_FLAG - specifies the flag to check.
|
||||
* RCC_FLAG_HSIRDY - HSI oscillator clock ready.
|
||||
* RCC_FLAG_OPARST - OPA reset.
|
||||
* RCC_FLAG_PINRST - Pin reset.
|
||||
* RCC_FLAG_PORRST - POR/PDR reset.
|
||||
* RCC_FLAG_SFTRST - Software reset.
|
||||
* RCC_FLAG_IWDGRST - Independent Watchdog reset.
|
||||
* RCC_FLAG_WWDGRST - Window Watchdog reset.
|
||||
* RCC_FLAG_LPWRRST - Low Power reset.
|
||||
*
|
||||
* @return FlagStatus - SET or RESET.
|
||||
*/
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
uint32_t statusreg = 0;
|
||||
|
||||
FlagStatus bitstatus = RESET;
|
||||
tmp = RCC_FLAG >> 5;
|
||||
|
||||
if (tmp == 1)
|
||||
{
|
||||
statusreg = RCC->CTLR;
|
||||
}
|
||||
else
|
||||
{
|
||||
statusreg = RCC->RSTSCKR;
|
||||
}
|
||||
|
||||
tmp = RCC_FLAG & FLAG_Mask;
|
||||
|
||||
if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_ClearFlag
|
||||
*
|
||||
* @brief Clears the RCC reset flags.
|
||||
* Note-
|
||||
* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
|
||||
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
|
||||
* @return none
|
||||
*/
|
||||
void RCC_ClearFlag(void)
|
||||
{
|
||||
RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
506
Peripheral/src/ch32x035_spi.c
Normal file
506
Peripheral/src/ch32x035_spi.c
Normal file
|
|
@ -0,0 +1,506 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_spi.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the SPI firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_spi.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* SPI SPE mask */
|
||||
#define CTLR1_SPE_Set ((uint16_t)0x0040)
|
||||
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||
|
||||
/* SPI CRCNext mask */
|
||||
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
|
||||
|
||||
/* SPI CRCEN mask */
|
||||
#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
|
||||
#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
|
||||
|
||||
/* SPI SSOE mask */
|
||||
#define CTLR2_SSOE_Set ((uint16_t)0x0004)
|
||||
#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
|
||||
|
||||
/* SPI registers Masks */
|
||||
#define CTLR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_DeInit
|
||||
*
|
||||
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||
{
|
||||
if(SPIx == SPI1)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Init
|
||||
*
|
||||
* @brief Initializes the SPIx peripheral according to the specified
|
||||
* parameters in the SPI_InitStruct.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
|
||||
* contains the configuration information for the specified SPI peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
|
||||
{
|
||||
uint16_t tmpreg = 0;
|
||||
|
||||
tmpreg = SPIx->CTLR1;
|
||||
tmpreg &= CTLR1_CLEAR_Mask;
|
||||
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
|
||||
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
|
||||
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
|
||||
|
||||
SPIx->CTLR1 = tmpreg;
|
||||
SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_StructInit
|
||||
*
|
||||
* @brief Fills each SPI_InitStruct member with its default value.
|
||||
*
|
||||
* @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
|
||||
{
|
||||
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
|
||||
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
|
||||
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
|
||||
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||
/*"SPI_FirstBit_LSB" not support SPI slave mode*/
|
||||
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||
SPI_InitStruct->SPI_CRCPolynomial = 7;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified SPI peripheral.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR1 |= CTLR1_SPE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= CTLR1_SPE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified SPI interrupts.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* SPI_I2S_IT - specifies the SPI interrupt source to be
|
||||
* enabled or disabled.
|
||||
* SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
|
||||
* SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
|
||||
* SPI_I2S_IT_ERR - Error interrupt mask.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||||
{
|
||||
uint16_t itpos = 0, itmask = 0;
|
||||
|
||||
itpos = SPI_I2S_IT >> 4;
|
||||
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR2 |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR2 &= (uint16_t)~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_DMACmd
|
||||
*
|
||||
* @brief Enables or disables the SPIxDMA interface.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* SPI_I2S_DMAReq - specifies the SPI DMA transfer request to
|
||||
* be enabled or disabled.
|
||||
* SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
|
||||
* SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR2 |= SPI_I2S_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_SendData
|
||||
*
|
||||
* @brief Transmits a Data through the SPIx peripheral.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* Data - Data to be transmitted.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
|
||||
{
|
||||
SPIx->DATAR = Data;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ReceiveData
|
||||
*
|
||||
* @brief Returns the most recent received data by the SPIx peripheral.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* Data - Data to be transmitted.
|
||||
*
|
||||
* @return SPIx->DATAR - The value of the received data.
|
||||
*/
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
|
||||
{
|
||||
return SPIx->DATAR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_NSSInternalSoftwareConfig
|
||||
*
|
||||
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* SPI_NSSInternalSoft -
|
||||
* SPI_NSSInternalSoft_Set - Set NSS pin internally.
|
||||
* SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
|
||||
{
|
||||
if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||||
{
|
||||
SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_SSOutputCmd
|
||||
*
|
||||
* @brief Enables or disables the SS output for the selected SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* NewState - new state of the SPIx SS output.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR2 |= CTLR2_SSOE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR2 &= CTLR2_SSOE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_DataSizeConfig
|
||||
*
|
||||
* @brief Configures the data size for the selected SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* SPI_DataSize - specifies the SPI data size.
|
||||
* SPI_DataSize_16b - Set data frame format to 16bit.
|
||||
* SPI_DataSize_8b - Set data frame format to 8bit.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
|
||||
{
|
||||
SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
|
||||
SPIx->CTLR1 |= SPI_DataSize;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_TransmitCRC
|
||||
*
|
||||
* @brief Transmit the SPIx CRC value.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
|
||||
{
|
||||
SPIx->CTLR1 |= CTLR1_CRCNext_Set;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_CalculateCRC
|
||||
*
|
||||
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* NewState - new state of the SPIx CRC value calculation.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
SPIx->CTLR1 |= CTLR1_CRCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_GetCRC
|
||||
*
|
||||
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* SPI_CRC - specifies the CRC register to be read.
|
||||
* SPI_CRC_Tx - Selects Tx CRC register.
|
||||
* SPI_CRC_Rx - Selects Rx CRC register.
|
||||
*
|
||||
* @return crcreg: The selected CRC register value.
|
||||
*/
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
|
||||
{
|
||||
uint16_t crcreg = 0;
|
||||
|
||||
if(SPI_CRC != SPI_CRC_Rx)
|
||||
{
|
||||
crcreg = SPIx->TCRCR;
|
||||
}
|
||||
else
|
||||
{
|
||||
crcreg = SPIx->RCRCR;
|
||||
}
|
||||
|
||||
return crcreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_GetCRCPolynomial
|
||||
*
|
||||
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
*
|
||||
* @return SPIx->CRCR - The CRC Polynomial register value.
|
||||
*/
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
|
||||
{
|
||||
return SPIx->CRCR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_BiDirectionalLineConfig
|
||||
*
|
||||
* @brief Selects the data transfer direction in bi-directional mode
|
||||
* for the specified SPI.
|
||||
*
|
||||
* @param SPIx - where x can be 1 to select the SPI peripheral.
|
||||
* SPI_Direction - specifies the data transfer direction in
|
||||
* bi-directional mode.
|
||||
* SPI_Direction_Tx - Selects Tx transmission direction.
|
||||
* SPI_Direction_Rx - Selects Rx receive direction.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
|
||||
{
|
||||
if(SPI_Direction == SPI_Direction_Tx)
|
||||
{
|
||||
SPIx->CTLR1 |= SPI_Direction_Tx;
|
||||
}
|
||||
else
|
||||
{
|
||||
SPIx->CTLR1 &= SPI_Direction_Rx;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
|
||||
* SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
|
||||
* SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
|
||||
* SPI_I2S_FLAG_BSY - Busy flag.
|
||||
* SPI_I2S_FLAG_OVR - Overrun flag.
|
||||
* SPI_FLAG_MODF - Mode Fault flag.
|
||||
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||
*
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ClearFlag
|
||||
*
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* SPI_I2S_FLAG - specifies the SPI flag to clear.
|
||||
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||
* Note-
|
||||
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||
* operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read
|
||||
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||
* SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a
|
||||
* write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI).
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||
{
|
||||
SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
|
||||
* SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
|
||||
* SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
|
||||
* SPI_I2S_IT_OVR - Overrun interrupt.
|
||||
* SPI_IT_MODF - Mode Fault interrupt.
|
||||
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||
*
|
||||
* @return FlagStatus: SET or RESET.
|
||||
*/
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
itmask = SPI_I2S_IT >> 4;
|
||||
itmask = 0x01 << itmask;
|
||||
enablestatus = (SPIx->CTLR2 & itmask);
|
||||
|
||||
if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SPI_I2S_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||
*
|
||||
* @param SPIx - where x can be
|
||||
* - 1 in SPI mode.
|
||||
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
|
||||
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||
* Note-
|
||||
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||
* sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData())
|
||||
* followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||
* operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||
* a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus())
|
||||
* followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable
|
||||
* the SPI).
|
||||
* @return none
|
||||
*/
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||
{
|
||||
uint16_t itpos = 0;
|
||||
|
||||
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||
SPIx->STATR = (uint16_t)~itpos;
|
||||
}
|
||||
2457
Peripheral/src/ch32x035_tim.c
Normal file
2457
Peripheral/src/ch32x035_tim.c
Normal file
File diff suppressed because it is too large
Load diff
743
Peripheral/src/ch32x035_usart.c
Normal file
743
Peripheral/src/ch32x035_usart.c
Normal file
|
|
@ -0,0 +1,743 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_usart.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the USART firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_usart.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* USART_Private_Defines */
|
||||
#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
|
||||
#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
|
||||
|
||||
#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
|
||||
|
||||
#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
|
||||
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
|
||||
#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
|
||||
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */
|
||||
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
|
||||
|
||||
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
|
||||
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
|
||||
|
||||
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
|
||||
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
|
||||
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
|
||||
|
||||
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
|
||||
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
|
||||
|
||||
#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
|
||||
#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
|
||||
|
||||
#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
|
||||
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
|
||||
|
||||
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
|
||||
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */
|
||||
|
||||
#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
|
||||
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
|
||||
#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
|
||||
#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
|
||||
#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_DeInit
|
||||
*
|
||||
* @brief Deinitializes the USARTx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_DeInit(USART_TypeDef *USARTx)
|
||||
{
|
||||
if(USARTx == USART1)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
|
||||
}
|
||||
else if(USARTx == USART2)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
|
||||
}
|
||||
else if(USARTx == USART3)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
|
||||
}
|
||||
else if(USARTx == USART4)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Init
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral according to the specified
|
||||
* parameters in the USART_InitStruct.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2 , 3 or 4 to select the UART peripheral.
|
||||
* USART_InitStruct - pointer to a USART_InitTypeDef structure
|
||||
* that contains the configuration information for the specified
|
||||
* USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0x00, apbclock = 0x00;
|
||||
uint32_t integerdivider = 0x00;
|
||||
uint32_t fractionaldivider = 0x00;
|
||||
uint32_t usartxbase = 0;
|
||||
RCC_ClocksTypeDef RCC_ClocksStatus;
|
||||
|
||||
if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
|
||||
{
|
||||
}
|
||||
|
||||
usartxbase = (uint32_t)USARTx;
|
||||
tmpreg = USARTx->CTLR2;
|
||||
tmpreg &= CTLR2_STOP_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
|
||||
|
||||
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||
tmpreg = USARTx->CTLR1;
|
||||
tmpreg &= CTLR1_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
|
||||
USART_InitStruct->USART_Mode;
|
||||
USARTx->CTLR1 = (uint16_t)tmpreg;
|
||||
|
||||
tmpreg = USARTx->CTLR3;
|
||||
tmpreg &= CTLR3_CLEAR_Mask;
|
||||
tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
|
||||
USARTx->CTLR3 = (uint16_t)tmpreg;
|
||||
|
||||
RCC_GetClocksFreq(&RCC_ClocksStatus);
|
||||
|
||||
if(usartxbase == USART1_BASE)
|
||||
{
|
||||
apbclock = RCC_ClocksStatus.PCLK2_Frequency;
|
||||
}
|
||||
else
|
||||
{
|
||||
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
|
||||
}
|
||||
|
||||
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
|
||||
tmpreg = (integerdivider / 100) << 4;
|
||||
|
||||
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
|
||||
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
|
||||
|
||||
USARTx->BRR = (uint16_t)tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_StructInit
|
||||
*
|
||||
* @brief Fills each USART_InitStruct member with its default value.
|
||||
*
|
||||
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
USART_InitStruct->USART_BaudRate = 9600;
|
||||
USART_InitStruct->USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStruct->USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStruct->USART_Parity = USART_Parity_No;
|
||||
USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClockInit
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral Clock according to the
|
||||
* specified parameters in the USART_ClockInitStruct .
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
|
||||
* structure that contains the configuration information for the specified
|
||||
* USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
|
||||
tmpreg = USARTx->CTLR2;
|
||||
tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
|
||||
USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
|
||||
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClockStructInit
|
||||
*
|
||||
* @brief Fills each USART_ClockStructInit member with its default value.
|
||||
*
|
||||
* @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
|
||||
* structure which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
|
||||
USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
|
||||
USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
|
||||
USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified USART peripheral.
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_UE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_UE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified USART interrupts.
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_IT - specifies the USART interrupt sources to be enabled or disabled.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TXE - Transmit Data Register empty interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* USART_IT_IDLE - Idle line detection interrupt.
|
||||
* USART_IT_PE - Parity Error interrupt.
|
||||
* USART_IT_ERR - Error interrupt.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
|
||||
{
|
||||
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
|
||||
uint32_t usartxbase = 0x00;
|
||||
|
||||
|
||||
usartxbase = (uint32_t)USARTx;
|
||||
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||
itpos = USART_IT & IT_Mask;
|
||||
itmask = (((uint32_t)0x01) << itpos);
|
||||
|
||||
if(usartreg == 0x01)
|
||||
{
|
||||
usartxbase += 0x0C;
|
||||
}
|
||||
else if(usartreg == 0x02)
|
||||
{
|
||||
usartxbase += 0x10;
|
||||
}
|
||||
else
|
||||
{
|
||||
usartxbase += 0x14;
|
||||
}
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
*(__IO uint32_t *)usartxbase |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(__IO uint32_t *)usartxbase &= ~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_DMACmd
|
||||
*
|
||||
* @brief Enables or disables the USART DMA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_DMAReq - specifies the DMA request.
|
||||
* USART_DMAReq_Tx - USART DMA transmit request.
|
||||
* USART_DMAReq_Rx - USART DMA receive request.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= USART_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetAddress
|
||||
*
|
||||
* @brief Sets the address of the USART node.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_Address - Indicates the address of the USART node.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_Address_Mask;
|
||||
USARTx->CTLR2 |= USART_Address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_WakeUpConfig
|
||||
*
|
||||
* @brief Selects the USART WakeUp method.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_WakeUp - specifies the USART wakeup method.
|
||||
* USART_WakeUp_IdleLine - WakeUp by an idle line detection.
|
||||
* USART_WakeUp_AddressMark - WakeUp by an address mark.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_WAKE_Mask;
|
||||
USARTx->CTLR1 |= USART_WakeUp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ReceiverWakeUpCmd
|
||||
*
|
||||
* @brief Determines if the USART is in mute mode or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_RWU_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_RWU_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_LINBreakDetectLengthConfig
|
||||
*
|
||||
* @brief Sets the USART LIN Break detection length.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_LINBreakDetectLength - specifies the LIN break detection length.
|
||||
* USART_LINBreakDetectLength_10b - 10-bit break detection.
|
||||
* USART_LINBreakDetectLength_11b - 11-bit break detection.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_LBDL_Mask;
|
||||
USARTx->CTLR2 |= USART_LINBreakDetectLength;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_LINCmd
|
||||
*
|
||||
* @brief Enables or disables the USART LIN mode.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR2 |= CTLR2_LINEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_LINEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SendData
|
||||
*
|
||||
* @brief Transmits single data through the USARTx peripheral.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* Data - the data to transmit.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
|
||||
{
|
||||
USARTx->DATAR = (Data & (uint16_t)0x01FF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ReceiveData
|
||||
*
|
||||
* @brief Returns the most recent received data by the USARTx peripheral.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
*
|
||||
* @return The received data.
|
||||
*/
|
||||
uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
|
||||
{
|
||||
return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SendBreak
|
||||
*
|
||||
* @brief Transmits break characters.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SendBreak(USART_TypeDef *USARTx)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_SBK_Set;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetGuardTime
|
||||
*
|
||||
* @brief Sets the specified USART guard time.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_GuardTime - specifies the guard time.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
|
||||
{
|
||||
USARTx->GPR &= GPR_LSB_Mask;
|
||||
USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetPrescaler
|
||||
*
|
||||
* @brief Sets the system clock prescaler.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_Prescaler - specifies the prescaler clock.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
|
||||
{
|
||||
USARTx->GPR &= GPR_MSB_Mask;
|
||||
USARTx->GPR |= USART_Prescaler;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SmartCardCmd
|
||||
*
|
||||
* @brief Enables or disables the USART Smart Card mode.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_SCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_SCEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SmartCardNACKCmd
|
||||
*
|
||||
* @brief Enables or disables NACK transmission.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_NACK_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_NACK_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_HalfDuplexCmd
|
||||
*
|
||||
* @brief Enables or disables the USART Half Duplex communication.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_HDSEL_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_IrDAConfig
|
||||
*
|
||||
* @brief Configures the USART's IrDA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_IrDAMode - specifies the IrDA mode.
|
||||
* USART_IrDAMode_LowPower.
|
||||
* USART_IrDAMode_Normal.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_IRLP_Mask;
|
||||
USARTx->CTLR3 |= USART_IrDAMode;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_IrDACmd
|
||||
*
|
||||
* @brief Enables or disables the USART's IrDA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_IREN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_IREN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified USART flag is set or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_FLAG - specifies the flag to check.
|
||||
* USART_FLAG_LBD - LIN Break detection flag.
|
||||
* USART_FLAG_TXE - Transmit data register empty flag.
|
||||
* USART_FLAG_TC - Transmission Complete flag.
|
||||
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||
* USART_FLAG_IDLE - Idle Line detection flag.
|
||||
* USART_FLAG_ORE - OverRun Error flag.
|
||||
* USART_FLAG_NE - Noise Error flag.
|
||||
* USART_FLAG_FE - Framing Error flag.
|
||||
* USART_FLAG_PE - Parity Error flag.
|
||||
*
|
||||
* @return bitstatus: SET or RESET
|
||||
*/
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
|
||||
if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClearFlag
|
||||
*
|
||||
* @brief Clears the USARTx's pending flags.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_FLAG - specifies the flag to clear.
|
||||
* USART_FLAG_LBD - LIN Break detection flag.
|
||||
* USART_FLAG_TC - Transmission Complete flag.
|
||||
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||
* Note-
|
||||
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||
* sequence: a read operation to USART_STATR register (USART_GetFlagStatus())
|
||||
* followed by a read operation to USART_DATAR register (USART_ReceiveData()).
|
||||
* - RXNE flag can be also cleared by a read to the USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_STATR register (USART_GetFlagStatus()) followed by a write operation
|
||||
* to USART_DATAR register (USART_SendData()).
|
||||
* - TXE flag is cleared only by a write to the USART_DATAR register
|
||||
* (USART_SendData()).
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||
{
|
||||
|
||||
USARTx->STATR = (uint16_t)~USART_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified USART interrupt has occurred or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_IT - specifies the USART interrupt source to check.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TXE - Tansmit Data Register empty interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* USART_IT_IDLE - Idle line detection interrupt.
|
||||
* USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
|
||||
* USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
|
||||
* USART_IT_NE - Noise Error interrupt.
|
||||
* USART_IT_FE - Framing Error interrupt.
|
||||
* USART_IT_PE - Parity Error interrupt.
|
||||
*
|
||||
* @return bitstatus: SET or RESET.
|
||||
*/
|
||||
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||
{
|
||||
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||
itmask = USART_IT & IT_Mask;
|
||||
itmask = (uint32_t)0x01 << itmask;
|
||||
|
||||
if(usartreg == 0x01)
|
||||
{
|
||||
itmask &= USARTx->CTLR1;
|
||||
}
|
||||
else if(usartreg == 0x02)
|
||||
{
|
||||
itmask &= USARTx->CTLR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
itmask &= USARTx->CTLR3;
|
||||
}
|
||||
|
||||
bitpos = USART_IT >> 0x08;
|
||||
bitpos = (uint32_t)0x01 << bitpos;
|
||||
bitpos &= USARTx->STATR;
|
||||
|
||||
if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the USARTx's interrupt pending bits.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 or 4 to select the USART peripheral.
|
||||
* USART_IT - specifies the interrupt pending bit to clear.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* Note-
|
||||
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) pending bits are cleared by
|
||||
* software sequence: a read operation to USART_STATR register
|
||||
* (USART_GetITStatus()) followed by a read operation to USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - RXNE pending bit can be also cleared by a read to the USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - TC pending bit can be also cleared by software sequence: a read
|
||||
* operation to USART_STATR register (USART_GetITStatus()) followed by a write
|
||||
* operation to USART_DATAR register (USART_SendData()).
|
||||
* - TXE pending bit is cleared only by a write to the USART_DATAR register
|
||||
* (USART_SendData()).
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||
{
|
||||
uint16_t bitpos = 0x00, itmask = 0x00;
|
||||
|
||||
bitpos = USART_IT >> 0x08;
|
||||
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
|
||||
USARTx->STATR = (uint16_t)~itmask;
|
||||
}
|
||||
141
Peripheral/src/ch32x035_wwdg.c
Normal file
141
Peripheral/src/ch32x035_wwdg.c
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_wwdg.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file provides all the WWDG firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_wwdg.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
|
||||
|
||||
/* CFGR register bit mask */
|
||||
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
|
||||
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_Mask ((uint8_t)0x7F)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_DeInit
|
||||
*
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_SetPrescaler
|
||||
*
|
||||
* @brief Sets the WWDG Prescaler
|
||||
*
|
||||
* @param WWDG_Prescaler - specifies the WWDG Prescaler
|
||||
* WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
|
||||
* WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
|
||||
* WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
|
||||
* WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
|
||||
tmpreg |= WWDG_Prescaler;
|
||||
WWDG->CFGR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_SetWindowValue
|
||||
*
|
||||
* @brief Sets the WWDG window value
|
||||
*
|
||||
* @param WindowValue - specifies the window value to be compared to the
|
||||
* downcounter,which must be lower than 0x80
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = WWDG->CFGR & CFGR_W_Mask;
|
||||
|
||||
tmpreg |= WindowValue & (uint32_t)BIT_Mask;
|
||||
|
||||
WWDG->CFGR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_EnableIT
|
||||
*
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI)
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_EnableIT(void)
|
||||
{
|
||||
WWDG->CFGR |= (1 << 9);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_SetCounter
|
||||
*
|
||||
* @brief Sets the WWDG counter value
|
||||
*
|
||||
* @param Counter - specifies the watchdog counter value,which must be a
|
||||
* number between 0x40 and 0x7F
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
WWDG->CTLR = Counter & BIT_Mask;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_Enable
|
||||
*
|
||||
* @brief Enables WWDG and load the counter value
|
||||
*
|
||||
* @param Counter - specifies the watchdog counter value,which must be a
|
||||
* number between 0x40 and 0x7F
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
WWDG->CTLR = CTLR_WDGA_Set | Counter;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not
|
||||
*
|
||||
* @return The new state of the Early Wakeup interrupt flag (SET or RESET)
|
||||
*/
|
||||
FlagStatus WWDG_GetFlagStatus(void)
|
||||
{
|
||||
return (FlagStatus)(WWDG->STATR);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn WWDG_ClearFlag
|
||||
*
|
||||
* @brief Clears Early Wakeup interrupt flag
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void WWDG_ClearFlag(void)
|
||||
{
|
||||
WWDG->STATR = (uint32_t)RESET;
|
||||
}
|
||||
227
Startup/startup_ch32x035.S
Normal file
227
Startup/startup_ch32x035.S
Normal file
|
|
@ -0,0 +1,227 @@
|
|||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_ch32x035.s
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.1
|
||||
;* Date : 2023/11/11
|
||||
;* Description : vector table for eclipse toolchain.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
;*******************************************************************************/
|
||||
|
||||
.section .init,"ax",@progbits
|
||||
.global _start
|
||||
.align 1
|
||||
_start:
|
||||
j handle_reset
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 1
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
.word _start
|
||||
.word 0
|
||||
.word NMI_Handler /* NMI */
|
||||
.word HardFault_Handler /* Hard Fault */
|
||||
.word 0
|
||||
.word Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.word 0
|
||||
.word 0
|
||||
.word Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.word Break_Point_Handler /* Break Point */
|
||||
.word 0
|
||||
.word 0
|
||||
.word SysTick_Handler /* SysTick */
|
||||
.word 0
|
||||
.word SW_Handler /* SW */
|
||||
.word 0
|
||||
/* External Interrupts */
|
||||
.word WWDG_IRQHandler /* Window Watchdog */
|
||||
.word PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.word FLASH_IRQHandler /* Flash */
|
||||
.word 0
|
||||
.word EXTI7_0_IRQHandler /* EXTI Line 7..0 */
|
||||
.word AWU_IRQHandler /* Auto Wake up */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.word ADC1_IRQHandler /* ADC1 */
|
||||
.word I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.word TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.word TIM2_UP_IRQHandler /* TIM2 Update */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word EXTI15_8_IRQHandler /* EXTI Line 15..8 */
|
||||
.word EXTI25_16_IRQHandler /* EXTI Line 25..16 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word USART4_IRQHandler /* USART4 */
|
||||
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
.word USBFS_IRQHandler /* USBFS Break */
|
||||
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
|
||||
.word PIOC_IRQHandler /* PIOC */
|
||||
.word OPA_IRQHandler /* OPA */
|
||||
.word USBPD_IRQHandler /* USBPD */
|
||||
.word USBPDWakeUp_IRQHandler /* USBPD Wake up */
|
||||
.word TIM2_CC_IRQHandler /* TIM2 Capture Compare */
|
||||
.word TIM2_TRG_COM_IRQHandler /* TIM2 Trigger and Commutation */
|
||||
.word TIM2_BRK_IRQHandler /* TIM2 Break */
|
||||
.word TIM3_IRQHandler /* TIM3 */
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler /* NMI */
|
||||
.weak HardFault_Handler /* Hard Fault */
|
||||
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
|
||||
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
|
||||
.weak Break_Point_Handler /* Break Point */
|
||||
.weak SysTick_Handler /* SysTick */
|
||||
.weak SW_Handler /* SW */
|
||||
.weak WWDG_IRQHandler /* Window Watchdog */
|
||||
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
.weak FLASH_IRQHandler /* Flash */
|
||||
.weak EXTI7_0_IRQHandler /* EXTI Line 7..0 */
|
||||
.weak AWU_IRQHandler /* Auto Wake up */
|
||||
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.weak ADC1_IRQHandler /* ADC1 */
|
||||
.weak I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
.weak I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
.weak USART1_IRQHandler /* USART1 */
|
||||
.weak SPI1_IRQHandler /* SPI1 */
|
||||
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
.weak TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
.weak TIM2_UP_IRQHandler /* TIM2 Update */
|
||||
.weak USART2_IRQHandler /* USART2 */
|
||||
.weak EXTI15_8_IRQHandler /* EXTI Line 15..8 */
|
||||
.weak EXTI25_16_IRQHandler /* EXTI Line 25..16 */
|
||||
.weak USART3_IRQHandler /* USART3 */
|
||||
.weak USART4_IRQHandler /* USART4 */
|
||||
.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
|
||||
.weak USBFS_IRQHandler /* USBFS Break */
|
||||
.weak USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
|
||||
.weak PIOC_IRQHandler /* PIOC */
|
||||
.weak OPA_IRQHandler /* OPA */
|
||||
.weak USBPD_IRQHandler /* USBPD */
|
||||
.weak USBPDWakeUp_IRQHandler /* USBPD Wake up */
|
||||
.weak TIM2_CC_IRQHandler /* TIM2 Capture Compare */
|
||||
.weak TIM2_TRG_COM_IRQHandler /* TIM2 Trigger and Commutation */
|
||||
.weak TIM2_BRK_IRQHandler /* TIM2 Break */
|
||||
.weak TIM3_IRQHandler /* TIM3 */
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
Ecall_M_Mode_Handler:
|
||||
Ecall_U_Mode_Handler:
|
||||
Break_Point_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
WWDG_IRQHandler:
|
||||
PVD_IRQHandler:
|
||||
FLASH_IRQHandler:
|
||||
EXTI7_0_IRQHandler:
|
||||
AWU_IRQHandler:
|
||||
DMA1_Channel1_IRQHandler:
|
||||
DMA1_Channel2_IRQHandler:
|
||||
DMA1_Channel3_IRQHandler:
|
||||
DMA1_Channel4_IRQHandler:
|
||||
DMA1_Channel5_IRQHandler:
|
||||
DMA1_Channel6_IRQHandler:
|
||||
DMA1_Channel7_IRQHandler:
|
||||
ADC1_IRQHandler:
|
||||
I2C1_EV_IRQHandler:
|
||||
I2C1_ER_IRQHandler:
|
||||
USART1_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
TIM1_BRK_IRQHandler:
|
||||
TIM1_UP_IRQHandler:
|
||||
TIM1_TRG_COM_IRQHandler:
|
||||
TIM1_CC_IRQHandler:
|
||||
TIM2_UP_IRQHandler:
|
||||
USART2_IRQHandler:
|
||||
EXTI15_8_IRQHandler:
|
||||
EXTI25_16_IRQHandler:
|
||||
USART3_IRQHandler:
|
||||
USART4_IRQHandler:
|
||||
DMA1_Channel8_IRQHandler:
|
||||
USBFS_IRQHandler:
|
||||
USBFSWakeUp_IRQHandler:
|
||||
PIOC_IRQHandler:
|
||||
OPA_IRQHandler:
|
||||
USBPD_IRQHandler:
|
||||
USBPDWakeUp_IRQHandler:
|
||||
TIM2_CC_IRQHandler:
|
||||
TIM2_TRG_COM_IRQHandler:
|
||||
TIM2_BRK_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
1:
|
||||
la sp, _eusrstack
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
/* Configure pipelining and instruction prediction */
|
||||
li t0, 0x1f
|
||||
csrw 0xbc0, t0
|
||||
/* Enable interrupt nesting and hardware stack */
|
||||
li t0, 0x3
|
||||
csrw 0x804, t0
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x88
|
||||
csrs mstatus, t0
|
||||
/* Configure the interrupt vector table recognition mode and entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 3
|
||||
csrw mtvec, t0
|
||||
|
||||
jal SystemInit
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
|
||||
|
||||
39
User/ch32x035_conf.h
Normal file
39
User/ch32x035_conf.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_conf.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : Library configuration file.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_CONF_H
|
||||
#define __CH32X035_CONF_H
|
||||
|
||||
#include "ch32x035_adc.h"
|
||||
#include "ch32x035_awu.h"
|
||||
#include "ch32x035_dbgmcu.h"
|
||||
#include "ch32x035_dma.h"
|
||||
#include "ch32x035_exti.h"
|
||||
#include "ch32x035_flash.h"
|
||||
#include "ch32x035_gpio.h"
|
||||
#include "ch32x035_i2c.h"
|
||||
#include "ch32x035_iwdg.h"
|
||||
#include "ch32x035_pwr.h"
|
||||
#include "ch32x035_rcc.h"
|
||||
#include "ch32x035_spi.h"
|
||||
#include "ch32x035_tim.h"
|
||||
#include "ch32x035_usart.h"
|
||||
#include "ch32x035_wwdg.h"
|
||||
#include "ch32x035_it.h"
|
||||
#include "ch32x035_misc.h"
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
42
User/ch32x035_it.c
Normal file
42
User/ch32x035_it.c
Normal file
|
|
@ -0,0 +1,42 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_it.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : Main Interrupt Service Routines.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035_it.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NMI_Handler
|
||||
*
|
||||
* @brief This function handles NMI exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn HardFault_Handler
|
||||
*
|
||||
* @brief This function handles Hard Fault exception.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while (1)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
20
User/ch32x035_it.h
Normal file
20
User/ch32x035_it.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32x035_it.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : This file contains the headers of the interrupt handlers.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32X035_IT_H
|
||||
#define __CH32X035_IT_H
|
||||
|
||||
#include "debug.h"
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
41
User/main.c
Normal file
41
User/main.c
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
#include "debug.h"
|
||||
|
||||
void GPIO_LED_Init(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
int main(void)
|
||||
{
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
|
||||
SystemCoreClockUpdate();
|
||||
Delay_Init();
|
||||
|
||||
#if (SDI_PRINT == SDI_PR_OPEN)
|
||||
SDI_Printf_Enable();
|
||||
#else
|
||||
USART_Printf_Init(115200);
|
||||
#endif
|
||||
|
||||
printf("SystemClk: %ld\r\n", SystemCoreClock);
|
||||
printf("DeviceID: %08lx\r\n", DBGMCU_GetDEVID());
|
||||
printf("ChipID: %08lx\r\n", DBGMCU_GetCHIPID());
|
||||
|
||||
GPIO_LED_Init();
|
||||
|
||||
while(1)
|
||||
{
|
||||
Delay_Ms(1000);
|
||||
printf("On\r\n");
|
||||
GPIO_WriteBit(GPIOA, GPIO_Pin_0, Bit_SET);
|
||||
Delay_Ms(1000);
|
||||
printf("Off\r\n");
|
||||
GPIO_WriteBit(GPIOA, GPIO_Pin_0, Bit_RESET);
|
||||
}
|
||||
}
|
||||
241
User/system_ch32x035.c
Normal file
241
User/system_ch32x035.c
Normal file
|
|
@ -0,0 +1,241 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32x035.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : CH32X035 Device Peripheral Access Layer System Source File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32x035.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
*/
|
||||
|
||||
//#define SYSCLK_FREQ_8MHz_HSI 8000000
|
||||
//#define SYSCLK_FREQ_12MHz_HSI 12000000
|
||||
//#define SYSCLK_FREQ_16MHz_HSI 16000000
|
||||
//#define SYSCLK_FREQ_24MHz_HSI 24000000
|
||||
#define SYSCLK_FREQ_48MHz_HSI HSI_VALUE
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_8MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_12MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_12MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_16MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_24MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
|
||||
|
||||
|
||||
/* system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_8MHz_HSI
|
||||
static void SetSysClockTo8_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_12MHz_HSI
|
||||
static void SetSysClockTo12_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_16MHz_HSI
|
||||
static void SetSysClockTo16_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_24MHz_HSI
|
||||
static void SetSysClockTo24_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 |= (uint32_t)0x00000050;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FFFF5F;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
|
||||
if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8)
|
||||
{
|
||||
SystemCoreClock /= tmp;
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
// GPIO_IPD_Unused();
|
||||
|
||||
#ifdef SYSCLK_FREQ_8MHz_HSI
|
||||
SetSysClockTo8_HSI();
|
||||
#elif defined SYSCLK_FREQ_12MHz_HSI
|
||||
SetSysClockTo12_HSI();
|
||||
#elif defined SYSCLK_FREQ_16MHz_HSI
|
||||
SetSysClockTo16_HSI();
|
||||
#elif defined SYSCLK_FREQ_24MHz_HSI
|
||||
SetSysClockTo24_HSI();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#ifdef SYSCLK_FREQ_8MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo8_HSI
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo8_HSI(void)
|
||||
{
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK = APB1 */
|
||||
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV6;
|
||||
|
||||
/* Flash 0 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_12MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo12_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 12MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo12_HSI(void)
|
||||
{
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK = APB1 */
|
||||
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV4;
|
||||
|
||||
/* Flash 0 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_16MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo16_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 16MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo16_HSI(void)
|
||||
{
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK = APB1 */
|
||||
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3;
|
||||
|
||||
/* Flash 0 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_24MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo24_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 24MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo24_HSI(void)
|
||||
{
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK = APB1 */
|
||||
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
|
||||
|
||||
/* Flash 1 wait state */
|
||||
FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK = APB1 */
|
||||
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
32
User/system_ch32x035.h
Normal file
32
User/system_ch32x035.h
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32x035.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2023/04/06
|
||||
* Description : CH32X035 Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_CH32X035_H
|
||||
#define __SYSTEM_CH32X035_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
Loading…
Reference in a new issue