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Logan G 2024-03-21 20:13:22 -06:00
parent 5f3e781619
commit 81afcad3e9
Signed by: logan
GPG key ID: E328528C921E7A7A
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614
Core/core_riscv.c
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@ -1,307 +1,307 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.c * File Name : core_riscv.c
* Author : WCH * Author : WCH
* Version : V1.0.1 * Version : V1.0.1
* Date : 2023/11/11 * Date : 2023/11/11
* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32X035 * Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32X035
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include <stdint.h> #include <stdint.h>
/* define compiler specific symbols */ /* define compiler specific symbols */
#if defined ( __CC_ARM ) #if defined ( __CC_ARM )
#define __ASM __asm /* asm keyword for ARM Compiler */ #define __ASM __asm /* asm keyword for ARM Compiler */
#define __INLINE __inline /* inline keyword for ARM Compiler */ #define __INLINE __inline /* inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ ) #elif defined ( __ICCARM__ )
#define __ASM __asm /* asm keyword for IAR Compiler */ #define __ASM __asm /* asm keyword for IAR Compiler */
#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ ) #elif defined ( __GNUC__ )
#define __ASM __asm /* asm keyword for GNU Compiler */ #define __ASM __asm /* asm keyword for GNU Compiler */
#define __INLINE inline /* inline keyword for GNU Compiler */ #define __INLINE inline /* inline keyword for GNU Compiler */
#elif defined ( __TASKING__ ) #elif defined ( __TASKING__ )
#define __ASM __asm /* asm keyword for TASKING Compiler */ #define __ASM __asm /* asm keyword for TASKING Compiler */
#define __INLINE inline /* inline keyword for TASKING Compiler */ #define __INLINE inline /* inline keyword for TASKING Compiler */
#endif #endif
/********************************************************************* /*********************************************************************
* @fn __get_MSTATUS * @fn __get_MSTATUS
* *
* @brief Return the Machine Status Register * @brief Return the Machine Status Register
* *
* @return mstatus value * @return mstatus value
*/ */
uint32_t __get_MSTATUS(void) uint32_t __get_MSTATUS(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_MSTATUS * @fn __set_MSTATUS
* *
* @brief Set the Machine Status Register * @brief Set the Machine Status Register
* *
* @param value - set mstatus value * @param value - set mstatus value
* *
* @return none * @return none
*/ */
void __set_MSTATUS(uint32_t value) void __set_MSTATUS(uint32_t value)
{ {
__ASM volatile ("csrw mstatus, %0" : : "r" (value) ); __ASM volatile ("csrw mstatus, %0" : : "r" (value) );
} }
/********************************************************************* /*********************************************************************
* @fn __get_MISA * @fn __get_MISA
* *
* @brief Return the Machine ISA Register * @brief Return the Machine ISA Register
* *
* @return misa value * @return misa value
*/ */
uint32_t __get_MISA(void) uint32_t __get_MISA(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "misa" : "=r" (result) ); __ASM volatile ( "csrr %0," "misa" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_MISA * @fn __set_MISA
* *
* @brief Set the Machine ISA Register * @brief Set the Machine ISA Register
* *
* @param value - set misa value * @param value - set misa value
* *
* @return none * @return none
*/ */
void __set_MISA(uint32_t value) void __set_MISA(uint32_t value)
{ {
__ASM volatile ("csrw misa, %0" : : "r" (value) ); __ASM volatile ("csrw misa, %0" : : "r" (value) );
} }
/********************************************************************* /*********************************************************************
* @fn __get_MTVEC * @fn __get_MTVEC
* *
* @brief Return the Machine Trap-Vector Base-Address Register * @brief Return the Machine Trap-Vector Base-Address Register
* *
* @return mtvec value * @return mtvec value
*/ */
uint32_t __get_MTVEC(void) uint32_t __get_MTVEC(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_MTVEC * @fn __set_MTVEC
* *
* @brief Set the Machine Trap-Vector Base-Address Register * @brief Set the Machine Trap-Vector Base-Address Register
* *
* @param value - set mtvec value * @param value - set mtvec value
* *
* @return none * @return none
*/ */
void __set_MTVEC(uint32_t value) void __set_MTVEC(uint32_t value)
{ {
__ASM volatile ("csrw mtvec, %0" : : "r" (value) ); __ASM volatile ("csrw mtvec, %0" : : "r" (value) );
} }
/********************************************************************* /*********************************************************************
* @fn __get_MSCRATCH * @fn __get_MSCRATCH
* *
* @brief Return the Machine Seratch Register * @brief Return the Machine Seratch Register
* *
* @return mscratch value * @return mscratch value
*/ */
uint32_t __get_MSCRATCH(void) uint32_t __get_MSCRATCH(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_MSCRATCH * @fn __set_MSCRATCH
* *
* @brief Set the Machine Seratch Register * @brief Set the Machine Seratch Register
* *
* @param value - set mscratch value * @param value - set mscratch value
* *
* @return none * @return none
*/ */
void __set_MSCRATCH(uint32_t value) void __set_MSCRATCH(uint32_t value)
{ {
__ASM volatile ("csrw mscratch, %0" : : "r" (value) ); __ASM volatile ("csrw mscratch, %0" : : "r" (value) );
} }
/********************************************************************* /*********************************************************************
* @fn __get_MEPC * @fn __get_MEPC
* *
* @brief Return the Machine Exception Program Register * @brief Return the Machine Exception Program Register
* *
* @return mepc value * @return mepc value
*/ */
uint32_t __get_MEPC(void) uint32_t __get_MEPC(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); __ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_MEPC * @fn __set_MEPC
* *
* @brief Set the Machine Exception Program Register * @brief Set the Machine Exception Program Register
* *
* @return mepc value * @return mepc value
*/ */
void __set_MEPC(uint32_t value) void __set_MEPC(uint32_t value)
{ {
__ASM volatile ("csrw mepc, %0" : : "r" (value) ); __ASM volatile ("csrw mepc, %0" : : "r" (value) );
} }
/********************************************************************* /*********************************************************************
* @fn __get_MCAUSE * @fn __get_MCAUSE
* *
* @brief Return the Machine Cause Register * @brief Return the Machine Cause Register
* *
* @return mcause value * @return mcause value
*/ */
uint32_t __get_MCAUSE(void) uint32_t __get_MCAUSE(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); __ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_MEPC * @fn __set_MEPC
* *
* @brief Set the Machine Cause Register * @brief Set the Machine Cause Register
* *
* @return mcause value * @return mcause value
*/ */
void __set_MCAUSE(uint32_t value) void __set_MCAUSE(uint32_t value)
{ {
__ASM volatile ("csrw mcause, %0" : : "r" (value) ); __ASM volatile ("csrw mcause, %0" : : "r" (value) );
} }
/********************************************************************* /*********************************************************************
* @fn __get_MTVAL * @fn __get_MTVAL
* *
* @brief Return the Machine Trap Value Register * @brief Return the Machine Trap Value Register
* *
* @return mtval value * @return mtval value
*/ */
uint32_t __get_MTVAL(void) uint32_t __get_MTVAL(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); __ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_MTVAL * @fn __set_MTVAL
* *
* @brief Set the Machine Trap Value Register * @brief Set the Machine Trap Value Register
* *
* @return mtval value * @return mtval value
*/ */
void __set_MTVAL(uint32_t value) void __set_MTVAL(uint32_t value)
{ {
__ASM volatile ("csrw mtval, %0" : : "r" (value) ); __ASM volatile ("csrw mtval, %0" : : "r" (value) );
} }
/********************************************************************* /*********************************************************************
* @fn __get_MVENDORID * @fn __get_MVENDORID
* *
* @brief Return Vendor ID Register * @brief Return Vendor ID Register
* *
* @return mvendorid value * @return mvendorid value
*/ */
uint32_t __get_MVENDORID(void) uint32_t __get_MVENDORID(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __get_MARCHID * @fn __get_MARCHID
* *
* @brief Return Machine Architecture ID Register * @brief Return Machine Architecture ID Register
* *
* @return marchid value * @return marchid value
*/ */
uint32_t __get_MARCHID(void) uint32_t __get_MARCHID(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); __ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __get_MIMPID * @fn __get_MIMPID
* *
* @brief Return Machine Implementation ID Register * @brief Return Machine Implementation ID Register
* *
* @return mimpid value * @return mimpid value
*/ */
uint32_t __get_MIMPID(void) uint32_t __get_MIMPID(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __get_MHARTID * @fn __get_MHARTID
* *
* @brief Return Hart ID Register * @brief Return Hart ID Register
* *
* @return mhartid value * @return mhartid value
*/ */
uint32_t __get_MHARTID(void) uint32_t __get_MHARTID(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __get_SP * @fn __get_SP
* *
* @brief Return SP Register * @brief Return SP Register
* *
* @return SP value * @return SP value
*/ */
uint32_t __get_SP(void) uint32_t __get_SP(void)
{ {
uint32_t result; uint32_t result;
__ASM volatile ( "mv %0," "sp" : "=r"(result) : ); __ASM volatile ( "mv %0," "sp" : "=r"(result) : );
return (result); return (result);
} }

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Core/core_riscv.h
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Debug/debug.c
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/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : debug.c * File Name : debug.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for UART * Description : This file contains all the functions prototypes for UART
* Printf , Delay functions. * Printf , Delay functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "debug.h" #include "debug.h"
static uint8_t p_us = 0; static uint8_t p_us = 0;
static uint16_t p_ms = 0; static uint16_t p_ms = 0;
#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) #define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380)
#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) #define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384)
/********************************************************************* /*********************************************************************
* @fn Delay_Init * @fn Delay_Init
* *
* @brief Initializes Delay Funcation. * @brief Initializes Delay Funcation.
* *
* @return none * @return none
*/ */
void Delay_Init(void) void Delay_Init(void)
{ {
p_us = SystemCoreClock / 8000000; p_us = SystemCoreClock / 8000000;
p_ms = (uint16_t)p_us * 1000; p_ms = (uint16_t)p_us * 1000;
SysTick->CTLR &= ~0x8000001F; SysTick->CTLR &= ~0x8000001F;
SysTick->CTLR |= (1 << 0); SysTick->CTLR |= (1 << 0);
} }
uint64_t SysTick_Read(void) uint64_t SysTick_Read(void)
{ {
uint64_t ticks; uint64_t ticks;
SysTick->CTLR &= ~(1 << 0); SysTick->CTLR &= ~(1 << 0);
ticks = SysTick->CNT; ticks = SysTick->CNT;
SysTick->CTLR |= (1 << 0); SysTick->CTLR |= (1 << 0);
return ticks; return ticks;
} }
uint64_t SysTick_Us(void) uint64_t SysTick_Us(void)
{ {
return SysTick_Read() / p_us; return SysTick_Read() / p_us;
} }
uint64_t SysTick_Ms(void) uint64_t SysTick_Ms(void)
{ {
return SysTick_Read() / p_ms; return SysTick_Read() / p_ms;
} }
/********************************************************************* /*********************************************************************
* @fn Delay_Us * @fn Delay_Us
* *
* @brief Microsecond Delay Time. * @brief Microsecond Delay Time.
* *
* @param n - Microsecond number. * @param n - Microsecond number.
* *
* @return None * @return None
*/ */
void Delay_Us(uint32_t n) void Delay_Us(uint32_t n)
{ {
uint32_t i; uint32_t i;
SysTick->SR &= ~(1 << 0); SysTick->SR &= ~(1 << 0);
i = (uint32_t)n * p_us; i = (uint32_t)n * p_us;
SysTick->CMP = SysTick_Read() + i; SysTick->CMP = SysTick_Read() + i;
while((SysTick->SR & (1 << 0)) != (1 << 0)); while((SysTick->SR & (1 << 0)) != (1 << 0));
/* /*
SysTick->CMP = i; SysTick->CMP = i;
SysTick->CTLR |= (1 << 4); SysTick->CTLR |= (1 << 4);
SysTick->CTLR |= (1 << 5) | (1 << 0); SysTick->CTLR |= (1 << 5) | (1 << 0);
while((SysTick->SR & (1 << 0)) != (1 << 0)); while((SysTick->SR & (1 << 0)) != (1 << 0));
SysTick->CTLR &= ~(1 << 0); SysTick->CTLR &= ~(1 << 0);
*/ */
} }
/********************************************************************* /*********************************************************************
* @fn Delay_Ms * @fn Delay_Ms
* *
* @brief Millisecond Delay Time. * @brief Millisecond Delay Time.
* *
* @param n - Millisecond number. * @param n - Millisecond number.
* *
* @return None * @return None
*/ */
void Delay_Ms(uint32_t n) void Delay_Ms(uint32_t n)
{ {
uint32_t i; uint32_t i;
SysTick->SR &= ~(1 << 0); SysTick->SR &= ~(1 << 0);
i = (uint32_t)n * p_ms; i = (uint32_t)n * p_ms;
SysTick->CMP = SysTick_Read() + i; SysTick->CMP = SysTick_Read() + i;
while((SysTick->SR & (1 << 0)) != (1 << 0)); while((SysTick->SR & (1 << 0)) != (1 << 0));
/* /*
SysTick->CMP = i; SysTick->CMP = i;
SysTick->CTLR |= (1 << 4); SysTick->CTLR |= (1 << 4);
SysTick->CTLR |= (1 << 5) | (1 << 0); SysTick->CTLR |= (1 << 5) | (1 << 0);
while((SysTick->SR & (1 << 0)) != (1 << 0)); while((SysTick->SR & (1 << 0)) != (1 << 0));
SysTick->CTLR &= ~(1 << 0); SysTick->CTLR &= ~(1 << 0);
*/ */
} }
/********************************************************************* /*********************************************************************
* @fn USART_Printf_Init * @fn USART_Printf_Init
* *
* @brief Initializes the USARTx peripheral. * @brief Initializes the USARTx peripheral.
* *
* @param baudrate - USART communication baud rate. * @param baudrate - USART communication baud rate.
* *
* @return None * @return None
*/ */
void USART_Printf_Init(uint32_t baudrate) void USART_Printf_Init(uint32_t baudrate)
{ {
GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitTypeDef GPIO_InitStructure;
USART_InitTypeDef USART_InitStructure; USART_InitTypeDef USART_InitStructure;
#if(DEBUG == DEBUG_UART1) #if(DEBUG == DEBUG_UART1)
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOB, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_Init(GPIOB, &GPIO_InitStructure);
#elif(DEBUG == DEBUG_UART2) #elif(DEBUG == DEBUG_UART2)
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_Init(GPIOA, &GPIO_InitStructure);
#elif(DEBUG == DEBUG_UART3) #elif(DEBUG == DEBUG_UART3)
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_Init(GPIOB, &GPIO_InitStructure);
#endif #endif
USART_InitStructure.USART_BaudRate = baudrate; USART_InitStructure.USART_BaudRate = baudrate;
USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1; USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No; USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Tx; USART_InitStructure.USART_Mode = USART_Mode_Tx;
#if(DEBUG == DEBUG_UART1) #if(DEBUG == DEBUG_UART1)
USART_Init(USART1, &USART_InitStructure); USART_Init(USART1, &USART_InitStructure);
USART_Cmd(USART1, ENABLE); USART_Cmd(USART1, ENABLE);
#elif(DEBUG == DEBUG_UART2) #elif(DEBUG == DEBUG_UART2)
USART_Init(USART2, &USART_InitStructure); USART_Init(USART2, &USART_InitStructure);
USART_Cmd(USART2, ENABLE); USART_Cmd(USART2, ENABLE);
#elif(DEBUG == DEBUG_UART3) #elif(DEBUG == DEBUG_UART3)
USART_Init(USART3, &USART_InitStructure); USART_Init(USART3, &USART_InitStructure);
USART_Cmd(USART3, ENABLE); USART_Cmd(USART3, ENABLE);
#endif #endif
} }
/********************************************************************* /*********************************************************************
* @fn SDI_Printf_Enable * @fn SDI_Printf_Enable
* *
* @brief Initializes the SDI printf Function. * @brief Initializes the SDI printf Function.
* *
* @param None * @param None
* *
* @return None * @return None
*/ */
void SDI_Printf_Enable(void) void SDI_Printf_Enable(void)
{ {
*(DEBUG_DATA0_ADDRESS) = 0; *(DEBUG_DATA0_ADDRESS) = 0;
Delay_Init(); Delay_Init();
Delay_Ms(1); Delay_Ms(1);
} }
/********************************************************************* /*********************************************************************
* @fn _write * @fn _write
* *
* @brief Support Printf Function * @brief Support Printf Function
* *
* @param *buf - UART send Data. * @param *buf - UART send Data.
* size - Data length * size - Data length
* *
* @return size - Data length * @return size - Data length
*/ */
__attribute__((used)) __attribute__((used))
int _write(int fd, char *buf, int size) int _write(int fd, char *buf, int size)
{ {
int i = 0; int i = 0;
#if (SDI_PRINT == SDI_PR_OPEN) #if (SDI_PRINT == SDI_PR_OPEN)
int writeSize = size; int writeSize = size;
do do
{ {
/** /**
* data0 data1 共8个字节 * data0 data1 共8个字节
* data0最低位的字节存放长度，最大为 7 * data0最低位的字节存放长度，最大为 7
* *
*/ */
while( (*(DEBUG_DATA0_ADDRESS) != 0u)) while( (*(DEBUG_DATA0_ADDRESS) != 0u))
{ {
} }
if(writeSize>7) if(writeSize>7)
{ {
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
i += 7; i += 7;
writeSize -= 7; writeSize -= 7;
} }
else else
{ {
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
writeSize = 0; writeSize = 0;
} }
} while (writeSize); } while (writeSize);
#else #else
for(i = 0; i < size; i++){ for(i = 0; i < size; i++){
#if(DEBUG == DEBUG_UART1) #if(DEBUG == DEBUG_UART1)
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
USART_SendData(USART1, *buf++); USART_SendData(USART1, *buf++);
#elif(DEBUG == DEBUG_UART2) #elif(DEBUG == DEBUG_UART2)
while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
USART_SendData(USART2, *buf++); USART_SendData(USART2, *buf++);
#elif(DEBUG == DEBUG_UART3) #elif(DEBUG == DEBUG_UART3)
while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
USART_SendData(USART3, *buf++); USART_SendData(USART3, *buf++);
#endif #endif
} }
#endif #endif
return size; return size;
} }
/********************************************************************* /*********************************************************************
* @fn _sbrk * @fn _sbrk
* *
* @brief Change the spatial position of data segment. * @brief Change the spatial position of data segment.
* *
* @return size - Data length * @return size - Data length
*/ */
__attribute__((used)) __attribute__((used))
void *_sbrk(ptrdiff_t incr) void *_sbrk(ptrdiff_t incr)
{ {
extern char _end[]; extern char _end[];
extern char _heap_end[]; extern char _heap_end[];
static char *curbrk = _end; static char *curbrk = _end;
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
return NULL - 1; return NULL - 1;
curbrk += incr; curbrk += incr;
return curbrk - incr; return curbrk - incr;
} }

120
Debug/debug.h
View file

@ -1,60 +1,60 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : debug.h * File Name : debug.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for UART * Description : This file contains all the functions prototypes for UART
* Printf , Delay functions. * Printf , Delay functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __DEBUG_H #ifndef __DEBUG_H
#define __DEBUG_H #define __DEBUG_H
#include "stdio.h" #include "stdio.h"
#include "ch32x035.h" #include "ch32x035.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* UART Printf Definition */ /* UART Printf Definition */
#define DEBUG_UART1 1 #define DEBUG_UART1 1
#define DEBUG_UART2 2 #define DEBUG_UART2 2
#define DEBUG_UART3 3 #define DEBUG_UART3 3
/* DEBUG UATR Definition */ /* DEBUG UATR Definition */
#ifndef DEBUG #ifndef DEBUG
#define DEBUG DEBUG_UART1 #define DEBUG DEBUG_UART1
#endif #endif
/* SDI Printf Definition */ /* SDI Printf Definition */
#define SDI_PR_CLOSE 0 #define SDI_PR_CLOSE 0
#define SDI_PR_OPEN 1 #define SDI_PR_OPEN 1
#ifndef SDI_PRINT #ifndef SDI_PRINT
#define SDI_PRINT SDI_PR_CLOSE #define SDI_PRINT SDI_PR_CLOSE
#endif #endif
void Delay_Init(void); void Delay_Init(void);
uint64_t SysTick_Read(void); uint64_t SysTick_Read(void);
uint64_t SysTick_Us(void); uint64_t SysTick_Us(void);
uint64_t SysTick_Ms(void); uint64_t SysTick_Ms(void);
void Delay_Us(uint32_t n); void Delay_Us(uint32_t n);
void Delay_Ms(uint32_t n); void Delay_Ms(uint32_t n);
void USART_Printf_Init(uint32_t baudrate); void USART_Printf_Init(uint32_t baudrate);
void SDI_Printf_Enable(void); void SDI_Printf_Enable(void);
#if(DEBUG) #if(DEBUG)
#define PRINT(format, ...) printf(format, ##__VA_ARGS__) #define PRINT(format, ...) printf(format, ##__VA_ARGS__)
#else #else
#define PRINT(X...) #define PRINT(X...)
#endif #endif
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

532
Peripheral/inc/PIOC_SFR.h
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@ -1,266 +1,266 @@
/* Define for PIOC */ /* Define for PIOC */
/* Website: http://wch.cn */ /* Website: http://wch.cn */
/* Email: tech@wch.cn */ /* Email: tech@wch.cn */
/* Author: W.ch 2022.08 */ /* Author: W.ch 2022.08 */
/* V1.0 SpecialFunctionRegister */ /* V1.0 SpecialFunctionRegister */
// __PIOC_SFR_H__ // __PIOC_SFR_H__
#ifndef __PIOC_SFR_H__ #ifndef __PIOC_SFR_H__
#define __PIOC_SFR_H__ #define __PIOC_SFR_H__
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
// Register Bit Attribute / Bit Access Type // Register Bit Attribute / Bit Access Type
// RO: Read Only (internal change) // RO: Read Only (internal change)
// RW: Read / Write // RW: Read / Write
// Attribute: master/PIOC // Attribute: master/PIOC
/* Register name rule: /* Register name rule:
R32_* for 32 bits register (UINT32,ULONG) R32_* for 32 bits register (UINT32,ULONG)
R16_* for 16 bits register (UINT16,USHORT) R16_* for 16 bits register (UINT16,USHORT)
R8_* for 8 bits register (UINT8,UCHAR) R8_* for 8 bits register (UINT8,UCHAR)
RB_* for bit or bit mask of 8 bit register */ RB_* for bit or bit mask of 8 bit register */
/* ********************************************************************************************************************* */ /* ********************************************************************************************************************* */
#define PIOC_SRAM_BASE (SRAM_BASE+0x4000) // PIOC code RAM base address #define PIOC_SRAM_BASE (SRAM_BASE+0x4000) // PIOC code RAM base address
#define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address #define PIOC_SFR_BASE PIOC_BASE // PIOC SFR base address
#define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR #define R32_PIOC_SFR (*((volatile unsigned long *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC SFR
#define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address #define R8_INDIR_ADDR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x04))) // RO/RW, PIOC indirect address
#define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count #define R8_TMR0_COUNT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x05))) // RO/RW, PIOC timer count
#define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit #define R8_TMR0_CTRL (*((volatile unsigned char *)(PIOC_SFR_BASE+0x06))) // RO/RW, PIOC timer control and GP bit
#define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag #define RB_EN_LEVEL1 0x80 // RO/RW, enable IO1 level change to wakeup & action interrupt flag
#define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag #define RB_EN_LEVEL0 0x40 // RO/RW, enable IO0 level change to wakeup & action interrupt flag
#define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset #define RB_GP_BIT_Y 0x20 // RO/RW, general-purpose bit 1, reset by power on, no effect if system reset or RB_MST_RESET reset
#define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset #define RB_GP_BIT_X 0x10 // RO/RW, general-purpose bit 0, reset by power on, no effect if system reset or RB_MST_RESET reset
#define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM #define RB_TMR0_MODE 0x08 // RO/RW, timer mode: 0-timer, 1-PWM
#define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2 #define RB_TMR0_FREQ2 0x04 // RO/RW, timer clock frequency selection 2
#define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1 #define RB_TMR0_FREQ1 0x02 // RO/RW, timer clock frequency selection 1
#define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0 #define RB_TMR0_FREQ0 0x01 // RO/RW, timer clock frequency selection 0
#define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value #define R8_TMR0_INIT (*((volatile unsigned char *)(PIOC_SFR_BASE+0x07))) // RO/RW, PIOC timer initial value
#define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config #define R32_PORT_CFG (*((volatile unsigned long *)(PIOC_SFR_BASE+0x08))) // RO/RW, port status and config
#define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle #define R8_BIT_CYCLE (*((volatile unsigned char *)(PIOC_SFR_BASE+0x08))) // RO/RW, encode bit cycle
#define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output #define RB_BIT_TX_O0 0x80 // RO/RW, bit data for IO0 port encode output
#define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1 #define RB_BIT_CYCLE 0x7F // RO/RW, IO0 port bit data cycle -1
#define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2 #define R8_INDIR_ADDR2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x09))) // RO/RW, PIOC indirect address 2
#define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode #define R8_PORT_DIR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0A))) // RO/RW, IO port direction and mode
//#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3 //#define RB_PORT_MOD3 0x80 // RO/RW, IO port mode 3
//#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2 //#define RB_PORT_MOD2 0x40 // RO/RW, IO port mode 2
//#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1 //#define RB_PORT_MOD1 0x20 // RO/RW, IO port mode 1
//#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0 //#define RB_PORT_MOD0 0x10 // RO/RW, IO port mode 0
//#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable //#define RB_PORT_PU1 0x08 // RO/RW, IO1 port pullup enable
//#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable //#define RB_PORT_PU0 0x04 // RO/RW, IO0 port pullup enable
#define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction #define RB_PORT_DIR1 0x02 // RO/RW, IO1 port direction
#define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction #define RB_PORT_DIR0 0x01 // RO/RW, IO0 port direction
#define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output #define R8_PORT_IO (*((volatile unsigned char *)(PIOC_SFR_BASE+0x0B))) // RO/RW, IO port input and output
#define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input #define RB_PORT_IN_XOR 0x80 // RO/RO, IO0 XOR IO1 port input
#define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received #define RB_BIT_RX_I0 0x40 // RO/RO, decoced bit data for IO0 port received
#define RB_PORT_IN1 0x20 // RO/RO, IO1 port input #define RB_PORT_IN1 0x20 // RO/RO, IO1 port input
#define RB_PORT_IN0 0x10 // RO/RO, IO0 port input #define RB_PORT_IN0 0x10 // RO/RO, IO0 port input
#define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input #define RB_PORT_XOR1 0x08 // RO/RO, IO1 port output XOR input
#define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input #define RB_PORT_XOR0 0x04 // RO/RO, IO0 port output XOR input
#define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output #define RB_PORT_OUT1 0x02 // RO/RW, IO1 port output
#define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output #define RB_PORT_OUT0 0x01 // RO/RW, IO0 port output
#define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control #define R32_DATA_CTRL (*((volatile unsigned long *)(PIOC_SFR_BASE+0x1C))) // RW/RW, data control
#define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config #define R8_SYS_CFG (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1C))) // RW/RW, port config
#define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect) #define RB_INT_REQ 0x80 // RO/RW, PIOC interrupt request action, set 1/0 by PIOC, clear 0 by master write R8_CTRL_RD (no effect)
#define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD #define RB_DATA_SW_MR 0x40 // RO/RO, R8_CTRL_RD wait for read status, set 1 by PIOC write R8_CTRL_RD, clear 0 by master read R8_CTRL_RD
#define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR #define RB_DATA_MW_SR 0x20 // RO/RO, R8_CTRL_WR wait for read status, set 1 by master write R8_CTRL_WR, clear 0 by PIOC read R8_CTRL_WR
#define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0 #define RB_MST_CFG_B4 0x10 // RW/RO, config inform bit, default 0
#define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0 #define RB_MST_IO_EN1 0x08 // RW/RO, IO1 switch enable, default 0
#define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0 #define RB_MST_IO_EN0 0x04 // RW/RO, IO0 switch enable, default 0
#define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0 #define RB_MST_RESET 0x02 // RW/RO, force PIOC reset, high action, default 0
#define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0 #define RB_MST_CLK_GATE 0x01 // RW/RO, PIOC global clock enable, high action, default 0
#define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only #define R8_CTRL_RD (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1D))) // RO/RW, data for master read only and PIOC write only
#define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only #define R8_CTRL_WR (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1E))) // RW/RO, data for master write only and PIOC read only
#define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange #define R8_DATA_EXCH (*((volatile unsigned char *)(PIOC_SFR_BASE+0x1F))) // RW/RW, data exchange
#define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3 #define R32_DATA_REG0_3 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0~3
#define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0 #define R8_DATA_REG0 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x20))) // RW/RW, data buffer 0
#define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1 #define R8_DATA_REG1 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x21))) // RW/RW, data buffer 1
#define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2 #define R8_DATA_REG2 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x22))) // RW/RW, data buffer 2
#define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3 #define R8_DATA_REG3 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x23))) // RW/RW, data buffer 3
#define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7 #define R32_DATA_REG4_7 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4~7
#define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4 #define R8_DATA_REG4 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x24))) // RW/RW, data buffer 4
#define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5 #define R8_DATA_REG5 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x25))) // RW/RW, data buffer 5
#define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6 #define R8_DATA_REG6 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x26))) // RW/RW, data buffer 6
#define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7 #define R8_DATA_REG7 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x27))) // RW/RW, data buffer 7
#define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11 #define R32_DATA_REG8_11 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8~11
#define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8 #define R8_DATA_REG8 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x28))) // RW/RW, data buffer 8
#define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9 #define R8_DATA_REG9 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x29))) // RW/RW, data buffer 9
#define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10 #define R8_DATA_REG10 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2A))) // RW/RW, data buffer 10
#define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11 #define R8_DATA_REG11 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2B))) // RW/RW, data buffer 11
#define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15 #define R32_DATA_REG12_15 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12~15
#define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12 #define R8_DATA_REG12 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2C))) // RW/RW, data buffer 12
#define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13 #define R8_DATA_REG13 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2D))) // RW/RW, data buffer 13
#define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14 #define R8_DATA_REG14 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2E))) // RW/RW, data buffer 14
#define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15 #define R8_DATA_REG15 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x2F))) // RW/RW, data buffer 15
#define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19 #define R32_DATA_REG16_19 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16~19
#define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16 #define R8_DATA_REG16 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x30))) // RW/RW, data buffer 16
#define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17 #define R8_DATA_REG17 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x31))) // RW/RW, data buffer 17
#define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18 #define R8_DATA_REG18 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x32))) // RW/RW, data buffer 18
#define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19 #define R8_DATA_REG19 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x33))) // RW/RW, data buffer 19
#define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23 #define R32_DATA_REG20_23 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20~23
#define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20 #define R8_DATA_REG20 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x34))) // RW/RW, data buffer 20
#define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21 #define R8_DATA_REG21 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x35))) // RW/RW, data buffer 21
#define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22 #define R8_DATA_REG22 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x36))) // RW/RW, data buffer 22
#define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23 #define R8_DATA_REG23 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x37))) // RW/RW, data buffer 23
#define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27 #define R32_DATA_REG24_27 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24~27
#define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24 #define R8_DATA_REG24 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x38))) // RW/RW, data buffer 24
#define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25 #define R8_DATA_REG25 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x39))) // RW/RW, data buffer 25
#define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26 #define R8_DATA_REG26 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3A))) // RW/RW, data buffer 26
#define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27 #define R8_DATA_REG27 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3B))) // RW/RW, data buffer 27
#define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31 #define R32_DATA_REG28_31 (*((volatile unsigned long *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28~31
#define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28 #define R8_DATA_REG28 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3C))) // RW/RW, data buffer 28
#define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29 #define R8_DATA_REG29 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3D))) // RW/RW, data buffer 29
#define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30 #define R8_DATA_REG30 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3E))) // RW/RW, data buffer 30
#define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31 #define R8_DATA_REG31 (*((volatile unsigned char *)(PIOC_SFR_BASE+0x3F))) // RW/RW, data buffer 31
/* ******************************************************************************************************* */ /* ******************************************************************************************************* */
/* PIOC Registers */ /* PIOC Registers */
typedef struct typedef struct
{ {
uint32_t RESERVED00; uint32_t RESERVED00;
union { union {
__IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR __IO uint32_t D32_PIOC_SFR ; // RO/RW, PIOC SFR
struct { struct {
__IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address __IO uint8_t D8_INDIR_ADDR; // RO/RW, PIOC indirect address
__IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count __IO uint8_t D8_TMR0_COUNT; // RO/RW, PIOC timer count
__IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit __IO uint8_t D8_TMR0_CTRL; // RO/RW, PIOC timer control and GP bit
__IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value __IO uint8_t D8_TMR0_INIT; // RO/RW, PIOC timer initial value
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config __IO uint32_t D32_PORT_CFG ; // RO/RW, port status and config
struct { struct {
__IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle __IO uint8_t D8_BIT_CYCLE; // RO/RW, encode bit cycle
__IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2 __IO uint8_t D8_INDIR_ADDR2; // RO/RW, PIOC indirect address 2
__IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode __IO uint8_t D8_PORT_DIR; // RO/RW, IO port direction and mode
__IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output __IO uint8_t D8_PORT_IO; // RO/RW, IO port input and output
} ; } ;
} ; } ;
uint32_t RESERVED0C; uint32_t RESERVED0C;
uint32_t RESERVED10; uint32_t RESERVED10;
uint32_t RESERVED14; uint32_t RESERVED14;
uint32_t RESERVED18; uint32_t RESERVED18;
union { union {
__IO uint32_t D32_DATA_CTRL ; // RW/RW, data control __IO uint32_t D32_DATA_CTRL ; // RW/RW, data control
struct { struct {
__IO uint8_t D8_SYS_CFG; // RW/RW, port config __IO uint8_t D8_SYS_CFG; // RW/RW, port config
__IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only __IO uint8_t D8_CTRL_RD; // RO/RW, data for master read only and PIOC write only
__IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only __IO uint8_t D8_CTRL_WR; // RW/RO, data for master write only and PIOC read only
__IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange __IO uint8_t D8_DATA_EXCH; // RW/RW, data exchange
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3 __IO uint32_t D32_DATA_REG0_3 ; // RW/RW, data buffer 0~3
struct { struct {
__IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0 __IO uint8_t D8_DATA_REG0; // RW/RW, data buffer 0
__IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1 __IO uint8_t D8_DATA_REG1; // RW/RW, data buffer 1
__IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2 __IO uint8_t D8_DATA_REG2; // RW/RW, data buffer 2
__IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3 __IO uint8_t D8_DATA_REG3; // RW/RW, data buffer 3
} ; } ;
__IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1 __IO uint16_t D16_DATA_REG0_1 ; // RW/RW, data buffer 0~1
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7 __IO uint32_t D32_DATA_REG4_7 ; // RW/RW, data buffer 4~7
struct { struct {
__IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4 __IO uint8_t D8_DATA_REG4; // RW/RW, data buffer 4
__IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5 __IO uint8_t D8_DATA_REG5; // RW/RW, data buffer 5
__IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6 __IO uint8_t D8_DATA_REG6; // RW/RW, data buffer 6
__IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7 __IO uint8_t D8_DATA_REG7; // RW/RW, data buffer 7
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11 __IO uint32_t D32_DATA_REG8_11 ; // RW/RW, data buffer 8~11
struct { struct {
__IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8 __IO uint8_t D8_DATA_REG8; // RW/RW, data buffer 8
__IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9 __IO uint8_t D8_DATA_REG9; // RW/RW, data buffer 9
__IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10 __IO uint8_t D8_DATA_REG10; // RW/RW, data buffer 10
__IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11 __IO uint8_t D8_DATA_REG11; // RW/RW, data buffer 11
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15 __IO uint32_t D32_DATA_REG12_15 ; // RW/RW, data buffer 12~15
struct { struct {
__IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12 __IO uint8_t D8_DATA_REG12; // RW/RW, data buffer 12
__IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13 __IO uint8_t D8_DATA_REG13; // RW/RW, data buffer 13
__IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14 __IO uint8_t D8_DATA_REG14; // RW/RW, data buffer 14
__IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15 __IO uint8_t D8_DATA_REG15; // RW/RW, data buffer 15
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19 __IO uint32_t D32_DATA_REG16_19 ; // RW/RW, data buffer 16~19
struct { struct {
__IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16 __IO uint8_t D8_DATA_REG16; // RW/RW, data buffer 16
__IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17 __IO uint8_t D8_DATA_REG17; // RW/RW, data buffer 17
__IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18 __IO uint8_t D8_DATA_REG18; // RW/RW, data buffer 18
__IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19 __IO uint8_t D8_DATA_REG19; // RW/RW, data buffer 19
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23 __IO uint32_t D32_DATA_REG20_23 ; // RW/RW, data buffer 20~23
struct { struct {
__IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20 __IO uint8_t D8_DATA_REG20; // RW/RW, data buffer 20
__IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21 __IO uint8_t D8_DATA_REG21; // RW/RW, data buffer 21
__IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22 __IO uint8_t D8_DATA_REG22; // RW/RW, data buffer 22
__IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23 __IO uint8_t D8_DATA_REG23; // RW/RW, data buffer 23
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27 __IO uint32_t D32_DATA_REG24_27 ; // RW/RW, data buffer 24~27
struct { struct {
__IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24 __IO uint8_t D8_DATA_REG24; // RW/RW, data buffer 24
__IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25 __IO uint8_t D8_DATA_REG25; // RW/RW, data buffer 25
__IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26 __IO uint8_t D8_DATA_REG26; // RW/RW, data buffer 26
__IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27 __IO uint8_t D8_DATA_REG27; // RW/RW, data buffer 27
} ; } ;
} ; } ;
union { union {
__IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31 __IO uint32_t D32_DATA_REG28_31 ; // RW/RW, data buffer 28~31
struct { struct {
__IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28 __IO uint8_t D8_DATA_REG28; // RW/RW, data buffer 28
__IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29 __IO uint8_t D8_DATA_REG29; // RW/RW, data buffer 29
__IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30 __IO uint8_t D8_DATA_REG30; // RW/RW, data buffer 30
__IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31 __IO uint8_t D8_DATA_REG31; // RW/RW, data buffer 31
} ; } ;
} ; } ;
} PIOC_TypeDef; } PIOC_TypeDef;
#define PIOC ((PIOC_TypeDef *)PIOC_BASE) #define PIOC ((PIOC_TypeDef *)PIOC_BASE)
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif // __PIOC_SFR_H__ #endif // __PIOC_SFR_H__

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Peripheral/inc/ch32x035.h
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Peripheral/inc/ch32x035_adc.h
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/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_adc.h * File Name : ch32x035_adc.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* ADC firmware library. * ADC firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_ADC_H #ifndef __CH32X035_ADC_H
#define __CH32X035_ADC_H #define __CH32X035_ADC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* ADC Init structure definition */ /* ADC Init structure definition */
typedef struct typedef struct
{ {
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
dual mode. dual mode.
This parameter can be a value of @ref ADC_mode */ This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode. Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */ This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
Continuous or Single mode. Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */ This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align, Note:ADC_DataAlign_Left only applies to regular channels */ This parameter can be a value of @ref ADC_data_align, Note:ADC_DataAlign_Left only applies to regular channels */
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group. using the sequencer for regular channel group.
This parameter must range from 1 to 16. */ This parameter must range from 1 to 16. */
uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
This parameter can be a value of @ref ADC_OutputBuffer */ This parameter can be a value of @ref ADC_OutputBuffer */
uint32_t ADC_Pga; /* Specifies the PGA gain multiple. uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
This parameter can be a value of @ref ADC_Pga */ This parameter can be a value of @ref ADC_Pga */
} ADC_InitTypeDef; } ADC_InitTypeDef;
/* ADC_mode */ /* ADC_mode */
#define ADC_Mode_Independent ((uint32_t)0x00000000) #define ADC_Mode_Independent ((uint32_t)0x00000000)
/* ADC_external_trigger_sources_for_regular_channels_conversion */ /* ADC_external_trigger_sources_for_regular_channels_conversion */
#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000) #define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000) #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000) #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000) #define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000) #define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x000A0000) #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000) #define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
/* ADC_data_align */ /* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000) #define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800) #define ADC_DataAlign_Left ((uint32_t)0x00000800)
/* ADC_channels */ /* ADC_channels */
#define ADC_Channel_0 ((uint8_t)0x00) #define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01) #define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02) #define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03) #define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04) #define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05) #define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06) #define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07) #define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08) #define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09) #define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A) #define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B) #define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C) #define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D) #define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E) #define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F) #define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_15) #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_15)
/* ADC_sampling_time */ /* ADC_sampling_time */
#define ADC_SampleTime_4Cycles ((uint8_t)0x00) #define ADC_SampleTime_4Cycles ((uint8_t)0x00)
#define ADC_SampleTime_5Cycles ((uint8_t)0x01) #define ADC_SampleTime_5Cycles ((uint8_t)0x01)
#define ADC_SampleTime_6Cycles ((uint8_t)0x02) #define ADC_SampleTime_6Cycles ((uint8_t)0x02)
#define ADC_SampleTime_7Cycles ((uint8_t)0x03) #define ADC_SampleTime_7Cycles ((uint8_t)0x03)
#define ADC_SampleTime_8Cycles ((uint8_t)0x04) #define ADC_SampleTime_8Cycles ((uint8_t)0x04)
#define ADC_SampleTime_9Cycles ((uint8_t)0x05) #define ADC_SampleTime_9Cycles ((uint8_t)0x05)
#define ADC_SampleTime_10Cycles ((uint8_t)0x06) #define ADC_SampleTime_10Cycles ((uint8_t)0x06)
#define ADC_SampleTime_11Cycles ((uint8_t)0x07) #define ADC_SampleTime_11Cycles ((uint8_t)0x07)
/* ADC_external_trigger_sources_for_injected_channels_conversion */ /* ADC_external_trigger_sources_for_injected_channels_conversion */
#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000) #define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000) #define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000) #define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00004000) #define ADC_ExternalTrigInjecConv_T2_CC2 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000) #define ADC_ExternalTrigInjecConv_T3_CC2 ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000) #define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
/* ADC_injected_channel_selection */ /* ADC_injected_channel_selection */
#define ADC_InjectedChannel_1 ((uint8_t)0x14) #define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18) #define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C) #define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20) #define ADC_InjectedChannel_4 ((uint8_t)0x20)
/* ADC_analog_watchdog_selection */ /* ADC_analog_watchdog_selection */
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
/* ADC_interrupts_definition */ /* ADC_interrupts_definition */
#define ADC_IT_EOC ((uint16_t)0x0220) #define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140) #define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480) #define ADC_IT_JEOC ((uint16_t)0x0480)
/* ADC_flags_definition */ /* ADC_flags_definition */
#define ADC_FLAG_AWD ((uint8_t)0x01) #define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02) #define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04) #define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08) #define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10) #define ADC_FLAG_STRT ((uint8_t)0x10)
/* ADC_analog_watchdog_reset_enable_selection */ /* ADC_analog_watchdog_reset_enable_selection */
#define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00001000) #define ADC_AnalogWatchdog_0_RST_EN ((uint32_t)0x00001000)
#define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00002000) #define ADC_AnalogWatchdog_1_RST_EN ((uint32_t)0x00002000)
#define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00004000) #define ADC_AnalogWatchdog_2_RST_EN ((uint32_t)0x00004000)
#define ADC_AnalogWatchdog_3_RST_EN ((uint32_t)0x00008000) #define ADC_AnalogWatchdog_3_RST_EN ((uint32_t)0x00008000)
/* ADC_analog_watchdog_reset_flags_definition */ /* ADC_analog_watchdog_reset_flags_definition */
#define ADC_AnalogWatchdogResetFLAG_0 ((uint32_t)0x00010000) #define ADC_AnalogWatchdogResetFLAG_0 ((uint32_t)0x00010000)
#define ADC_AnalogWatchdogResetFLAG_1 ((uint32_t)0x00020000) #define ADC_AnalogWatchdogResetFLAG_1 ((uint32_t)0x00020000)
#define ADC_AnalogWatchdogResetFLAG_2 ((uint32_t)0x00040000) #define ADC_AnalogWatchdogResetFLAG_2 ((uint32_t)0x00040000)
#define ADC_AnalogWatchdogResetFLAG_3 ((uint32_t)0x00080000) #define ADC_AnalogWatchdogResetFLAG_3 ((uint32_t)0x00080000)
/* ADC_clock */ /* ADC_clock */
#define ADC_CLK_Div4 ((uint32_t)0x00000013) #define ADC_CLK_Div4 ((uint32_t)0x00000013)
#define ADC_CLK_Div5 ((uint32_t)0x00000014) #define ADC_CLK_Div5 ((uint32_t)0x00000014)
#define ADC_CLK_Div6 ((uint32_t)0x00000025) #define ADC_CLK_Div6 ((uint32_t)0x00000025)
#define ADC_CLK_Div7 ((uint32_t)0x00000026) #define ADC_CLK_Div7 ((uint32_t)0x00000026)
#define ADC_CLK_Div8 ((uint32_t)0x00000037) #define ADC_CLK_Div8 ((uint32_t)0x00000037)
#define ADC_CLK_Div9 ((uint32_t)0x00000038) #define ADC_CLK_Div9 ((uint32_t)0x00000038)
#define ADC_CLK_Div10 ((uint32_t)0x00000049) #define ADC_CLK_Div10 ((uint32_t)0x00000049)
#define ADC_CLK_Div11 ((uint32_t)0x0000004A) #define ADC_CLK_Div11 ((uint32_t)0x0000004A)
#define ADC_CLK_Div12 ((uint32_t)0x0000005B) #define ADC_CLK_Div12 ((uint32_t)0x0000005B)
#define ADC_CLK_Div13 ((uint32_t)0x0000005C) #define ADC_CLK_Div13 ((uint32_t)0x0000005C)
#define ADC_CLK_Div14 ((uint32_t)0x0000006D) #define ADC_CLK_Div14 ((uint32_t)0x0000006D)
#define ADC_CLK_Div15 ((uint32_t)0x0000006E) #define ADC_CLK_Div15 ((uint32_t)0x0000006E)
#define ADC_CLK_Div16 ((uint32_t)0x0000007F) #define ADC_CLK_Div16 ((uint32_t)0x0000007F)
void ADC_DeInit(ADC_TypeDef *ADCx); void ADC_DeInit(ADC_TypeDef *ADCx);
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
uint32_t ADC_GetDualModeConversionValue(void); uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); void ADC_AnalogWatchdog1ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); void ADC_AnalogWatchdog2ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); void ADC_AnalogWatchdog3ThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState); void ADC_AnalogWatchdogResetCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog_x, FunctionalState NewState);
void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState); void ADC_AnalogWatchdogScanCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x); void ADC_CLKConfig(ADC_TypeDef *ADCx, uint32_t ADC_CLK_Div_x);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

96
Peripheral/inc/ch32x035_awu.h
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@ -1,48 +1,48 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_awu.h * File Name : ch32x035_awu.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* AWU firmware library. * AWU firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_AWU_H #ifndef __CH32X035_AWU_H
#define __CH32X035_AWU_H #define __CH32X035_AWU_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* PWR_AWU_Prescaler */ /* PWR_AWU_Prescaler */
#define AWU_Prescaler_1 ((uint32_t)0x00000000) #define AWU_Prescaler_1 ((uint32_t)0x00000000)
#define AWU_Prescaler_2 ((uint32_t)0x00000002) #define AWU_Prescaler_2 ((uint32_t)0x00000002)
#define AWU_Prescaler_4 ((uint32_t)0x00000003) #define AWU_Prescaler_4 ((uint32_t)0x00000003)
#define AWU_Prescaler_8 ((uint32_t)0x00000004) #define AWU_Prescaler_8 ((uint32_t)0x00000004)
#define AWU_Prescaler_16 ((uint32_t)0x00000005) #define AWU_Prescaler_16 ((uint32_t)0x00000005)
#define AWU_Prescaler_32 ((uint32_t)0x00000006) #define AWU_Prescaler_32 ((uint32_t)0x00000006)
#define AWU_Prescaler_64 ((uint32_t)0x00000007) #define AWU_Prescaler_64 ((uint32_t)0x00000007)
#define AWU_Prescaler_128 ((uint32_t)0x00000008) #define AWU_Prescaler_128 ((uint32_t)0x00000008)
#define AWU_Prescaler_256 ((uint32_t)0x00000009) #define AWU_Prescaler_256 ((uint32_t)0x00000009)
#define AWU_Prescaler_512 ((uint32_t)0x0000000A) #define AWU_Prescaler_512 ((uint32_t)0x0000000A)
#define AWU_Prescaler_1024 ((uint32_t)0x0000000B) #define AWU_Prescaler_1024 ((uint32_t)0x0000000B)
#define AWU_Prescaler_2048 ((uint32_t)0x0000000C) #define AWU_Prescaler_2048 ((uint32_t)0x0000000C)
#define AWU_Prescaler_4096 ((uint32_t)0x0000000D) #define AWU_Prescaler_4096 ((uint32_t)0x0000000D)
#define AWU_Prescaler_10240 ((uint32_t)0x0000000E) #define AWU_Prescaler_10240 ((uint32_t)0x0000000E)
#define AWU_Prescaler_61440 ((uint32_t)0x0000000F) #define AWU_Prescaler_61440 ((uint32_t)0x0000000F)
void AutoWakeUpCmd(FunctionalState NewState); void AutoWakeUpCmd(FunctionalState NewState);
void AWU_SetPrescaler(uint32_t AWU_Prescaler); void AWU_SetPrescaler(uint32_t AWU_Prescaler);
void AWU_SetWindowValue(uint8_t WindowValue); void AWU_SetWindowValue(uint8_t WindowValue);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

82
Peripheral/inc/ch32x035_dbgmcu.h
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@ -1,41 +1,41 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_dbgmcu.h * File Name : ch32x035_dbgmcu.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* DBGMCU firmware library. * DBGMCU firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_DBGMCU_H #ifndef __CH32X035_DBGMCU_H
#define __CH32X035_DBGMCU_H #define __CH32X035_DBGMCU_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
#define DBGMCU_SLEEP ((uint32_t)0x00000001) #define DBGMCU_SLEEP ((uint32_t)0x00000001)
#define DBGMCU_STOP ((uint32_t)0x00000002) #define DBGMCU_STOP ((uint32_t)0x00000002)
#define DBGMCU_STANDBY ((uint32_t)0x00000004) #define DBGMCU_STANDBY ((uint32_t)0x00000004)
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) #define DBGMCU_TIM1_STOP ((uint32_t)0x00001000)
#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) #define DBGMCU_TIM2_STOP ((uint32_t)0x00002000)
#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) #define DBGMCU_TIM3_STOP ((uint32_t)0x00004000)
uint32_t DBGMCU_GetREVID(void); uint32_t DBGMCU_GetREVID(void);
uint32_t DBGMCU_GetDEVID(void); uint32_t DBGMCU_GetDEVID(void);
uint32_t __get_DEBUG_CR(void); uint32_t __get_DEBUG_CR(void);
void __set_DEBUG_CR(uint32_t value); void __set_DEBUG_CR(uint32_t value);
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
uint32_t DBGMCU_GetCHIPID( void ); uint32_t DBGMCU_GetCHIPID( void );
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

368
Peripheral/inc/ch32x035_dma.h
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@ -1,184 +1,184 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_dma.h * File Name : ch32x035_dma.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* DMA firmware library. * DMA firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_DMA_H #ifndef __CH32X035_DMA_H
#define __CH32X035_DMA_H #define __CH32X035_DMA_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* DMA Init structure definition */ /* DMA Init structure definition */
typedef struct typedef struct
{ {
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */ This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */ or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */ This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */ This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */ This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode. This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory @note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */ data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */ This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */ This parameter can be a value of @ref DMA_memory_to_memory */
} DMA_InitTypeDef; } DMA_InitTypeDef;
/* DMA_data_transfer_direction */ /* DMA_data_transfer_direction */
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) #define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
/* DMA_peripheral_incremented_mode */ /* DMA_peripheral_incremented_mode */
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) #define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
/* DMA_memory_incremented_mode */ /* DMA_memory_incremented_mode */
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) #define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
/* DMA_peripheral_data_size */ /* DMA_peripheral_data_size */
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) #define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) #define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
/* DMA_memory_data_size */ /* DMA_memory_data_size */
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) #define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) #define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
/* DMA_circular_normal_mode */ /* DMA_circular_normal_mode */
#define DMA_Mode_Circular ((uint32_t)0x00000020) #define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000) #define DMA_Mode_Normal ((uint32_t)0x00000000)
/* DMA_priority_level */ /* DMA_priority_level */
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) #define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000) #define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000) #define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000) #define DMA_Priority_Low ((uint32_t)0x00000000)
/* DMA_memory_to_memory */ /* DMA_memory_to_memory */
#define DMA_M2M_Enable ((uint32_t)0x00004000) #define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000) #define DMA_M2M_Disable ((uint32_t)0x00000000)
/* DMA_interrupts_definition */ /* DMA_interrupts_definition */
#define DMA_IT_TC ((uint32_t)0x00000002) #define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004) #define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008) #define DMA_IT_TE ((uint32_t)0x00000008)
#define DMA1_IT_GL1 ((uint32_t)0x00000001) #define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002) #define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004) #define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008) #define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010) #define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020) #define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040) #define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080) #define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100) #define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200) #define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400) #define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800) #define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000) #define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000) #define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000) #define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000) #define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000) #define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000) #define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000) #define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000) #define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000) #define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000) #define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000) #define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000) #define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000) #define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000) #define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000) #define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000) #define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA1_IT_GL8 ((uint32_t)0x10000000) #define DMA1_IT_GL8 ((uint32_t)0x10000000)
#define DMA1_IT_TC8 ((uint32_t)0x20000000) #define DMA1_IT_TC8 ((uint32_t)0x20000000)
#define DMA1_IT_HT8 ((uint32_t)0x40000000) #define DMA1_IT_HT8 ((uint32_t)0x40000000)
#define DMA1_IT_TE8 ((uint32_t)0x80000000) #define DMA1_IT_TE8 ((uint32_t)0x80000000)
/* DMA_flags_definition */ /* DMA_flags_definition */
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) #define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) #define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) #define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) #define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) #define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) #define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) #define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) #define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) #define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) #define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) #define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) #define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) #define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) #define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) #define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) #define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) #define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) #define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) #define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) #define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) #define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) #define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) #define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) #define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) #define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) #define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) #define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) #define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA1_FLAG_GL8 ((uint32_t)0x10000000) #define DMA1_FLAG_GL8 ((uint32_t)0x10000000)
#define DMA1_FLAG_TC8 ((uint32_t)0x20000000) #define DMA1_FLAG_TC8 ((uint32_t)0x20000000)
#define DMA1_FLAG_HT8 ((uint32_t)0x40000000) #define DMA1_FLAG_HT8 ((uint32_t)0x40000000)
#define DMA1_FLAG_TE8 ((uint32_t)0x80000000) #define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG); void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT); ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT); void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

198
Peripheral/inc/ch32x035_exti.h
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@ -1,99 +1,99 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_exti.h * File Name : ch32x035_exti.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* EXTI firmware library. * EXTI firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_EXTI_H #ifndef __CH32X035_EXTI_H
#define __CH32X035_EXTI_H #define __CH32X035_EXTI_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* EXTI mode enumeration */ /* EXTI mode enumeration */
typedef enum typedef enum
{ {
EXTI_Mode_Interrupt = 0x00, EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04 EXTI_Mode_Event = 0x04
} EXTIMode_TypeDef; } EXTIMode_TypeDef;
/* EXTI Trigger enumeration */ /* EXTI Trigger enumeration */
typedef enum typedef enum
{ {
EXTI_Trigger_Rising = 0x08, EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C, EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10 EXTI_Trigger_Rising_Falling = 0x10
} EXTITrigger_TypeDef; } EXTITrigger_TypeDef;
/* EXTI Init Structure definition */ /* EXTI Init Structure definition */
typedef struct typedef struct
{ {
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */ This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */ This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */ This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */ This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitTypeDef; } EXTI_InitTypeDef;
/* EXTI_Lines */ /* EXTI_Lines */
#define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */ #define EXTI_Line0 ((uint32_t)0x00000001) /* External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */ #define EXTI_Line1 ((uint32_t)0x00000002) /* External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */ #define EXTI_Line2 ((uint32_t)0x00000004) /* External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */ #define EXTI_Line3 ((uint32_t)0x00000008) /* External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */ #define EXTI_Line4 ((uint32_t)0x00000010) /* External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */ #define EXTI_Line5 ((uint32_t)0x00000020) /* External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */ #define EXTI_Line6 ((uint32_t)0x00000040) /* External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */ #define EXTI_Line7 ((uint32_t)0x00000080) /* External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */ #define EXTI_Line8 ((uint32_t)0x00000100) /* External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */ #define EXTI_Line9 ((uint32_t)0x00000200) /* External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */ #define EXTI_Line10 ((uint32_t)0x00000400) /* External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */ #define EXTI_Line11 ((uint32_t)0x00000800) /* External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */ #define EXTI_Line12 ((uint32_t)0x00001000) /* External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */ #define EXTI_Line13 ((uint32_t)0x00002000) /* External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */ #define EXTI_Line14 ((uint32_t)0x00004000) /* External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */ #define EXTI_Line15 ((uint32_t)0x00008000) /* External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 */ #define EXTI_Line16 ((uint32_t)0x00010000) /* External interrupt line 16 */
#define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 */ #define EXTI_Line17 ((uint32_t)0x00020000) /* External interrupt line 17 */
#define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 */ #define EXTI_Line18 ((uint32_t)0x00040000) /* External interrupt line 18 */
#define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 */ #define EXTI_Line19 ((uint32_t)0x00080000) /* External interrupt line 19 */
#define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 */ #define EXTI_Line20 ((uint32_t)0x00100000) /* External interrupt line 20 */
#define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 */ #define EXTI_Line21 ((uint32_t)0x00200000) /* External interrupt line 21 */
#define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 */ #define EXTI_Line22 ((uint32_t)0x00400000) /* External interrupt line 22 */
#define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 */ #define EXTI_Line23 ((uint32_t)0x00800000) /* External interrupt line 23 */
#define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the PC18(SDI on) */ #define EXTI_Line24 ((uint32_t)0x01000000) /* External interrupt line 24 Connected to the PC18(SDI on) */
#define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the PC19(SDI on) */ #define EXTI_Line25 ((uint32_t)0x02000000) /* External interrupt line 25 Connected to the PC19(SDI on) */
#define EXTI_Line26 ((uint32_t)0x04000000) /* External interrupt line 26 Connected to the PVD Output */ #define EXTI_Line26 ((uint32_t)0x04000000) /* External interrupt line 26 Connected to the PVD Output */
#define EXTI_Line27 ((uint32_t)0x08000000) /* External interrupt line 27 Connected to the Auto Wake-up event */ #define EXTI_Line27 ((uint32_t)0x08000000) /* External interrupt line 27 Connected to the Auto Wake-up event */
#define EXTI_Line28 ((uint32_t)0x10000000) /* External interrupt line 28 Connected to the the USBFS Wake-up event */ #define EXTI_Line28 ((uint32_t)0x10000000) /* External interrupt line 28 Connected to the the USBFS Wake-up event */
#define EXTI_Line29 ((uint32_t)0x20000000) /* External interrupt line 29 Connected to the the USB PD Wake-up event */ #define EXTI_Line29 ((uint32_t)0x20000000) /* External interrupt line 29 Connected to the the USB PD Wake-up event */
void EXTI_DeInit(void); void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct); void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct); void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line); void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line); void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

298
Peripheral/inc/ch32x035_flash.h
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@ -1,149 +1,149 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_flash.h * File Name : ch32x035_flash.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the FLASH * Description : This file contains all the functions prototypes for the FLASH
* firmware library. * firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_FLASH_H #ifndef __CH32X035_FLASH_H
#define __CH32X035_FLASH_H #define __CH32X035_FLASH_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* FLASH Status */ /* FLASH Status */
typedef enum typedef enum
{ {
FLASH_BUSY = 1, FLASH_BUSY = 1,
FLASH_ERROR_PG, FLASH_ERROR_PG,
FLASH_ERROR_WRP, FLASH_ERROR_WRP,
FLASH_COMPLETE, FLASH_COMPLETE,
FLASH_TIMEOUT, FLASH_TIMEOUT,
FLASH_RDP, FLASH_RDP,
FLASH_OP_RANGE_ERROR = 0xFD, FLASH_OP_RANGE_ERROR = 0xFD,
FLASH_ALIGN_ERROR = 0xFE, FLASH_ALIGN_ERROR = 0xFE,
FLASH_ADR_RANGE_ERROR = 0xFF, FLASH_ADR_RANGE_ERROR = 0xFF,
} FLASH_Status; } FLASH_Status;
/* Flash_Latency */ /* Flash_Latency */
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ #define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ #define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ #define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
/* Values to be used with devices (1page = 256Byte) */ /* Values to be used with devices (1page = 256Byte) */
#define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */ #define FLASH_WRProt_Pages0to7 ((uint32_t)0x00000001) /* Write protection of page 0 to 7 */
#define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */ #define FLASH_WRProt_Pages8to15 ((uint32_t)0x00000002) /* Write protection of page 8 to 15 */
#define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */ #define FLASH_WRProt_Pages16to23 ((uint32_t)0x00000004) /* Write protection of page 16 to 23 */
#define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */ #define FLASH_WRProt_Pages24to31 ((uint32_t)0x00000008) /* Write protection of page 24 to 31 */
#define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */ #define FLASH_WRProt_Pages32to39 ((uint32_t)0x00000010) /* Write protection of page 32 to 39 */
#define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */ #define FLASH_WRProt_Pages40to47 ((uint32_t)0x00000020) /* Write protection of page 40 to 47 */
#define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */ #define FLASH_WRProt_Pages48to55 ((uint32_t)0x00000040) /* Write protection of page 48 to 55 */
#define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */ #define FLASH_WRProt_Pages56to63 ((uint32_t)0x00000080) /* Write protection of page 56 to 63 */
#define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */ #define FLASH_WRProt_Pages64to71 ((uint32_t)0x00000100) /* Write protection of page 64 to 71 */
#define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */ #define FLASH_WRProt_Pages72to79 ((uint32_t)0x00000200) /* Write protection of page 72 to 79 */
#define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */ #define FLASH_WRProt_Pages80to87 ((uint32_t)0x00000400) /* Write protection of page 80 to 87 */
#define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */ #define FLASH_WRProt_Pages88to95 ((uint32_t)0x00000800) /* Write protection of page 88 to 95 */
#define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */ #define FLASH_WRProt_Pages96to103 ((uint32_t)0x00001000) /* Write protection of page 96 to 103 */
#define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */ #define FLASH_WRProt_Pages104to111 ((uint32_t)0x00002000) /* Write protection of page 104 to 111 */
#define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */ #define FLASH_WRProt_Pages112to119 ((uint32_t)0x00004000) /* Write protection of page 112 to 119 */
#define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */ #define FLASH_WRProt_Pages120to127 ((uint32_t)0x00008000) /* Write protection of page 120 to 127 */
#define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */ #define FLASH_WRProt_Pages128to135 ((uint32_t)0x00010000) /* Write protection of page 128 to 135 */
#define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */ #define FLASH_WRProt_Pages136to143 ((uint32_t)0x00020000) /* Write protection of page 136 to 143 */
#define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */ #define FLASH_WRProt_Pages144to151 ((uint32_t)0x00040000) /* Write protection of page 144 to 151 */
#define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */ #define FLASH_WRProt_Pages152to159 ((uint32_t)0x00080000) /* Write protection of page 152 to 159 */
#define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */ #define FLASH_WRProt_Pages160to167 ((uint32_t)0x00100000) /* Write protection of page 160 to 167 */
#define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */ #define FLASH_WRProt_Pages168to175 ((uint32_t)0x00200000) /* Write protection of page 168 to 175 */
#define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */ #define FLASH_WRProt_Pages176to183 ((uint32_t)0x00400000) /* Write protection of page 176 to 183 */
#define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */ #define FLASH_WRProt_Pages184to191 ((uint32_t)0x00800000) /* Write protection of page 184 to 191 */
#define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */ #define FLASH_WRProt_Pages192to199 ((uint32_t)0x01000000) /* Write protection of page 192 to 199 */
#define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */ #define FLASH_WRProt_Pages200to207 ((uint32_t)0x02000000) /* Write protection of page 200 to 207 */
#define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */ #define FLASH_WRProt_Pages208to215 ((uint32_t)0x04000000) /* Write protection of page 208 to 215 */
#define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */ #define FLASH_WRProt_Pages216to223 ((uint32_t)0x08000000) /* Write protection of page 216 to 223 */
#define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */ #define FLASH_WRProt_Pages224to231 ((uint32_t)0x10000000) /* Write protection of page 224 to 231 */
#define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */ #define FLASH_WRProt_Pages232to239 ((uint32_t)0x20000000) /* Write protection of page 232 to 239 */
#define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */ #define FLASH_WRProt_Pages240to247 ((uint32_t)0x40000000) /* Write protection of page 240 to 247 */
#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */ #define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
/* Option_Bytes_IWatchdog */ /* Option_Bytes_IWatchdog */
#define OB_IWDG_SW ((uint8_t)0x01) /* Software IWDG selected */ #define OB_IWDG_SW ((uint8_t)0x01) /* Software IWDG selected */
#define OB_IWDG_HW ((uint8_t)0x00) /* Hardware IWDG selected */ #define OB_IWDG_HW ((uint8_t)0x00) /* Hardware IWDG selected */
/* Option_Bytes_nRST_STOP */ /* Option_Bytes_nRST_STOP */
#define OB_STOP_NoRST ((uint8_t)0x02) /* No reset generated when entering in STOP */ #define OB_STOP_NoRST ((uint8_t)0x02) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint8_t)0x00) /* Reset generated when entering in STOP */ #define OB_STOP_RST ((uint8_t)0x00) /* Reset generated when entering in STOP */
/* Option_Bytes_nRST_STDBY */ /* Option_Bytes_nRST_STDBY */
#define OB_STDBY_NoRST ((uint8_t)0x04) /* No reset generated when entering in STANDBY */ #define OB_STDBY_NoRST ((uint8_t)0x04) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint8_t)0x00) /* Reset generated when entering in STANDBY */ #define OB_STDBY_RST ((uint8_t)0x00) /* Reset generated when entering in STANDBY */
/* Option_Bytes_RST_ENandDT */ /* Option_Bytes_RST_ENandDT */
#define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */ #define OB_RST_NoEN ((uint8_t)0x18) /* Reset IO disable */
#define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */ #define OB_RST_EN_DT12ms ((uint8_t)0x10) /* Reset IO enable and Ignore delay time 12ms */
#define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */ #define OB_RST_EN_DT1ms ((uint8_t)0x08) /* Reset IO enable and Ignore delay time 1ms */
#define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */ #define OB_RST_EN_DT128us ((uint8_t)0x00) /* Reset IO enable and Ignore delay time 128us */
/* FLASH_Interrupts */ /* FLASH_Interrupts */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ #define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ #define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
/* FLASH_Flags */ /* FLASH_Flags */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
/* System_Reset_Start_Mode */ /* System_Reset_Start_Mode */
#define Start_Mode_USER ((uint32_t)0x00000000) #define Start_Mode_USER ((uint32_t)0x00000000)
#define Start_Mode_BOOT ((uint32_t)0x00004000) #define Start_Mode_BOOT ((uint32_t)0x00004000)
/*Functions used for all CH32V00x devices*/ /*Functions used for all CH32V00x devices*/
void FLASH_SetLatency(uint32_t FLASH_Latency); void FLASH_SetLatency(uint32_t FLASH_Latency);
void FLASH_Unlock(void); void FLASH_Unlock(void);
void FLASH_Lock(void); void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address); FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void); FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void); FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages); FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
FLASH_Status FLASH_EnableReadOutProtection(void); FLASH_Status FLASH_EnableReadOutProtection(void);
FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST); FLASH_Status FLASH_UserOptionByteConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY, uint8_t OB_RST);
uint32_t FLASH_GetUserOptionByte(void); uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void); uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void); FlagStatus FLASH_GetReadOutProtectionStatus(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG); void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void); FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
void FLASH_Unlock_Fast(void); void FLASH_Unlock_Fast(void);
void FLASH_Lock_Fast(void); void FLASH_Lock_Fast(void);
void FLASH_BufReset(void); void FLASH_BufReset(void);
void FLASH_BufLoad(uint32_t Address, uint32_t Data0); void FLASH_BufLoad(uint32_t Address, uint32_t Data0);
void FLASH_ErasePage_Fast(uint32_t Page_Address); void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address); void FLASH_ProgramPage_Fast(uint32_t Page_Address);
void SystemReset_StartMode(uint32_t Mode); void SystemReset_StartMode(uint32_t Mode);
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

362
Peripheral/inc/ch32x035_gpio.h
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@ -1,181 +1,181 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_gpio.h * File Name : ch32x035_gpio.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* GPIO firmware library. * GPIO firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_GPIO_H #ifndef __CH32X035_GPIO_H
#define __CH32X035_GPIO_H #define __CH32X035_GPIO_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* Output Maximum frequency selection */ /* Output Maximum frequency selection */
typedef enum typedef enum
{ {
GPIO_Speed_50MHz = 1, GPIO_Speed_50MHz = 1,
} GPIOSpeed_TypeDef; } GPIOSpeed_TypeDef;
/* Configuration Mode enumeration */ /* Configuration Mode enumeration */
typedef enum typedef enum
{ {
GPIO_Mode_AIN = 0x0, GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04, GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28, /* Only PA0--PA15 and PC16--PC17 support input pull-down */ GPIO_Mode_IPD = 0x28, /* Only PA0--PA15 and PC16--PC17 support input pull-down */
GPIO_Mode_IPU = 0x48, GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_PP = 0x10, GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_PP = 0x18 GPIO_Mode_AF_PP = 0x18
} GPIOMode_TypeDef; } GPIOMode_TypeDef;
/* GPIO Init structure definition */ /* GPIO Init structure definition */
typedef struct typedef struct
{ {
uint32_t GPIO_Pin; /* Specifies the GPIO pins to be configured. uint32_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */ This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */ This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */ This parameter can be a value of @ref GPIOMode_TypeDef */
} GPIO_InitTypeDef; } GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */ /* Bit_SET and Bit_RESET enumeration */
typedef enum typedef enum
{ {
Bit_RESET = 0, Bit_RESET = 0,
Bit_SET Bit_SET
} BitAction; } BitAction;
/* GPIO_pins_define */ /* GPIO_pins_define */
#define GPIO_Pin_0 ((uint32_t)0x000001) /* Pin 0 selected */ #define GPIO_Pin_0 ((uint32_t)0x000001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint32_t)0x000002) /* Pin 1 selected */ #define GPIO_Pin_1 ((uint32_t)0x000002) /* Pin 1 selected */
#define GPIO_Pin_2 ((uint32_t)0x000004) /* Pin 2 selected */ #define GPIO_Pin_2 ((uint32_t)0x000004) /* Pin 2 selected */
#define GPIO_Pin_3 ((uint32_t)0x000008) /* Pin 3 selected */ #define GPIO_Pin_3 ((uint32_t)0x000008) /* Pin 3 selected */
#define GPIO_Pin_4 ((uint32_t)0x000010) /* Pin 4 selected */ #define GPIO_Pin_4 ((uint32_t)0x000010) /* Pin 4 selected */
#define GPIO_Pin_5 ((uint32_t)0x000020) /* Pin 5 selected */ #define GPIO_Pin_5 ((uint32_t)0x000020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint32_t)0x000040) /* Pin 6 selected */ #define GPIO_Pin_6 ((uint32_t)0x000040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint32_t)0x000080) /* Pin 7 selected */ #define GPIO_Pin_7 ((uint32_t)0x000080) /* Pin 7 selected */
#define GPIO_Pin_8 ((uint32_t)0x000100) /* Pin 8 selected */ #define GPIO_Pin_8 ((uint32_t)0x000100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint32_t)0x000200) /* Pin 9 selected */ #define GPIO_Pin_9 ((uint32_t)0x000200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint32_t)0x000400) /* Pin 10 selected */ #define GPIO_Pin_10 ((uint32_t)0x000400) /* Pin 10 selected */
#define GPIO_Pin_11 ((uint32_t)0x000800) /* Pin 11 selected */ #define GPIO_Pin_11 ((uint32_t)0x000800) /* Pin 11 selected */
#define GPIO_Pin_12 ((uint32_t)0x001000) /* Pin 12 selected */ #define GPIO_Pin_12 ((uint32_t)0x001000) /* Pin 12 selected */
#define GPIO_Pin_13 ((uint32_t)0x002000) /* Pin 13 selected */ #define GPIO_Pin_13 ((uint32_t)0x002000) /* Pin 13 selected */
#define GPIO_Pin_14 ((uint32_t)0x004000) /* Pin 14 selected */ #define GPIO_Pin_14 ((uint32_t)0x004000) /* Pin 14 selected */
#define GPIO_Pin_15 ((uint32_t)0x008000) /* Pin 15 selected */ #define GPIO_Pin_15 ((uint32_t)0x008000) /* Pin 15 selected */
#define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */ #define GPIO_Pin_16 ((uint32_t)0x010000) /* Pin 16 selected */
#define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */ #define GPIO_Pin_17 ((uint32_t)0x020000) /* Pin 17 selected */
#define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */ #define GPIO_Pin_18 ((uint32_t)0x040000) /* Pin 18 selected */
#define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */ #define GPIO_Pin_19 ((uint32_t)0x080000) /* Pin 19 selected */
#define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */ #define GPIO_Pin_20 ((uint32_t)0x100000) /* Pin 20 selected */
#define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */ #define GPIO_Pin_21 ((uint32_t)0x200000) /* Pin 21 selected */
#define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */ #define GPIO_Pin_22 ((uint32_t)0x400000) /* Pin 22 selected */
#define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */ #define GPIO_Pin_23 ((uint32_t)0x800000) /* Pin 23 selected */
#define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */ #define GPIO_Pin_All ((uint32_t)0xFFFFFF) /* All pins selected */
/* GPIO_Remap_define */ /* GPIO_Remap_define */
/* PCFR1 */ /* PCFR1 */
#define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_SPI1 ((uint32_t)0x00100001) /* SPI1 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_SPI1 ((uint32_t)0x00100002) /* SPI1 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */ #define GPIO_FullRemap_SPI1 ((uint32_t)0x00100003) /* SPI1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08000004) /* I2C1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_I2C1 ((uint32_t)0x08000004) /* I2C1 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08000008) /* I2C1 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_I2C1 ((uint32_t)0x08000008) /* I2C1 Partial2 Alternate Function mapping */
#define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0800000C) /* I2C1 Partial3 Alternate Function mapping */ #define GPIO_PartialRemap3_I2C1 ((uint32_t)0x0800000C) /* I2C1 Partial3 Alternate Function mapping */
#define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08000010) /* I2C1 Partial4 Alternate Function mapping */ #define GPIO_PartialRemap4_I2C1 ((uint32_t)0x08000010) /* I2C1 Partial4 Alternate Function mapping */
#define GPIO_FullRemap_I2C1 ((uint32_t)0x08000014) /* I2C1 Full Alternate Function mapping */ #define GPIO_FullRemap_I2C1 ((uint32_t)0x08000014) /* I2C1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_USART1 ((uint32_t)0x00150020) /* USART1 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_USART1 ((uint32_t)0x00150040) /* USART1 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */ #define GPIO_FullRemap_USART1 ((uint32_t)0x00150060) /* USART1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_USART2 ((uint32_t)0x08000080) /* USART2 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_USART2 ((uint32_t)0x08000080) /* USART2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_USART2 ((uint32_t)0x08000100) /* USART2 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_USART2 ((uint32_t)0x08000100) /* USART2 Partial2 Alternate Function mapping */
#define GPIO_PartialRemap3_USART2 ((uint32_t)0x08000180) /* USART2 Partial3 Alternate Function mapping */ #define GPIO_PartialRemap3_USART2 ((uint32_t)0x08000180) /* USART2 Partial3 Alternate Function mapping */
#define GPIO_FullRemap_USART2 ((uint32_t)0x08000200) /* USART2 Full Alternate Function mapping */ #define GPIO_FullRemap_USART2 ((uint32_t)0x08000200) /* USART2 Full Alternate Function mapping */
#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00100400) /* USART3 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_USART3 ((uint32_t)0x00100400) /* USART3 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_USART3 ((uint32_t)0x00100800) /* USART3 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_USART3 ((uint32_t)0x00100800) /* USART3 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00100C00) /* USART3 Full Alternate Function mapping */ #define GPIO_FullRemap_USART3 ((uint32_t)0x00100C00) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap1_USART4 ((uint32_t)0x08001000) /* USART4 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_USART4 ((uint32_t)0x08001000) /* USART4 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_USART4 ((uint32_t)0x08002000) /* USART4 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_USART4 ((uint32_t)0x08002000) /* USART4 Partial2 Alternate Function mapping */
#define GPIO_PartialRemap3_USART4 ((uint32_t)0x08003000) /* USART4 Partial3 Alternate Function mapping */ #define GPIO_PartialRemap3_USART4 ((uint32_t)0x08003000) /* USART4 Partial3 Alternate Function mapping */
#define GPIO_PartialRemap4_USART4 ((uint32_t)0x08004000) /* USART4 Partial4 Alternate Function mapping */ #define GPIO_PartialRemap4_USART4 ((uint32_t)0x08004000) /* USART4 Partial4 Alternate Function mapping */
#define GPIO_FullRemap_USART4 ((uint32_t)0x08007000) /* USART4 Full Alternate Function mapping */ #define GPIO_FullRemap_USART4 ((uint32_t)0x08007000) /* USART4 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x08400001) /* TIM1 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_TIM1 ((uint32_t)0x08400001) /* TIM1 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x08400002) /* TIM1 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_TIM1 ((uint32_t)0x08400002) /* TIM1 Partial2 Alternate Function mapping */
#define GPIO_PartialRemap3_TIM1 ((uint32_t)0x08400003) /* TIM1 Partial3 Alternate Function mapping */ #define GPIO_PartialRemap3_TIM1 ((uint32_t)0x08400003) /* TIM1 Partial3 Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x08400004) /* TIM1 Full Alternate Function mapping */ #define GPIO_FullRemap_TIM1 ((uint32_t)0x08400004) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08200004) /* TIM2 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x08200004) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08200008) /* TIM2 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x08200008) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0820000C) /* TIM2 Partial3 Alternate Function mapping */ #define GPIO_PartialRemap3_TIM2 ((uint32_t)0x0820000C) /* TIM2 Partial3 Alternate Function mapping */
#define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08200010) /* TIM2 Partial4 Alternate Function mapping */ #define GPIO_PartialRemap4_TIM2 ((uint32_t)0x08200010) /* TIM2 Partial4 Alternate Function mapping */
#define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08200014) /* TIM2 Partial5 Alternate Function mapping */ #define GPIO_PartialRemap5_TIM2 ((uint32_t)0x08200014) /* TIM2 Partial5 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x08200018) /* TIM2 Full Alternate Function mapping */ #define GPIO_FullRemap_TIM2 ((uint32_t)0x08200018) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00300020) /* TIM3 Partial1 Alternate Function mapping */ #define GPIO_PartialRemap1_TIM3 ((uint32_t)0x00300020) /* TIM3 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00300040) /* TIM3 Partial2 Alternate Function mapping */ #define GPIO_PartialRemap2_TIM3 ((uint32_t)0x00300040) /* TIM3 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x00300060) /* TIM3 Full Alternate Function mapping */ #define GPIO_FullRemap_TIM3 ((uint32_t)0x00300060) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */ #define GPIO_Remap_PIOC ((uint32_t)0x00200080) /* PIOC Alternate Function mapping */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */ #define GPIO_Remap_SWJ_Disable ((uint32_t)0x08300400) /* SDI Disabled (SDI) */
/* GPIO_Port_Sources */ /* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00) #define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01) #define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02) #define GPIO_PortSourceGPIOC ((uint8_t)0x02)
/* GPIO_Pin_sources */ /* GPIO_Pin_sources */
#define GPIO_PinSource0 ((uint8_t)0x00) #define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01) #define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02) #define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03) #define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04) #define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05) #define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06) #define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07) #define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08) #define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09) #define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A) #define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B) #define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C) #define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D) #define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E) #define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F) #define GPIO_PinSource15 ((uint8_t)0x0F)
#define GPIO_PinSource16 ((uint8_t)0x10) #define GPIO_PinSource16 ((uint8_t)0x10)
#define GPIO_PinSource17 ((uint8_t)0x11) #define GPIO_PinSource17 ((uint8_t)0x11)
#define GPIO_PinSource18 ((uint8_t)0x12) #define GPIO_PinSource18 ((uint8_t)0x12)
#define GPIO_PinSource19 ((uint8_t)0x13) #define GPIO_PinSource19 ((uint8_t)0x13)
#define GPIO_PinSource20 ((uint8_t)0x14) #define GPIO_PinSource20 ((uint8_t)0x14)
#define GPIO_PinSource21 ((uint8_t)0x15) #define GPIO_PinSource21 ((uint8_t)0x15)
#define GPIO_PinSource22 ((uint8_t)0x16) #define GPIO_PinSource22 ((uint8_t)0x16)
#define GPIO_PinSource23 ((uint8_t)0x17) #define GPIO_PinSource23 ((uint8_t)0x17)
void GPIO_DeInit(GPIO_TypeDef *GPIOx); void GPIO_DeInit(GPIO_TypeDef *GPIOx);
void GPIO_AFIODeInit(void); void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); uint32_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); uint32_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal); void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal); void GPIO_Write(GPIO_TypeDef *GPIOx, uint32_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource); void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint16_t GPIO_PinSource);
void GPIO_IPD_Unused(void); void GPIO_IPD_Unused(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

832
Peripheral/inc/ch32x035_i2c.h
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@ -1,416 +1,416 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_i2c.h * File Name : ch32x035_i2c.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* I2C firmware library. * I2C firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_I2C_H #ifndef __CH32X035_I2C_H
#define __CH32X035_I2C_H #define __CH32X035_I2C_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* I2C Init structure definition */ /* I2C Init structure definition */
typedef struct typedef struct
{ {
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
This parameter must be set to a value lower than 400kHz */ This parameter must be set to a value lower than 400kHz */
uint16_t I2C_Mode; /* Specifies the I2C mode. uint16_t I2C_Mode; /* Specifies the I2C mode.
This parameter can be a value of @ref I2C_mode */ This parameter can be a value of @ref I2C_mode */
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
uint16_t I2C_OwnAddress1; /* Specifies the first device own address. uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
This parameter can be a 7-bit or 10-bit address. */ This parameter can be a 7-bit or 10-bit address. */
uint16_t I2C_Ack; /* Enables or disables the acknowledgement. uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
This parameter can be a value of @ref I2C_acknowledgement */ This parameter can be a value of @ref I2C_acknowledgement */
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
This parameter can be a value of @ref I2C_acknowledged_address */ This parameter can be a value of @ref I2C_acknowledged_address */
} I2C_InitTypeDef; } I2C_InitTypeDef;
/* I2C_mode */ /* I2C_mode */
#define I2C_Mode_I2C ((uint16_t)0x0000) #define I2C_Mode_I2C ((uint16_t)0x0000)
/* I2C_duty_cycle_in_fast_mode */ /* I2C_duty_cycle_in_fast_mode */
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
/* I2C_acknowledgement */ /* I2C_acknowledgement */
#define I2C_Ack_Enable ((uint16_t)0x0400) #define I2C_Ack_Enable ((uint16_t)0x0400)
#define I2C_Ack_Disable ((uint16_t)0x0000) #define I2C_Ack_Disable ((uint16_t)0x0000)
/* I2C_transfer_direction */ /* I2C_transfer_direction */
#define I2C_Direction_Transmitter ((uint8_t)0x00) #define I2C_Direction_Transmitter ((uint8_t)0x00)
#define I2C_Direction_Receiver ((uint8_t)0x01) #define I2C_Direction_Receiver ((uint8_t)0x01)
/* I2C_acknowledged_address */ /* I2C_acknowledged_address */
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
/* I2C_registers */ /* I2C_registers */
#define I2C_Register_CTLR1 ((uint8_t)0x00) #define I2C_Register_CTLR1 ((uint8_t)0x00)
#define I2C_Register_CTLR2 ((uint8_t)0x04) #define I2C_Register_CTLR2 ((uint8_t)0x04)
#define I2C_Register_OADDR1 ((uint8_t)0x08) #define I2C_Register_OADDR1 ((uint8_t)0x08)
#define I2C_Register_OADDR2 ((uint8_t)0x0C) #define I2C_Register_OADDR2 ((uint8_t)0x0C)
#define I2C_Register_DATAR ((uint8_t)0x10) #define I2C_Register_DATAR ((uint8_t)0x10)
#define I2C_Register_STAR1 ((uint8_t)0x14) #define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18) #define I2C_Register_STAR2 ((uint8_t)0x18)
#define I2C_Register_CKCFGR ((uint8_t)0x1C) #define I2C_Register_CKCFGR ((uint8_t)0x1C)
#define I2C_Register_RTR ((uint8_t)0x20) #define I2C_Register_RTR ((uint8_t)0x20)
/* I2C_PEC_position */ /* I2C_PEC_position */
#define I2C_PECPosition_Next ((uint16_t)0x0800) #define I2C_PECPosition_Next ((uint16_t)0x0800)
#define I2C_PECPosition_Current ((uint16_t)0xF7FF) #define I2C_PECPosition_Current ((uint16_t)0xF7FF)
/* I2C_NACK_position */ /* I2C_NACK_position */
#define I2C_NACKPosition_Next ((uint16_t)0x0800) #define I2C_NACKPosition_Next ((uint16_t)0x0800)
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) #define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
/* I2C_interrupts_definition */ /* I2C_interrupts_definition */
#define I2C_IT_BUF ((uint16_t)0x0400) #define I2C_IT_BUF ((uint16_t)0x0400)
#define I2C_IT_EVT ((uint16_t)0x0200) #define I2C_IT_EVT ((uint16_t)0x0200)
#define I2C_IT_ERR ((uint16_t)0x0100) #define I2C_IT_ERR ((uint16_t)0x0100)
/* I2C_interrupts_definition */ /* I2C_interrupts_definition */
#define I2C_IT_PECERR ((uint32_t)0x01001000) #define I2C_IT_PECERR ((uint32_t)0x01001000)
#define I2C_IT_OVR ((uint32_t)0x01000800) #define I2C_IT_OVR ((uint32_t)0x01000800)
#define I2C_IT_AF ((uint32_t)0x01000400) #define I2C_IT_AF ((uint32_t)0x01000400)
#define I2C_IT_ARLO ((uint32_t)0x01000200) #define I2C_IT_ARLO ((uint32_t)0x01000200)
#define I2C_IT_BERR ((uint32_t)0x01000100) #define I2C_IT_BERR ((uint32_t)0x01000100)
#define I2C_IT_TXE ((uint32_t)0x06000080) #define I2C_IT_TXE ((uint32_t)0x06000080)
#define I2C_IT_RXNE ((uint32_t)0x06000040) #define I2C_IT_RXNE ((uint32_t)0x06000040)
#define I2C_IT_STOPF ((uint32_t)0x02000010) #define I2C_IT_STOPF ((uint32_t)0x02000010)
#define I2C_IT_ADD10 ((uint32_t)0x02000008) #define I2C_IT_ADD10 ((uint32_t)0x02000008)
#define I2C_IT_BTF ((uint32_t)0x02000004) #define I2C_IT_BTF ((uint32_t)0x02000004)
#define I2C_IT_ADDR ((uint32_t)0x02000002) #define I2C_IT_ADDR ((uint32_t)0x02000002)
#define I2C_IT_SB ((uint32_t)0x02000001) #define I2C_IT_SB ((uint32_t)0x02000001)
/* SR2 register flags */ /* SR2 register flags */
#define I2C_FLAG_DUALF ((uint32_t)0x00800000) #define I2C_FLAG_DUALF ((uint32_t)0x00800000)
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) #define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
#define I2C_FLAG_TRA ((uint32_t)0x00040000) #define I2C_FLAG_TRA ((uint32_t)0x00040000)
#define I2C_FLAG_BUSY ((uint32_t)0x00020000) #define I2C_FLAG_BUSY ((uint32_t)0x00020000)
#define I2C_FLAG_MSL ((uint32_t)0x00010000) #define I2C_FLAG_MSL ((uint32_t)0x00010000)
/* SR1 register flags */ /* SR1 register flags */
#define I2C_FLAG_PECERR ((uint32_t)0x10001000) #define I2C_FLAG_PECERR ((uint32_t)0x10001000)
#define I2C_FLAG_OVR ((uint32_t)0x10000800) #define I2C_FLAG_OVR ((uint32_t)0x10000800)
#define I2C_FLAG_AF ((uint32_t)0x10000400) #define I2C_FLAG_AF ((uint32_t)0x10000400)
#define I2C_FLAG_ARLO ((uint32_t)0x10000200) #define I2C_FLAG_ARLO ((uint32_t)0x10000200)
#define I2C_FLAG_BERR ((uint32_t)0x10000100) #define I2C_FLAG_BERR ((uint32_t)0x10000100)
#define I2C_FLAG_TXE ((uint32_t)0x10000080) #define I2C_FLAG_TXE ((uint32_t)0x10000080)
#define I2C_FLAG_RXNE ((uint32_t)0x10000040) #define I2C_FLAG_RXNE ((uint32_t)0x10000040)
#define I2C_FLAG_STOPF ((uint32_t)0x10000010) #define I2C_FLAG_STOPF ((uint32_t)0x10000010)
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) #define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
#define I2C_FLAG_BTF ((uint32_t)0x10000004) #define I2C_FLAG_BTF ((uint32_t)0x10000004)
#define I2C_FLAG_ADDR ((uint32_t)0x10000002) #define I2C_FLAG_ADDR ((uint32_t)0x10000002)
#define I2C_FLAG_SB ((uint32_t)0x10000001) #define I2C_FLAG_SB ((uint32_t)0x10000001)
/****************I2C Master Events (Events grouped in order of communication)********************/ /****************I2C Master Events (Events grouped in order of communication)********************/
/******************************************************************************************************************** /********************************************************************************************************************
* @brief Start communicate * @brief Start communicate
* *
* After master use I2C_GenerateSTART() function sending the START condition,the master * After master use I2C_GenerateSTART() function sending the START condition,the master
* has to wait for event 5(the Start condition has been correctly * has to wait for event 5(the Start condition has been correctly
* released on the I2C bus ). * released on the I2C bus ).
* *
*/ */
/* EVT5 */ /* EVT5 */
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
/******************************************************************************************************************** /********************************************************************************************************************
* @brief Address Acknowledge * @brief Address Acknowledge
* *
* When start condition correctly released on the bus(check EVT5), the * When start condition correctly released on the bus(check EVT5), the
* master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
* it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
* his address. If an acknowledge is sent on the bus, one of the following events will be set: * his address. If an acknowledge is sent on the bus, one of the following events will be set:
* *
* *
* *
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
* event is set. * event is set.
* *
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
* is set * is set
* *
* 3) In case of 10-Bit addressing mode, the master (after generating the START * 3) In case of 10-Bit addressing mode, the master (after generating the START
* and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
* Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
* on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
* of the 10-bit address (LSB) . Then master should wait for event 6. * of the 10-bit address (LSB) . Then master should wait for event 6.
* *
* *
*/ */
/* EVT6 */ /* EVT6 */
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
/*EVT9 */ /*EVT9 */
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
/******************************************************************************************************************** /********************************************************************************************************************
* @brief Communication events * @brief Communication events
* *
* If START condition has generated and slave address * If START condition has generated and slave address
* been acknowledged. then the master has to check one of the following events for * been acknowledged. then the master has to check one of the following events for
* communication procedures: * communication procedures:
* *
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use * 1) Master Receiver mode: The master has to wait on the event EVT7 then use
* I2C_ReceiveData() function to read the data received from the slave . * I2C_ReceiveData() function to read the data received from the slave .
* *
* 2) Master Transmitter mode: The master use I2C_SendData() function to send data * 2) Master Transmitter mode: The master use I2C_SendData() function to send data
* then to wait on event EVT8 or EVT8_2. * then to wait on event EVT8 or EVT8_2.
* These two events are similar: * These two events are similar:
* - EVT8 means that the data has been written in the data register and is * - EVT8 means that the data has been written in the data register and is
* being shifted out. * being shifted out.
* - EVT8_2 means that the data has been physically shifted out and output * - EVT8_2 means that the data has been physically shifted out and output
* on the bus. * on the bus.
* In most cases, using EVT8 is sufficient for the application. * In most cases, using EVT8 is sufficient for the application.
* Using EVT8_2 will leads to a slower communication speed but will more reliable . * Using EVT8_2 will leads to a slower communication speed but will more reliable .
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
* *
* *
* Note: * Note:
* In case the user software does not guarantee that this event EVT7 is managed before * In case the user software does not guarantee that this event EVT7 is managed before
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
* *
* *
*/ */
/* Master Receive mode */ /* Master Receive mode */
/* EVT7 */ /* EVT7 */
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
/* Master Transmitter mode*/ /* Master Transmitter mode*/
/* EVT8 */ /* EVT8 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
/* EVT8_2 */ /* EVT8_2 */
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
/******************I2C Slave Events (Events grouped in order of communication)******************/ /******************I2C Slave Events (Events grouped in order of communication)******************/
/******************************************************************************************************************** /********************************************************************************************************************
* @brief Start Communicate events * @brief Start Communicate events
* *
* Wait on one of these events at the start of the communication. It means that * Wait on one of these events at the start of the communication. It means that
* the I2C peripheral detected a start condition of master device generate on the bus. * the I2C peripheral detected a start condition of master device generate on the bus.
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
* *
* *
* *
* a) In normal case (only one address managed by the slave), when the address * a) In normal case (only one address managed by the slave), when the address
* sent by the master matches the own address of the peripheral (configured by * sent by the master matches the own address of the peripheral (configured by
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
* (where XXX could be TRANSMITTER or RECEIVER). * (where XXX could be TRANSMITTER or RECEIVER).
* *
* b) In case the address sent by the master matches the second address of the * b) In case the address sent by the master matches the second address of the
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
* (where XXX could be TRANSMITTER or RECEIVER) are set. * (where XXX could be TRANSMITTER or RECEIVER) are set.
* *
* c) In case the address sent by the master is General Call (address 0x00) and * c) In case the address sent by the master is General Call (address 0x00) and
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
* *
*/ */
/* EVT1 */ /* EVT1 */
/* a) Case of One Single Address managed by the slave */ /* a) Case of One Single Address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
/* b) Case of Dual address managed by the slave */ /* b) Case of Dual address managed by the slave */
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
/* c) Case of General Call enabled for the slave */ /* c) Case of General Call enabled for the slave */
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
/******************************************************************************************************************** /********************************************************************************************************************
* @brief Communication events * @brief Communication events
* *
* Wait on one of these events when EVT1 has already been checked : * Wait on one of these events when EVT1 has already been checked :
* *
* - Slave Receiver mode: * - Slave Receiver mode:
* - EVT2--The device is expecting to receive a data byte . * - EVT2--The device is expecting to receive a data byte .
* - EVT4--The device is expecting the end of the communication: master * - EVT4--The device is expecting the end of the communication: master
* sends a stop condition and data transmission is stopped. * sends a stop condition and data transmission is stopped.
* *
* - Slave Transmitter mode: * - Slave Transmitter mode:
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting * - EVT3--When a byte has been transmitted by the slave and the Master is expecting
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
* the EVT3 is managed before the current byte end of transfer The second one can optionally * the EVT3 is managed before the current byte end of transfer The second one can optionally
* be used. * be used.
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission * - EVT3_2--When the master sends a NACK to tell slave device that data transmission
* shall end . The slave device has to stop sending * shall end . The slave device has to stop sending
* data bytes and wait a Stop condition from bus. * data bytes and wait a Stop condition from bus.
* *
* Note: * Note:
* If the user software does not guarantee that the event 2 is * If the user software does not guarantee that the event 2 is
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
* and I2C_FLAG_BTF flag at the same time . * and I2C_FLAG_BTF flag at the same time .
* In this case the communication will be slower. * In this case the communication will be slower.
* *
*/ */
/* Slave Receiver mode*/ /* Slave Receiver mode*/
/* EVT2 */ /* EVT2 */
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
/* EVT4 */ /* EVT4 */
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
/* Slave Transmitter mode*/ /* Slave Transmitter mode*/
/* EVT3 */ /* EVT3 */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
/*EVT3_2 */ /*EVT3_2 */
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
void I2C_DeInit(I2C_TypeDef *I2Cx); void I2C_DeInit(I2C_TypeDef *I2Cx);
void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct); void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct); void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address); void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState); void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data); void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx); uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx);
void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction); void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register); uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition); void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition); void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx); uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx);
void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState); void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle); void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
/***************************************************************************************** /*****************************************************************************************
* *
* I2C State Monitoring Functions * I2C State Monitoring Functions
* *
**************************************************************************************** ****************************************************************************************
* This I2C driver provides three different ways for I2C state monitoring * This I2C driver provides three different ways for I2C state monitoring
* profit the application requirements and constraints: * profit the application requirements and constraints:
* *
* *
* a) First way: * a) First way:
* Using I2C_CheckEvent() function: * Using I2C_CheckEvent() function:
* It compares the status registers (STARR1 and STAR2) content to a given event * It compares the status registers (STARR1 and STAR2) content to a given event
* (can be the combination of more flags). * (can be the combination of more flags).
* If the current status registers includes the given flags will return SUCCESS. * If the current status registers includes the given flags will return SUCCESS.
* and if the current status registers miss flags will returns ERROR. * and if the current status registers miss flags will returns ERROR.
* - When to use: * - When to use:
* - This function is suitable for most applications as well as for startup * - This function is suitable for most applications as well as for startup
* activity since the events are fully described in the product reference manual * activity since the events are fully described in the product reference manual
* (CH64xRM). * (CH64xRM).
* - It is also suitable for users who need to define their own events. * - It is also suitable for users who need to define their own events.
* - Limitations: * - Limitations:
* - If an error occurs besides to the monitored error, * - If an error occurs besides to the monitored error,
* the I2C_CheckEvent() function may return SUCCESS despite the communication * the I2C_CheckEvent() function may return SUCCESS despite the communication
* in corrupted state. it is suggeted to use error interrupts to monitor the error * in corrupted state. it is suggeted to use error interrupts to monitor the error
* events and handle them in IRQ handler. * events and handle them in IRQ handler.
* *
* *
* Note: * Note:
* The following functions are recommended for error management: : * The following functions are recommended for error management: :
* - I2C_ITConfig() main function of configure and enable the error interrupts. * - I2C_ITConfig() main function of configure and enable the error interrupts.
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
* Where x is the peripheral instance (I2C1, I2C2 ...) * Where x is the peripheral instance (I2C1, I2C2 ...)
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
* to determine which error occurred. * to determine which error occurred.
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
* \ I2C_GenerateStop() will be use to clear the error flag and source, * \ I2C_GenerateStop() will be use to clear the error flag and source,
* and return to correct communication status. * and return to correct communication status.
* *
* *
* b) Second way: * b) Second way:
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2. * Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
* - When to use: * - When to use:
* *
* - This function is suitable for the same applications above but it * - This function is suitable for the same applications above but it
* don't have the limitations of I2C_GetFlagStatus() function . * don't have the limitations of I2C_GetFlagStatus() function .
* The returned value could be compared to events already defined in the * The returned value could be compared to events already defined in the
* library (ch64x_i2c.h) or to custom values defined by user. * library (ch64x_i2c.h) or to custom values defined by user.
* - This function can be used to monitor the status of multiple flags simultaneously. * - This function can be used to monitor the status of multiple flags simultaneously.
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to * - Contrary to the I2C_CheckEvent () function, this function can choose the time to
* accept the event according to the user's needs (when all event flags are set and * accept the event according to the user's needs (when all event flags are set and
* no other flags are set, or only when the required flags are set) * no other flags are set, or only when the required flags are set)
* *
* - Limitations: * - Limitations:
* - User may need to define his own events. * - User may need to define his own events.
* - Same remark concerning the error management is applicable for this * - Same remark concerning the error management is applicable for this
* function if user decides to check only regular communication flags (and * function if user decides to check only regular communication flags (and
* ignores error flags). * ignores error flags).
* *
* *
* c) Third way: * c) Third way:
* Using the function I2C_GetFlagStatus() get the status of * Using the function I2C_GetFlagStatus() get the status of
* one single flag . * one single flag .
* - When to use: * - When to use:
* - This function could be used for specific applications or in debug phase. * - This function could be used for specific applications or in debug phase.
* - It is suitable when only one flag checking is needed . * - It is suitable when only one flag checking is needed .
* *
* - Limitations: * - Limitations:
* - Call this function to access the status register. Some flag bits may be cleared. * - Call this function to access the status register. Some flag bits may be cleared.
* - Function may need to be called twice or more in order to monitor one single event. * - Function may need to be called twice or more in order to monitor one single event.
*/ */
/********************************************************* /*********************************************************
* *
* a) Basic state monitoring(First way) * a) Basic state monitoring(First way)
******************************************************** ********************************************************
*/ */
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
/********************************************************* /*********************************************************
* *
* b) Advanced state monitoring(Second way:) * b) Advanced state monitoring(Second way:)
******************************************************** ********************************************************
*/ */
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
/********************************************************* /*********************************************************
* *
* c) Flag-based state monitoring(Third way) * c) Flag-based state monitoring(Third way)
********************************************************* *********************************************************
*/ */
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG); void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT); ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT); void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

100
Peripheral/inc/ch32x035_iwdg.h
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@ -1,50 +1,50 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_iwdg.h * File Name : ch32x035_iwdg.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* IWDG firmware library. * IWDG firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_IWDG_H #ifndef __CH32X035_IWDG_H
#define __CH32X035_IWDG_H #define __CH32X035_IWDG_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* IWDG_WriteAccess */ /* IWDG_WriteAccess */
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
/* IWDG_prescaler */ /* IWDG_prescaler */
#define IWDG_Prescaler_4 ((uint8_t)0x00) #define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01) #define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02) #define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03) #define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04) #define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05) #define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06) #define IWDG_Prescaler_256 ((uint8_t)0x06)
/* IWDG_Flag */ /* IWDG_Flag */
#define IWDG_FLAG_PVU ((uint16_t)0x0001) #define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002) #define IWDG_FLAG_RVU ((uint16_t)0x0002)
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload); void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void); void IWDG_ReloadCounter(void);
void IWDG_Enable(void); void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_misc.h
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@ -1,45 +1,45 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_misc.h * File Name : ch32x035_misc.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* miscellaneous firmware library functions. * miscellaneous firmware library functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_MISC_H #ifndef __CH32X035_MISC_H
#define __CH32X035_MISC_H #define __CH32X035_MISC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* NVIC Init Structure definition */ /* NVIC Init Structure definition */
typedef struct typedef struct
{ {
uint8_t NVIC_IRQChannel; uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority; uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority; uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd; FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef; } NVIC_InitTypeDef;
/* Preemption_Priority_Group */ /* Preemption_Priority_Group */
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) #define NVIC_PriorityGroup_0 ((uint32_t)0x00)
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) #define NVIC_PriorityGroup_1 ((uint32_t)0x01)
#define NVIC_PriorityGroup_2 ((uint32_t)0x02) #define NVIC_PriorityGroup_2 ((uint32_t)0x02)
#define NVIC_PriorityGroup_3 ((uint32_t)0x03) #define NVIC_PriorityGroup_3 ((uint32_t)0x03)
#define NVIC_PriorityGroup_4 ((uint32_t)0x04) #define NVIC_PriorityGroup_4 ((uint32_t)0x04)
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_opa.h
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@ -1,221 +1,221 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_opa.h * File Name : ch32x035_opa.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* OPA firmware library. * OPA firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_OPA_H #ifndef __CH32X035_OPA_H
#define __CH32X035_OPA_H #define __CH32X035_OPA_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* OPA_member_enumeration */ /* OPA_member_enumeration */
typedef enum typedef enum
{ {
OPA1 = 0, OPA1 = 0,
OPA2 OPA2
} OPA_Num_TypeDef; } OPA_Num_TypeDef;
/* OPA_out_channel_enumeration */ /* OPA_out_channel_enumeration */
typedef enum typedef enum
{ {
OUT_IO_OUT0 = 0, OUT_IO_OUT0 = 0,
OUT_IO_OUT1 OUT_IO_OUT1
} OPA_Mode_TypeDef; } OPA_Mode_TypeDef;
/* OPA_PSEL_enumeration */ /* OPA_PSEL_enumeration */
typedef enum typedef enum
{ {
CHP0 = 0, CHP0 = 0,
CHP1, CHP1,
CHP2, CHP2,
CHP_OFF CHP_OFF
} OPA_PSEL_TypeDef; } OPA_PSEL_TypeDef;
/* OPA_FB_enumeration */ /* OPA_FB_enumeration */
typedef enum typedef enum
{ {
FB_OFF = 0, FB_OFF = 0,
FB_ON FB_ON
} OPA_FB_TypeDef; } OPA_FB_TypeDef;
/* OPA_NSEL_enumeration */ /* OPA_NSEL_enumeration */
typedef enum typedef enum
{ {
CHN0 = 0, CHN0 = 0,
CHN1, CHN1,
CHN2_PGA_16xIN, CHN2_PGA_16xIN,
CHN_PGA_4xIN, CHN_PGA_4xIN,
CHN_PGA_8xIN, CHN_PGA_8xIN,
CHN_PGA_16xIN, CHN_PGA_16xIN,
CHN_PGA_32xIN, CHN_PGA_32xIN,
CHN_OFF CHN_OFF
} OPA_NSEL_TypeDef; } OPA_NSEL_TypeDef;
/* OPA_PSEL_POLL_enumeration */ /* OPA_PSEL_POLL_enumeration */
typedef enum typedef enum
{ {
CHP_OPA1_OFF_OPA2_OFF = 0, CHP_OPA1_OFF_OPA2_OFF = 0,
CHP_OPA1_ON_OPA2_OFF, CHP_OPA1_ON_OPA2_OFF,
CHP_OPA1_OFF_OPA2_ON, CHP_OPA1_OFF_OPA2_ON,
CHP_OPA1_ON_OPA2_ON CHP_OPA1_ON_OPA2_ON
} OPA_PSEL_POLL_TypeDef; } OPA_PSEL_POLL_TypeDef;
/* OPA_BKIN_EN_enumeration */ /* OPA_BKIN_EN_enumeration */
typedef enum typedef enum
{ {
BKIN_OPA1_OFF_OPA2_OFF = 0, BKIN_OPA1_OFF_OPA2_OFF = 0,
BKIN_OPA1_ON_OPA2_OFF, BKIN_OPA1_ON_OPA2_OFF,
BKIN_OPA1_OFF_OPA2_ON, BKIN_OPA1_OFF_OPA2_ON,
BKIN_OPA1_ON_OPA2_ON BKIN_OPA1_ON_OPA2_ON
} OPA_BKIN_EN_TypeDef; } OPA_BKIN_EN_TypeDef;
/* OPA_RST_EN_enumeration */ /* OPA_RST_EN_enumeration */
typedef enum typedef enum
{ {
RST_OPA1_OFF_OPA2_OFF = 0, RST_OPA1_OFF_OPA2_OFF = 0,
RST_OPA1_ON_OPA2_OFF, RST_OPA1_ON_OPA2_OFF,
RST_OPA1_OFF_OPA2_ON, RST_OPA1_OFF_OPA2_ON,
RST_OPA1_ON_OPA2_ON RST_OPA1_ON_OPA2_ON
} OPA_RST_EN_TypeDef; } OPA_RST_EN_TypeDef;
/* OPA_BKIN_SEL_enumeration */ /* OPA_BKIN_SEL_enumeration */
typedef enum typedef enum
{ {
BKIN_OPA1_TIM1_OPA2_TIM2 = 0, BKIN_OPA1_TIM1_OPA2_TIM2 = 0,
BKIN_OPA1_TIM2_OPA2_TIM1 BKIN_OPA1_TIM2_OPA2_TIM1
} OPA_BKIN_SEL_TypeDef; } OPA_BKIN_SEL_TypeDef;
/* OPA_OUT_IE_enumeration */ /* OPA_OUT_IE_enumeration */
typedef enum typedef enum
{ {
OUT_IE_OPA1_OFF_OPA2_OFF = 0, OUT_IE_OPA1_OFF_OPA2_OFF = 0,
OUT_IE_OPA1_ON_OPA2_OFF, OUT_IE_OPA1_ON_OPA2_OFF,
OUT_IE_OPA1_OFF_OPA2_ON, OUT_IE_OPA1_OFF_OPA2_ON,
OUT_IE_OPA1_ON_OPA2_ON OUT_IE_OPA1_ON_OPA2_ON
} OPA_OUT_IE_TypeDef; } OPA_OUT_IE_TypeDef;
/* OPA_CNT_IE_enumeration */ /* OPA_CNT_IE_enumeration */
typedef enum typedef enum
{ {
CNT_IE_OFF = 0, CNT_IE_OFF = 0,
CNT_IE_ON, CNT_IE_ON,
} OPA_CNT_IE_TypeDef; } OPA_CNT_IE_TypeDef;
/* OPA_NMI_IE_enumeration */ /* OPA_NMI_IE_enumeration */
typedef enum typedef enum
{ {
NMI_IE_OFF = 0, NMI_IE_OFF = 0,
NMI_IE_ON, NMI_IE_ON,
} OPA_NMI_IE_TypeDef; } OPA_NMI_IE_TypeDef;
/* OPA_PSEL_POLL_NUM_enumeration */ /* OPA_PSEL_POLL_NUM_enumeration */
typedef enum typedef enum
{ {
CHP_POLL_NUM_1 = 0, CHP_POLL_NUM_1 = 0,
CHP_POLL_NUM_2, CHP_POLL_NUM_2,
CHP_POLL_NUM_3 CHP_POLL_NUM_3
} OPA_PSEL_POLL_NUM_TypeDef; } OPA_PSEL_POLL_NUM_TypeDef;
/* OPA Init Structure definition */ /* OPA Init Structure definition */
typedef struct typedef struct
{ {
uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us uint16_t OPA_POLL_Interval; /* OPA polling interval = (OPA_POLL_Interval+1)*1us
This parameter must range from 0 to 0x1FF.*/ This parameter must range from 0 to 0x1FF.*/
OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */
OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */ OPA_FB_TypeDef FB; /* Specifies the internal feedback resistor of OPA */
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */ OPA_PSEL_POLL_TypeDef PSEL_POLL; /* Specifies the positive channel poll of OPA */
OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */ OPA_BKIN_EN_TypeDef BKIN_EN; /* Specifies the brake input source of OPA */
OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */ OPA_RST_EN_TypeDef RST_EN; /* Specifies the reset source of OPA */
OPA_BKIN_SEL_TypeDef BKIN_SEL; /* Specifies the brake input source selection of OPA */ OPA_BKIN_SEL_TypeDef BKIN_SEL; /* Specifies the brake input source selection of OPA */
OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */ OPA_OUT_IE_TypeDef OUT_IE; /* Specifies the out interrupt of OPA */
OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */ OPA_CNT_IE_TypeDef CNT_IE; /* Specifies the out interrupt rising edge of sampling data */
OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */ OPA_NMI_IE_TypeDef NMI_IE; /* Specifies the out NIM interrupt of OPA */
OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/ OPA_PSEL_POLL_NUM_TypeDef POLL_NUM; /* Specifies the number of forward inputs*/
} OPA_InitTypeDef; } OPA_InitTypeDef;
/* CMP_member_enumeration */ /* CMP_member_enumeration */
typedef enum typedef enum
{ {
CMP1 = 0, CMP1 = 0,
CMP2, CMP2,
CMP3 CMP3
} CMP_Num_TypeDef; } CMP_Num_TypeDef;
/* CMP_out_channel_enumeration */ /* CMP_out_channel_enumeration */
typedef enum typedef enum
{ {
OUT_IO_TIM2 = 0, OUT_IO_TIM2 = 0,
OUT_IO0 OUT_IO0
} CMP_Mode_TypeDef; } CMP_Mode_TypeDef;
/* CMP_NSEL_enumeration */ /* CMP_NSEL_enumeration */
typedef enum typedef enum
{ {
CMP_CHN0 = 0, CMP_CHN0 = 0,
CMP_CHN1, CMP_CHN1,
} CMP_NSEL_TypeDef; } CMP_NSEL_TypeDef;
/* CMP_PSEL_enumeration */ /* CMP_PSEL_enumeration */
typedef enum typedef enum
{ {
CMP_CHP1 = 0, CMP_CHP1 = 0,
CMP_CHP2, CMP_CHP2,
} CMP_PSEL_TypeDef; } CMP_PSEL_TypeDef;
/* CMP_HYEN_enumeration */ /* CMP_HYEN_enumeration */
typedef enum typedef enum
{ {
CMP_HYEN1 = 0, CMP_HYEN1 = 0,
CMP_HYEN2, CMP_HYEN2,
} CMP_HYEN_TypeDef; } CMP_HYEN_TypeDef;
/* CMP Init Structure definition */ /* CMP Init Structure definition */
typedef struct typedef struct
{ {
CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */ CMP_Num_TypeDef CMP_NUM; /* Specifies the members of CMP */
CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */ CMP_Mode_TypeDef Mode; /* Specifies the mode of CMP */
CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */ CMP_NSEL_TypeDef NSEL; /* Specifies the negative channel of CMP */
CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */ CMP_PSEL_TypeDef PSEL; /* Specifies the positive channel of CMP */
CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */ CMP_HYEN_TypeDef HYEN; /* Specifies the hysteresis comparator of CMP */
} CMP_InitTypeDef; } CMP_InitTypeDef;
/* OPA_flags_definition */ /* OPA_flags_definition */
#define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000) #define OPA_FLAG_OUT_OPA1 ((uint16_t)0x1000)
#define OPA_FLAG_OUT_OPA2 ((uint16_t)0x2000) #define OPA_FLAG_OUT_OPA2 ((uint16_t)0x2000)
#define OPA_FLAG_OUT_CNT ((uint16_t)0x4000) #define OPA_FLAG_OUT_CNT ((uint16_t)0x4000)
void OPA_Unlock(void); void OPA_Unlock(void);
void OPA_Lock(void); void OPA_Lock(void);
void OPA_POLL_Unlock(void); void OPA_POLL_Unlock(void);
void OPA_POLL_Lock(void); void OPA_POLL_Lock(void);
void OPA_CMP_Unlock(void); void OPA_CMP_Unlock(void);
void OPA_CMP_Lock(void); void OPA_CMP_Lock(void);
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct); void OPA_Init(OPA_InitTypeDef *OPA_InitStruct);
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct); void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct);
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct); void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct);
void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct); void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct);
void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState); void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState);
FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG); FlagStatus OPA_GetFlagStatus( uint16_t OPA_FLAG);
void OPA_ClearFlag(uint16_t OPA_FLAG); void OPA_ClearFlag(uint16_t OPA_FLAG);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_pwr.h
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@ -1,50 +1,50 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_pwr.h * File Name : ch32x035_pwr.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the PWR * Description : This file contains all the functions prototypes for the PWR
* firmware library. * firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_PWR_H #ifndef __CH32X035_PWR_H
#define __CH32X035_PWR_H #define __CH32X035_PWR_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* PVD_detection_level */ /* PVD_detection_level */
#define PWR_PVDLevel_2V1 ((uint32_t)0x00000000) #define PWR_PVDLevel_2V1 ((uint32_t)0x00000000)
#define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020)
#define PWR_PVDLevel_3V0 ((uint32_t)0x00000040) #define PWR_PVDLevel_3V0 ((uint32_t)0x00000040)
#define PWR_PVDLevel_4V0 ((uint32_t)0x00000060) #define PWR_PVDLevel_4V0 ((uint32_t)0x00000060)
/* STOP_mode_entry */ /* STOP_mode_entry */
#define PWR_STOPEntry_WFI ((uint8_t)0x01) #define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02) #define PWR_STOPEntry_WFE ((uint8_t)0x02)
/* PWR_Flag */ /* PWR_Flag */
#define PWR_FLAG_PVDO ((uint32_t)0x00000004) #define PWR_FLAG_PVDO ((uint32_t)0x00000004)
#define PWR_FLAG_FLASH ((uint32_t)0x00000020) #define PWR_FLAG_FLASH ((uint32_t)0x00000020)
/* PWR_VDD_Supply_Voltage */ /* PWR_VDD_Supply_Voltage */
typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD; typedef enum {PWR_VDD_5V = 0, PWR_VDD_3V3 = !PWR_VDD_5V} PWR_VDD;
void PWR_DeInit(void); void PWR_DeInit(void);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry); void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void); void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
PWR_VDD PWR_VDD_SupplyVoltage(void); PWR_VDD PWR_VDD_SupplyVoltage(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_rcc.h
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@ -1,111 +1,111 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_rcc.h * File Name : ch32x035_rcc.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the RCC firmware functions. * Description : This file provides all the RCC firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_RCC_H #ifndef __CH32X035_RCC_H
#define __CH32X035_RCC_H #define __CH32X035_RCC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* RCC_Exported_Types */ /* RCC_Exported_Types */
typedef struct typedef struct
{ {
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
} RCC_ClocksTypeDef; } RCC_ClocksTypeDef;
/* AHB_clock_source */ /* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010) #define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020) #define RCC_SYSCLK_Div3 ((uint32_t)0x00000020)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030) #define RCC_SYSCLK_Div4 ((uint32_t)0x00000030)
#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040) #define RCC_SYSCLK_Div5 ((uint32_t)0x00000040)
#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050) #define RCC_SYSCLK_Div6 ((uint32_t)0x00000050)
#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060) #define RCC_SYSCLK_Div7 ((uint32_t)0x00000060)
#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070) #define RCC_SYSCLK_Div8 ((uint32_t)0x00000070)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0) #define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0) #define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0) #define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0) #define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
/* AHB_peripheral */ /* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) #define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_IO2W ((uint32_t)0x00002000) #define RCC_AHBPeriph_IO2W ((uint32_t)0x00002000)
#define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000) #define RCC_AHBPeriph_USBPD ((uint32_t)0x00020000)
/* APB2_peripheral */ /* APB2_peripheral */
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
/* APB1_peripheral */ /* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_USART4 ((uint32_t)0x00080000) #define RCC_APB1Periph_USART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) #define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
/* Clock_source_to_output_on_MCO_pin */ /* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_NoClock ((uint8_t)0x00) #define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04) #define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05) #define RCC_MCO_HSI ((uint8_t)0x05)
/* RCC_Flag */ /* RCC_Flag */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21) #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_OPARST ((uint8_t)0x79) #define RCC_FLAG_OPARST ((uint8_t)0x79)
#define RCC_FLAG_PINRST ((uint8_t)0x7A) #define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B) #define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C) #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/* SysTick_clock_source */ /* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
void RCC_DeInit(void); void RCC_DeInit(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState); void RCC_HSICmd(FunctionalState NewState);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK); void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO); void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void); void RCC_ClearFlag(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_spi.h
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/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_spi.h * File Name : ch32x035_spi.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* SPI firmware library. * SPI firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_SPI_H #ifndef __CH32X035_SPI_H
#define __CH32X035_SPI_H #define __CH32X035_SPI_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* SPI Init structure definition */ /* SPI Init structure definition */
typedef struct typedef struct
{ {
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */ This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /* Specifies the SPI operating mode. uint16_t SPI_Mode; /* Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */ This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /* Specifies the SPI data size. uint16_t SPI_DataSize; /* Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */ This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /* Specifies the serial clock steady state. uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */ This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */ This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit. hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */ This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock. used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler. This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master @note The communication clock is derived from the master
clock. The slave clock does not need to be set. */ clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_transmission */ This parameter can be a value of @ref SPI_MSB_transmission */
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
} SPI_InitTypeDef; } SPI_InitTypeDef;
/* SPI_data_direction */ /* SPI_data_direction */
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) #define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) #define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
/* SPI_mode */ /* SPI_mode */
#define SPI_Mode_Master ((uint16_t)0x0104) #define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000) #define SPI_Mode_Slave ((uint16_t)0x0000)
/* SPI_data_size */ /* SPI_data_size */
#define SPI_DataSize_16b ((uint16_t)0x0800) #define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000) #define SPI_DataSize_8b ((uint16_t)0x0000)
/* SPI_Clock_Polarity */ /* SPI_Clock_Polarity */
#define SPI_CPOL_Low ((uint16_t)0x0000) #define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002) #define SPI_CPOL_High ((uint16_t)0x0002)
/* SPI_Clock_Phase */ /* SPI_Clock_Phase */
#define SPI_CPHA_1Edge ((uint16_t)0x0000) #define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001) #define SPI_CPHA_2Edge ((uint16_t)0x0001)
/* SPI_Slave_Select_management */ /* SPI_Slave_Select_management */
#define SPI_NSS_Soft ((uint16_t)0x0200) #define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000) #define SPI_NSS_Hard ((uint16_t)0x0000)
/* SPI_BaudRate_Prescaler */ /* SPI_BaudRate_Prescaler */
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
/* SPI_MSB_LSB_transmission */ /* SPI_MSB_LSB_transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000) #define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode #define SPI_FirstBit_LSB ((uint16_t)0x0080)//not support SPI slave mode
/* SPI_I2S_DMA_transfer_requests */ /* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
/* SPI_NSS_internal_software_management */ /* SPI_NSS_internal_software_management */
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
/* SPI_CRC_Transmit_Receive */ /* SPI_CRC_Transmit_Receive */
#define SPI_CRC_Tx ((uint8_t)0x00) #define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01) #define SPI_CRC_Rx ((uint8_t)0x01)
/* SPI_direction_transmit_receive */ /* SPI_direction_transmit_receive */
#define SPI_Direction_Rx ((uint16_t)0xBFFF) #define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000) #define SPI_Direction_Tx ((uint16_t)0x4000)
/* SPI_I2S_interrupts_definition */ /* SPI_I2S_interrupts_definition */
#define SPI_I2S_IT_TXE ((uint8_t)0x71) #define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60) #define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50) #define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define SPI_I2S_IT_OVR ((uint8_t)0x56) #define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55) #define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54) #define SPI_IT_CRCERR ((uint8_t)0x54)
/* SPI_I2S_flags_definition */ /* SPI_I2S_flags_definition */
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010) #define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020) #define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
void SPI_I2S_DeInit(SPI_TypeDef *SPIx); void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct); void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct); void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState); void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data); void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx); uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft); void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState); void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize); void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef *SPIx); void SPI_TransmitCRC(SPI_TypeDef *SPIx);
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState); void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC); uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx); uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction); void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG); void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT); void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_tim.h
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Peripheral/inc/ch32x035_usart.h
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/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_usart.h * File Name : ch32x035_usart.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the * Description : This file contains all the functions prototypes for the
* USART firmware library. * USART firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_USART_H #ifndef __CH32X035_USART_H
#define __CH32X035_USART_H #define __CH32X035_USART_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* USART Init Structure definition */ /* USART Init Structure definition */
typedef struct typedef struct
{ {
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
The baud rate is computed using the following formula: The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */ This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */ This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /* Specifies the parity mode. uint16_t USART_Parity; /* Specifies the parity mode.
This parameter can be a value of @ref USART_Parity This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted @note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */ word length is set to 8 data bits). */
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */ This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
or disabled. or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */ This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef; } USART_InitTypeDef;
/* USART Clock Init Structure definition */ /* USART Clock Init Structure definition */
typedef struct typedef struct
{ {
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */ This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */ This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */ This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode. data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */ This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef; } USART_ClockInitTypeDef;
/* USART_Word_Length */ /* USART_Word_Length */
#define USART_WordLength_8b ((uint16_t)0x0000) #define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000) #define USART_WordLength_9b ((uint16_t)0x1000)
/* USART_Stop_Bits */ /* USART_Stop_Bits */
#define USART_StopBits_1 ((uint16_t)0x0000) #define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000) #define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000) #define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000) #define USART_StopBits_1_5 ((uint16_t)0x3000)
/* USART_Parity */ /* USART_Parity */
#define USART_Parity_No ((uint16_t)0x0000) #define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400) #define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600) #define USART_Parity_Odd ((uint16_t)0x0600)
/* USART_Mode */ /* USART_Mode */
#define USART_Mode_Rx ((uint16_t)0x0004) #define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008) #define USART_Mode_Tx ((uint16_t)0x0008)
/* USART_Hardware_Flow_Control */ /* USART_Hardware_Flow_Control */
#define USART_HardwareFlowControl_None ((uint16_t)0x0000) #define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
/* USART_Clock */ /* USART_Clock */
#define USART_Clock_Disable ((uint16_t)0x0000) #define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800) #define USART_Clock_Enable ((uint16_t)0x0800)
/* USART_Clock_Polarity */ /* USART_Clock_Polarity */
#define USART_CPOL_Low ((uint16_t)0x0000) #define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400) #define USART_CPOL_High ((uint16_t)0x0400)
/* USART_Clock_Phase */ /* USART_Clock_Phase */
#define USART_CPHA_1Edge ((uint16_t)0x0000) #define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200) #define USART_CPHA_2Edge ((uint16_t)0x0200)
/* USART_Last_Bit */ /* USART_Last_Bit */
#define USART_LastBit_Disable ((uint16_t)0x0000) #define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100) #define USART_LastBit_Enable ((uint16_t)0x0100)
/* USART_Interrupt_definition */ /* USART_Interrupt_definition */
#define USART_IT_PE ((uint16_t)0x0028) #define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727) #define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626) #define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525) #define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_ORE_RX ((uint16_t)0x0325) #define USART_IT_ORE_RX ((uint16_t)0x0325)
#define USART_IT_IDLE ((uint16_t)0x0424) #define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846) #define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A) #define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060) #define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE_ER ((uint16_t)0x0360) #define USART_IT_ORE_ER ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260) #define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160) #define USART_IT_FE ((uint16_t)0x0160)
#define USART_IT_ORE USART_IT_ORE_ER #define USART_IT_ORE USART_IT_ORE_ER
/* USART_DMA_Requests */ /* USART_DMA_Requests */
#define USART_DMAReq_Tx ((uint16_t)0x0080) #define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040) #define USART_DMAReq_Rx ((uint16_t)0x0040)
/* USART_WakeUp_methods */ /* USART_WakeUp_methods */
#define USART_WakeUp_IdleLine ((uint16_t)0x0000) #define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800) #define USART_WakeUp_AddressMark ((uint16_t)0x0800)
/* USART_LIN_Break_Detection_Length */ /* USART_LIN_Break_Detection_Length */
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
/* USART_IrDA_Low_Power */ /* USART_IrDA_Low_Power */
#define USART_IrDAMode_LowPower ((uint16_t)0x0004) #define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000) #define USART_IrDAMode_Normal ((uint16_t)0x0000)
/* USART_Flags */ /* USART_Flags */
#define USART_FLAG_CTS ((uint16_t)0x0200) #define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100) #define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080) #define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040) #define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020) #define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010) #define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008) #define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004) #define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002) #define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001) #define USART_FLAG_PE ((uint16_t)0x0001)
void USART_DeInit(USART_TypeDef *USARTx); void USART_DeInit(USART_TypeDef *USARTx);
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
void USART_StructInit(USART_InitTypeDef *USART_InitStruct); void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef *USARTx); uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
void USART_SendBreak(USART_TypeDef *USARTx); void USART_SendBreak(USART_TypeDef *USARTx);
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_usb.h
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Peripheral/inc/ch32x035_usbpd.h
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/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_usbpd.h * File Name : ch32x035_usbpd.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the USBPD * Description : This file contains all the functions prototypes for the USBPD
* firmware library. * firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_USBPD_H #ifndef __CH32X035_USBPD_H
#define __CH32X035_USBPD_H #define __CH32X035_USBPD_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
#ifndef VOID #ifndef VOID
#define VOID void #define VOID void
#endif #endif
#ifndef CONST #ifndef CONST
#define CONST const #define CONST const
#endif #endif
#ifndef BOOL #ifndef BOOL
typedef unsigned char BOOL; typedef unsigned char BOOL;
#endif #endif
#ifndef BOOLEAN #ifndef BOOLEAN
typedef unsigned char BOOLEAN; typedef unsigned char BOOLEAN;
#endif #endif
#ifndef CHAR #ifndef CHAR
typedef char CHAR; typedef char CHAR;
#endif #endif
#ifndef INT8 #ifndef INT8
typedef char INT8; typedef char INT8;
#endif #endif
#ifndef INT16 #ifndef INT16
typedef short INT16; typedef short INT16;
#endif #endif
#ifndef INT32 #ifndef INT32
typedef long INT32; typedef long INT32;
#endif #endif
#ifndef UINT8 #ifndef UINT8
typedef unsigned char UINT8; typedef unsigned char UINT8;
#endif #endif
#ifndef UINT16 #ifndef UINT16
typedef unsigned short UINT16; typedef unsigned short UINT16;
#endif #endif
#ifndef UINT32 #ifndef UINT32
typedef unsigned long UINT32; typedef unsigned long UINT32;
#endif #endif
#ifndef UINT8V #ifndef UINT8V
typedef unsigned char volatile UINT8V; typedef unsigned char volatile UINT8V;
#endif #endif
#ifndef UINT16V #ifndef UINT16V
typedef unsigned short volatile UINT16V; typedef unsigned short volatile UINT16V;
#endif #endif
#ifndef UINT32V #ifndef UINT32V
typedef unsigned long volatile UINT32V; typedef unsigned long volatile UINT32V;
#endif #endif
#ifndef PVOID #ifndef PVOID
typedef void *PVOID; typedef void *PVOID;
#endif #endif
#ifndef PCHAR #ifndef PCHAR
typedef char *PCHAR; typedef char *PCHAR;
#endif #endif
#ifndef PCHAR #ifndef PCHAR
typedef const char *PCCHAR; typedef const char *PCCHAR;
#endif #endif
#ifndef PINT8 #ifndef PINT8
typedef char *PINT8; typedef char *PINT8;
#endif #endif
#ifndef PINT16 #ifndef PINT16
typedef short *PINT16; typedef short *PINT16;
#endif #endif
#ifndef PINT32 #ifndef PINT32
typedef long *PINT32; typedef long *PINT32;
#endif #endif
#ifndef PUINT8 #ifndef PUINT8
typedef unsigned char *PUINT8; typedef unsigned char *PUINT8;
#endif #endif
#ifndef PUINT16 #ifndef PUINT16
typedef unsigned short *PUINT16; typedef unsigned short *PUINT16;
#endif #endif
#ifndef PUINT32 #ifndef PUINT32
typedef unsigned long *PUINT32; typedef unsigned long *PUINT32;
#endif #endif
#ifndef PUINT8V #ifndef PUINT8V
typedef volatile unsigned char *PUINT8V; typedef volatile unsigned char *PUINT8V;
#endif #endif
#ifndef PUINT16V #ifndef PUINT16V
typedef volatile unsigned short *PUINT16V; typedef volatile unsigned short *PUINT16V;
#endif #endif
#ifndef PUINT32V #ifndef PUINT32V
typedef volatile unsigned long *PUINT32V; typedef volatile unsigned long *PUINT32V;
#endif #endif
/******************************************************************************/ /******************************************************************************/
/* Related macro definitions */ /* Related macro definitions */
/* Define the return value of the function */ /* Define the return value of the function */
#ifndef SUCCESS #ifndef SUCCESS
#define SUCCESS 0 #define SUCCESS 0
#endif #endif
#ifndef FAIL #ifndef FAIL
#define FAIL 0xFF #define FAIL 0xFF
#endif #endif
/* Register Bit Definition */ /* Register Bit Definition */
/* USBPD->CONFIG */ /* USBPD->CONFIG */
#define PD_FILT_ED (1<<0) /* PD pin input filter enable */ #define PD_FILT_ED (1<<0) /* PD pin input filter enable */
#define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */ #define PD_ALL_CLR (1<<1) /* Clear all interrupt flags */
#define CC_SEL (1<<2) /* Select PD communication port */ #define CC_SEL (1<<2) /* Select PD communication port */
#define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */ #define PD_DMA_EN (1<<3) /* Enable DMA for USBPD */
#define PD_RST_EN (1<<4) /* PD mode reset command enable */ #define PD_RST_EN (1<<4) /* PD mode reset command enable */
#define WAKE_POLAR (1<<5) /* PD port wake-up level */ #define WAKE_POLAR (1<<5) /* PD port wake-up level */
#define IE_PD_IO (1<<10) /* PD IO interrupt enable */ #define IE_PD_IO (1<<10) /* PD IO interrupt enable */
#define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */ #define IE_RX_BIT (1<<11) /* Receive bit interrupt enable */
#define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */ #define IE_RX_BYTE (1<<12) /* Receive byte interrupt enable */
#define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */ #define IE_RX_ACT (1<<13) /* Receive completion interrupt enable */
#define IE_RX_RESET (1<<14) /* Reset interrupt enable */ #define IE_RX_RESET (1<<14) /* Reset interrupt enable */
#define IE_TX_END (1<<15) /* Transfer completion interrupt enable */ #define IE_TX_END (1<<15) /* Transfer completion interrupt enable */
/* USBPD->CONTROL */ /* USBPD->CONTROL */
#define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */ #define PD_TX_EN (1<<0) /* USBPD transceiver mode and transmit enable */
#define BMC_START (1<<1) /* BMC send start signal */ #define BMC_START (1<<1) /* BMC send start signal */
#define RX_STATE_0 (1<<2) /* PD received state bit 0 */ #define RX_STATE_0 (1<<2) /* PD received state bit 0 */
#define RX_STATE_1 (1<<3) /* PD received state bit 1 */ #define RX_STATE_1 (1<<3) /* PD received state bit 1 */
#define RX_STATE_2 (1<<4) /* PD received state bit 2 */ #define RX_STATE_2 (1<<4) /* PD received state bit 2 */
#define DATA_FLAG (1<<5) /* Cache data valid flag bit */ #define DATA_FLAG (1<<5) /* Cache data valid flag bit */
#define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */ #define TX_BIT_BACK (1<<6) /* Indicates the current bit status of the BMC when sending the code */
#define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */ #define BMC_BYTE_HI (1<<7) /* Indicates the current half-byte status of the PD data being sent and received */
/* USBPD->TX_SEL */ /* USBPD->TX_SEL */
#define TX_SEL1 (0<<0) #define TX_SEL1 (0<<0)
#define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */ #define TX_SEL1_SYNC1 (0<<0) /* 0-SYNC1 */
#define TX_SEL1_RST1 (1<<0) /* 1-RST1 */ #define TX_SEL1_RST1 (1<<0) /* 1-RST1 */
#define TX_SEL2_Mask (3<<2) #define TX_SEL2_Mask (3<<2)
#define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */ #define TX_SEL2_SYNC1 (0<<2) /* 00-SYNC1 */
#define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */ #define TX_SEL2_SYNC3 (1<<2) /* 01-SYNC3 */
#define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */ #define TX_SEL2_RST1 (2<<2) /* 1x-RST1 */
#define TX_SEL3_Mask (3<<4) #define TX_SEL3_Mask (3<<4)
#define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */ #define TX_SEL3_SYNC1 (0<<4) /* 00-SYNC1 */
#define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */ #define TX_SEL3_SYNC3 (1<<4) /* 01-SYNC3 */
#define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */ #define TX_SEL3_RST1 (2<<4) /* 1x-RST1 */
#define TX_SEL4_Mask (3<<6) #define TX_SEL4_Mask (3<<6)
#define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */ #define TX_SEL4_SYNC2 (0<<6) /* 00-SYNC2 */
#define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */ #define TX_SEL4_SYNC3 (1<<6) /* 01-SYNC3 */
#define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */ #define TX_SEL4_RST2 (2<<6) /* 1x-RST2 */
/* USBPD->STATUS */ /* USBPD->STATUS */
#define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */ #define BMC_AUX_Mask (3<<0) /* Clear BMC auxiliary information */
#define BMC_AUX_INVALID (0<<0) /* 00-Invalid */ #define BMC_AUX_INVALID (0<<0) /* 00-Invalid */
#define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */ #define BMC_AUX_SOP0 (1<<0) /* 01-SOP0 */
#define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */ #define BMC_AUX_SOP1_HRST (2<<0) /* 10-SOP1 hard reset */
#define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */ #define BMC_AUX_SOP2_CRST (3<<0) /* 11-SOP2 cable reset */
#define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */ #define BUF_ERR (1<<2) /* BUFFER or DMA error interrupt flag */
#define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */ #define IF_RX_BIT (1<<3) /* Receive bit or 5bit interrupt flag */
#define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */ #define IF_RX_BYTE (1<<4) /* Receive byte or SOP interrupt flag */
#define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */ #define IF_RX_ACT (1<<5) /* Receive completion interrupt flag */
#define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */ #define IF_RX_RESET (1<<6) /* Receive reset interrupt flag */
#define IF_TX_END (1<<7) /* Transfer completion interrupt flag */ #define IF_TX_END (1<<7) /* Transfer completion interrupt flag */
/* USBPD->PORT_CC1 */ /* USBPD->PORT_CC1 */
/* USBPD->PORT_CC2 */ /* USBPD->PORT_CC2 */
#define PA_CC_AI (1<<0) /* CC port comparator analogue input */ #define PA_CC_AI (1<<0) /* CC port comparator analogue input */
#define CC_PD (1<<1) /* CC port pull-down resistor enable */ #define CC_PD (1<<1) /* CC port pull-down resistor enable */
#define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */ #define CC_PU_Mask (3<<2) /* Clear CC port pull-up current */
#define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */ #define CC_NO_PU (0<<2) /* 00-Prohibit pull-up current */
#define CC_PU_330 (1<<2) /* 01-330uA */ #define CC_PU_330 (1<<2) /* 01-330uA */
#define CC_PU_180 (2<<2) /* 10-180uA */ #define CC_PU_180 (2<<2) /* 10-180uA */
#define CC_PU_80 (3<<2) /* 11-80uA */ #define CC_PU_80 (3<<2) /* 11-80uA */
#define CC_LVE (1<<4) /* CC port output low voltage enable */ #define CC_LVE (1<<4) /* CC port output low voltage enable */
#define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/ #define CC_CMP_Mask (7<<5) /* Clear CC_CMP*/
#define CC_NO_CMP (0<<5) /* 000-closed */ #define CC_NO_CMP (0<<5) /* 000-closed */
#define CC_CMP_22 (2<<5) /* 010-0.22V */ #define CC_CMP_22 (2<<5) /* 010-0.22V */
#define CC_CMP_45 (3<<5) /* 011-0.45V */ #define CC_CMP_45 (3<<5) /* 011-0.45V */
#define CC_CMP_55 (4<<5) /* 100-0.55V */ #define CC_CMP_55 (4<<5) /* 100-0.55V */
#define CC_CMP_66 (5<<5) /* 101-0.66V */ #define CC_CMP_66 (5<<5) /* 101-0.66V */
#define CC_CMP_95 (6<<5) /* 110-0.95V */ #define CC_CMP_95 (6<<5) /* 110-0.95V */
#define CC_CMP_123 (7<<5) /* 111-1.23V */ #define CC_CMP_123 (7<<5) /* 111-1.23V */
#define USBPD_IN_HVT (1<<9) #define USBPD_IN_HVT (1<<9)
/********************************************************* /*********************************************************
* PD pin PC14/PC15 high threshold input mode: * PD pin PC14/PC15 high threshold input mode:
* 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication * 1-High threshold input (2.2V typical), to reduce the I/O power consumption during PD communication
* 0-Normal GPIO threshold input * 0-Normal GPIO threshold input
* *******************************************************/ * *******************************************************/
#define USBPD_PHY_V33 (1<<8) #define USBPD_PHY_V33 (1<<8)
/********************************************************** /**********************************************************
* PD transceiver PHY pull-up limit configuration bits: * PD transceiver PHY pull-up limit configuration bits:
* 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V * 1-Direct use of VDD for GPIO applications or PD applications with VDD voltage of 3.3V
* 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V * 0-LDO buck enabled, limited to approx 3.3V, for PD applications with VDD more than 4V
* ********************************************************/ * ********************************************************/
/* Control Message Types */ /* Control Message Types */
#define DEF_TYPE_RESERVED 0x00 #define DEF_TYPE_RESERVED 0x00
#define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_GOODCRC 0x01 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */ #define DEF_TYPE_GOTOMIN 0x02 /* Send By: Source */
#define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_ACCEPT 0x03 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_REJECT 0x04 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_PING 0x05 /* Send By: Source */ #define DEF_TYPE_PING 0x05 /* Send By: Source */
#define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */ #define DEF_TYPE_PS_RDY 0x06 /* Send By: Source,Sink */
#define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */ #define DEF_TYPE_GET_SRC_CAP 0x07 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */ #define DEF_TYPE_GET_SNK_CAP 0x08 /* Send By: Source,DRP */
#define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */ #define DEF_TYPE_DR_SWAP 0x09 /* Send By: Source,Sink */
#define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */ #define DEF_TYPE_PR_SWAP 0x0A /* Send By: Source,Sink */
#define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */ #define DEF_TYPE_VCONN_SWAP 0x0B /* Send By: Source,Sink */
#define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */ #define DEF_TYPE_WAIT 0x0C /* Send By: Source,Sink */
#define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */ #define DEF_TYPE_SOFT_RESET 0x0D /* Send By: Source,Sink */
#define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */ #define DEF_TYPE_DATA_RESET 0x0E /* Send By: Source,Sink */
#define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */ #define DEF_TYPE_DATA_RESET_CMP 0x0F /* Send By: Source,Sink */
#define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_NOT_SUPPORT 0x10 /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */ #define DEF_TYPE_GET_SRC_CAP_EX 0x11 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */ #define DEF_TYPE_GET_STATUS 0x12 /* Send By: Source,Sink */
#define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */ #define DEF_TYPE_GET_STATUS_R 0X02 /* ext=1 */
#define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */ #define DEF_TYPE_FR_SWAP 0x13 /* Send By: Sink */
#define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */ #define DEF_TYPE_GET_PPS_STATUS 0x14 /* Send By: Sink */
#define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */ #define DEF_TYPE_GET_CTY_CODES 0x15 /* Send By: Source,Sink */
#define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */ #define DEF_TYPE_GET_SNK_CAP_EX 0x16 /* Send By: Source,DRP */
#define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */ #define DEF_TYPE_GET_SRC_INFO 0x17 /* Send By: Sink,DRP */
#define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */ #define DEF_TYPE_GET_REVISION 0x18 /* Send By: Source,Sink */
/* Data Message Types */ /* Data Message Types */
#define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */ #define DEF_TYPE_SRC_CAP 0x01 /* Send By: Source,Dual-Role Power */
#define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */ #define DEF_TYPE_REQUEST 0x02 /* Send By: Sink */
#define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */ #define DEF_TYPE_BIST 0x03 /* Send By: Tester,Source,Sink */
#define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */ #define DEF_TYPE_SNK_CAP 0x04 /* Send By: Sink,Dual-Role Power */
#define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */ #define DEF_TYPE_BAT_STATUS 0x05 /* Send By: Source,Sink */
#define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */ #define DEF_TYPE_ALERT 0x06 /* Send By: Source,Sink */
#define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */ #define DEF_TYPE_GET_CTY_INFO 0x07 /* Send By: Source,Sink */
#define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */ #define DEF_TYPE_ENTER_USB 0x08 /* Send By: DFP */
#define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */ #define DEF_TYPE_EPR_REQUEST 0x09 /* Send By: Sink */
#define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */ #define DEF_TYPE_EPR_MODE 0x0A /* Send By: Source,Sink */
#define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */ #define DEF_TYPE_SRC_INFO 0x0B /* Send By: Source */
#define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_REVISION 0x0C /* Send By: Source,Sink,Cable Plug */
#define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */ #define DEF_TYPE_VENDOR_DEFINED 0x0F /* Send By: Source,Sink,Cable Plug */
/* Vendor Define Message Command */ /* Vendor Define Message Command */
#define DEF_VDM_DISC_IDENT 0x01 #define DEF_VDM_DISC_IDENT 0x01
#define DEF_VDM_DISC_SVID 0x02 #define DEF_VDM_DISC_SVID 0x02
#define DEF_VDM_DISC_MODE 0x03 #define DEF_VDM_DISC_MODE 0x03
#define DEF_VDM_ENTER_MODE 0x04 #define DEF_VDM_ENTER_MODE 0x04
#define DEF_VDM_EXIT_MODE 0x05 #define DEF_VDM_EXIT_MODE 0x05
#define DEF_VDM_ATTENTION 0x06 #define DEF_VDM_ATTENTION 0x06
#define DEF_VDM_DP_S_UPDATE 0x10 #define DEF_VDM_DP_S_UPDATE 0x10
#define DEF_VDM_DP_CONFIG 0x11 #define DEF_VDM_DP_CONFIG 0x11
/* PD Revision */ /* PD Revision */
#define DEF_PD_REVISION_10 0x00 #define DEF_PD_REVISION_10 0x00
#define DEF_PD_REVISION_20 0x01 #define DEF_PD_REVISION_20 0x01
#define DEF_PD_REVISION_30 0x02 #define DEF_PD_REVISION_30 0x02
/* PD PHY Channel */ /* PD PHY Channel */
#define DEF_PD_CC1 0x00 #define DEF_PD_CC1 0x00
#define DEF_PD_CC2 0x01 #define DEF_PD_CC2 0x01
#define PIN_CC1 GPIO_Pin_14 #define PIN_CC1 GPIO_Pin_14
#define PIN_CC2 GPIO_Pin_15 #define PIN_CC2 GPIO_Pin_15
/* PD Tx Status */ /* PD Tx Status */
#define DEF_PD_TX_OK 0x00 #define DEF_PD_TX_OK 0x00
#define DEF_PD_TX_FAIL 0x01 #define DEF_PD_TX_FAIL 0x01
/* PDO INDEX */ /* PDO INDEX */
#define PDO_INDEX_1 1 #define PDO_INDEX_1 1
#define PDO_INDEX_2 2 #define PDO_INDEX_2 2
#define PDO_INDEX_3 3 #define PDO_INDEX_3 3
#define PDO_INDEX_4 4 #define PDO_INDEX_4 4
#define PDO_INDEX_5 5 #define PDO_INDEX_5 5
/******************************************************************************/ /******************************************************************************/
#define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */ #define UPD_TMR_TX_48M (80-1) /* timer value for USB PD BMC transmittal @Fsys=48MHz */
#define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */ #define UPD_TMR_RX_48M (120-1) /* timer value for USB PD BMC receiving @Fsys=48MHz */
#define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */ #define UPD_TMR_TX_24M (40-1) /* timer value for USB PD BMC transmittal @Fsys=24MHz */
#define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */ #define UPD_TMR_RX_24M (60-1) /* timer value for USB PD BMC receiving @Fsys=24MHz */
#define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */ #define UPD_TMR_TX_12M (20-1) /* timer value for USB PD BMC transmittal @Fsys=12MHz */
#define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */ #define UPD_TMR_RX_12M (30-1) /* timer value for USB PD BMC receiving @Fsys=12MHz */
#define MASK_PD_STAT 0x03 /* Bit mask for current PD status */ #define MASK_PD_STAT 0x03 /* Bit mask for current PD status */
#define PD_RX_SOP0 0x01 /* SOP0 received */ #define PD_RX_SOP0 0x01 /* SOP0 received */
#define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */ #define PD_RX_SOP1_HRST 0x02 /* SOP1 or Hard Reset received */
#define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */ #define PD_RX_SOP2_CRST 0x03 /* SOP2 or Cable Reset received */
#define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */ #define UPD_SOP0 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC1 | TX_SEL4_SYNC2 ) /* SOP1 */
#define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */ #define UPD_SOP1 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC1 | TX_SEL3_SYNC3 | TX_SEL4_SYNC3 ) /* SOP2 */
#define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */ #define UPD_SOP2 ( TX_SEL1_SYNC1 | TX_SEL2_SYNC3 | TX_SEL3_SYNC1 | TX_SEL4_SYNC3 ) /* SOP3 */
#define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/ #define UPD_HARD_RESET ( TX_SEL1_RST1 | TX_SEL2_RST1 | TX_SEL3_RST1 | TX_SEL4_RST2 ) /* Hard Reset*/
#define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/ #define UPD_CABLE_RESET ( TX_SEL1_RST1 | TX_SEL2_SYNC1 | TX_SEL3_RST1 | TX_SEL4_SYNC3 ) /* Cable Reset*/
#define bCC_CMP_22 0X01 #define bCC_CMP_22 0X01
#define bCC_CMP_45 0X02 #define bCC_CMP_45 0X02
#define bCC_CMP_55 0X04 #define bCC_CMP_55 0X04
#define bCC_CMP_66 0X08 #define bCC_CMP_66 0X08
#define bCC_CMP_95 0X10 #define bCC_CMP_95 0X10
#define bCC_CMP_123 0X20 #define bCC_CMP_123 0X20
#define bCC_CMP_220 0X40 #define bCC_CMP_220 0X40
/******************************************************************************/ /******************************************************************************/
/* PD State Machine */ /* PD State Machine */
typedef enum typedef enum
{ {
STA_IDLE = 0, /* 0: No task status */ STA_IDLE = 0, /* 0: No task status */
STA_DISCONNECT, /* 1: Disconnection */ STA_DISCONNECT, /* 1: Disconnection */
STA_SRC_CONNECT, /* 2: SRC connect */ STA_SRC_CONNECT, /* 2: SRC connect */
STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */ STA_RX_SRC_CAP_WAIT, /* 3: Waiting to receive SRC_CAP */
STA_RX_SRC_CAP, /* 4: SRC_CAP received */ STA_RX_SRC_CAP, /* 4: SRC_CAP received */
STA_TX_REQ, /* 5: Send REQUEST */ STA_TX_REQ, /* 5: Send REQUEST */
STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */ STA_RX_ACCEPT_WAIT, /* 6: Waiting to receive ACCEPT */
STA_RX_ACCEPT, /* 7: ACCEPT received */ STA_RX_ACCEPT, /* 7: ACCEPT received */
STA_RX_REJECT, /* 8: REJECT received */ STA_RX_REJECT, /* 8: REJECT received */
STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */ STA_RX_PS_RDY_WAIT, /* 9: Waiting to receive PS_RDY */
STA_RX_PS_RDY, /* 10: PS_RDY received */ STA_RX_PS_RDY, /* 10: PS_RDY received */
STA_SINK_CONNECT, /* 11: SNK access */ STA_SINK_CONNECT, /* 11: SNK access */
STA_TX_SRC_CAP, /* 12: Send SRC_CAP */ STA_TX_SRC_CAP, /* 12: Send SRC_CAP */
STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */ STA_RX_REQ_WAIT, /* 13: Waiting to receive REQUEST */
STA_RX_REQ, /* 14: REQUEST received */ STA_RX_REQ, /* 14: REQUEST received */
STA_TX_ACCEPT, /* 15: Send ACCEPT */ STA_TX_ACCEPT, /* 15: Send ACCEPT */
STA_TX_REJECT, /* 16: Send REJECT */ STA_TX_REJECT, /* 16: Send REJECT */
STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */ STA_ADJ_VOL, /* 17: Adjustment of output voltage and current */
STA_TX_PS_RDY, /* 18: Send PS_RDY */ STA_TX_PS_RDY, /* 18: Send PS_RDY */
STA_TX_DR_SWAP, /* 19: Send DR_SWAP */ STA_TX_DR_SWAP, /* 19: Send DR_SWAP */
STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */ STA_RX_DR_SWAP_ACCEPT, /* 20: Waiting to receive the answer ACCEPT from DR_SWAP */
STA_TX_PR_SWAP, /* 21: Send PR_SWAP */ STA_TX_PR_SWAP, /* 21: Send PR_SWAP */
STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */ STA_RX_PR_SWAP_ACCEPT, /* 22: Waiting to receive the answer ACCEPT from PR_SWAP */
STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */ STA_RX_PR_SWAP_PS_RDY, /* 23: Waiting to receive the answer PS_RDY from PR_SWAP */
STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */ STA_TX_PR_SWAP_PS_RDY, /* 24: Send answer PS_RDY for PR_SWAP */
STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */ STA_PR_SWAP_RECON_WAIT, /* 25: Wait for PR_SWAP before reconnecting */
STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */ STA_SRC_RECON_WAIT, /* 26: Waiting for SRC to reconnect */
STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */ STA_SINK_RECON_WAIT, /* 27: Waiting for SNK to reconnect */
STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */ STA_RX_APD_PS_RDY_WAIT, /* 28: Waiting for PS_RDY from the receiving adapter */
STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */ STA_RX_APD_PS_RDY, /* 29: PS_RDY received from the adapter */
STA_MODE_SWITCH, /* 30: Mode switching */ STA_MODE_SWITCH, /* 30: Mode switching */
STA_TX_SOFTRST, /* 31: Sending a software reset */ STA_TX_SOFTRST, /* 31: Sending a software reset */
STA_TX_HRST, /* 32: Send hardware reset */ STA_TX_HRST, /* 32: Send hardware reset */
STA_PHY_RST, /* 33: PHY reset */ STA_PHY_RST, /* 33: PHY reset */
STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */ STA_APD_IDLE_WAIT, /* 34: Waiting for the adapter to become idle */
} CC_STATUS; } CC_STATUS;
/******************************************************************************/ /******************************************************************************/
/* PD Message Header Struct */ /* PD Message Header Struct */
typedef union typedef union
{ {
struct _Message_Header struct _Message_Header
{ {
UINT8 MsgType: 5; /* Message Type */ UINT8 MsgType: 5; /* Message Type */
UINT8 PDRole: 1; /* 0-UFP; 1-DFP */ UINT8 PDRole: 1; /* 0-UFP; 1-DFP */
UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */ UINT8 SpecRev: 2; /* 00-Rev1.0; 01-Rev2.0; 10-Rev3.0; */
UINT8 PRRole: 1; /* 0-Sink; 1-Source */ UINT8 PRRole: 1; /* 0-Sink; 1-Source */
UINT8 MsgID: 3; UINT8 MsgID: 3;
UINT8 NumDO: 3; UINT8 NumDO: 3;
UINT8 Ext: 1; UINT8 Ext: 1;
}Message_Header; }Message_Header;
UINT16 Data; UINT16 Data;
}_Message_Header; }_Message_Header;
/******************************************************************************/ /******************************************************************************/
/* Bit definition */ /* Bit definition */
typedef union typedef union
{ {
struct _BITS_ struct _BITS_
{ {
UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */ UINT8 Msg_Recvd: 1; /* Notify the main program of the receipt of a PD packet */
UINT8 Connected: 1; /* PD Physical Layer Connected Flag */ UINT8 Connected: 1; /* PD Physical Layer Connected Flag */
UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */ UINT8 Stop_Det_Chk: 1; /* 0-Enable detection; 1-Disable disconnection detection */
UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */ UINT8 PD_Role: 1; /* 0-UFP; 1-DFP */
UINT8 PR_Role: 1; /* 0-Sink; 1-Source */ UINT8 PR_Role: 1; /* 0-Sink; 1-Source */
UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */ UINT8 Auto_Ack_PRRole: 1; /* Role used by auto-responder 0:SINK; 1:SOURCE */
UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */ UINT8 PD_Version: 1; /* PD version 0-PD2.0; 1-PD3.0 */
UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */ UINT8 VDM_Version: 1; /* VDM Version 0-1.0 1-2.0 */
UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */ UINT8 HPD_Connected: 1; /* HPD Physical Layer Connected Flag */
UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */ UINT8 HPD_Det_Chk: 1; /* 0-turn off HPD connection detection; 1-turn on HPD connection detection */
UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */ UINT8 CC_Sel_En: 1; /* 0-CC channel selection toggle enable; 1-CC channel selection toggle disable */
UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */ UINT8 CC_Sel_State: 1; /* 0-CC channel selection switches to 0; 1-CC channel selection switches to 1 */
UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */ UINT8 PD_Comm_Succ: 1; /* 0-PD communication unsuccessful; 1-PD communication successful; */
UINT8 Recv: 3; UINT8 Recv: 3;
}Bit; }Bit;
UINT16 Bit_Flag; UINT16 Bit_Flag;
}_BIT_FLAG; }_BIT_FLAG;
/* PD control-related structures */ /* PD control-related structures */
typedef struct _PD_CONTROL typedef struct _PD_CONTROL
{ {
CC_STATUS PD_State; /* PD communication status machine */ CC_STATUS PD_State; /* PD communication status machine */
CC_STATUS PD_State_Last; /* PD communication status machine (last value) */ CC_STATUS PD_State_Last; /* PD communication status machine (last value) */
UINT8 Msg_ID; /* ID of the message sent */ UINT8 Msg_ID; /* ID of the message sent */
UINT8 Det_Timer; /* PD connection status detection timing */ UINT8 Det_Timer; /* PD connection status detection timing */
UINT8 Det_Cnt; /* Number of PD connection status detections */ UINT8 Det_Cnt; /* Number of PD connection status detections */
UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */ UINT8 Det_Sel_Cnt; /* Number of SEL toggles for PD connection status detection */
UINT8 HPD_Det_Timer; /* HPD connection detection timing */ UINT8 HPD_Det_Timer; /* HPD connection detection timing */
UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */ UINT8 HPD_Det_Cnt; /* HPD pin connection status detection count */
UINT16 PD_Comm_Timer; /* PD shared timing variables */ UINT16 PD_Comm_Timer; /* PD shared timing variables */
UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */ UINT8 ReqPDO_Idx; /* Index of the requested PDO, valid values 1-7 */
UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */ UINT16 PD_BusIdle_Timer; /* Bus Idle Time Timer */
UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */ UINT8 Mode_Try_Cnt; /* Number of retries for current mode, highest bit marks mode */
UINT8 Err_Op_Cnt; /* Exception operation count */ UINT8 Err_Op_Cnt; /* Exception operation count */
UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */ UINT8 Adapter_Idle_Cnt; /* Adapter communication idle timing */
_BIT_FLAG Flag; /* Flag byte bit definition */ _BIT_FLAG Flag; /* Flag byte bit definition */
}PD_CONTROL, *pPD_CONTROL; }PD_CONTROL, *pPD_CONTROL;
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/inc/ch32x035_wwdg.h
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@ -1,41 +1,41 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_wwdg.h * File Name : ch32x035_wwdg.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file contains all the functions prototypes for the WWDG * Description : This file contains all the functions prototypes for the WWDG
* firmware library. * firmware library.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_WWDG_H #ifndef __CH32X035_WWDG_H
#define __CH32X035_WWDG_H #define __CH32X035_WWDG_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "ch32x035.h" #include "ch32x035.h"
/* WWDG_Prescaler */ /* WWDG_Prescaler */
#define WWDG_Prescaler_1 ((uint32_t)0x00000000) #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
#define WWDG_Prescaler_2 ((uint32_t)0x00000080) #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
#define WWDG_Prescaler_4 ((uint32_t)0x00000100) #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
#define WWDG_Prescaler_8 ((uint32_t)0x00000180) #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
void WWDG_DeInit(void); void WWDG_DeInit(void);
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
void WWDG_SetWindowValue(uint8_t WindowValue); void WWDG_SetWindowValue(uint8_t WindowValue);
void WWDG_EnableIT(void); void WWDG_EnableIT(void);
void WWDG_SetCounter(uint8_t Counter); void WWDG_SetCounter(uint8_t Counter);
void WWDG_Enable(uint8_t Counter); void WWDG_Enable(uint8_t Counter);
FlagStatus WWDG_GetFlagStatus(void); FlagStatus WWDG_GetFlagStatus(void);
void WWDG_ClearFlag(void); void WWDG_ClearFlag(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif

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Peripheral/src/ch32x035_adc.c
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184
Peripheral/src/ch32x035_awu.c
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@ -1,92 +1,92 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_awu.c * File Name : ch32x035_awu.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the AWU firmware functions. * Description : This file provides all the AWU firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_awu.h" #include "ch32x035_awu.h"
/* PSC registers bit mask */ /* PSC registers bit mask */
#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0) #define AWUPSC_MASK ((uint32_t)0xFFFFFFF0)
/* WR register bit mask */ /* WR register bit mask */
#define AWUWR_MASK ((uint32_t)0xFFFFFFC0) #define AWUWR_MASK ((uint32_t)0xFFFFFFC0)
/********************************************************************* /*********************************************************************
* @fn AutoWakeUpCmd * @fn AutoWakeUpCmd
* *
* @brief Enables or disables the Auto WakeUp functionality. * @brief Enables or disables the Auto WakeUp functionality.
* *
* @param NewState - new state of the Auto WakeUp functionality * @param NewState - new state of the Auto WakeUp functionality
* (ENABLE or DISABLE). * (ENABLE or DISABLE).
* *
* @return none * @return none
*/ */
void AutoWakeUpCmd(FunctionalState NewState) void AutoWakeUpCmd(FunctionalState NewState)
{ {
if(NewState) if(NewState)
{ {
AWU->CSR |= (1 << 1); AWU->CSR |= (1 << 1);
} }
else else
{ {
AWU->CSR &= ~(1 << 1); AWU->CSR &= ~(1 << 1);
} }
} }
/********************************************************************* /*********************************************************************
* @fn AWU_SetPrescaler * @fn AWU_SetPrescaler
* *
* @brief Sets the Auto Wake up Prescaler * @brief Sets the Auto Wake up Prescaler
* *
* @param AWU_Prescaler - specifies the Auto Wake up Prescaler * @param AWU_Prescaler - specifies the Auto Wake up Prescaler
* AWU_Prescaler_1 - AWU counter clock = LSI/1 * AWU_Prescaler_1 - AWU counter clock = LSI/1
* AWU_Prescaler_2 - AWU counter clock = LSI/2 * AWU_Prescaler_2 - AWU counter clock = LSI/2
* AWU_Prescaler_4 - AWU counter clock = LSI/4 * AWU_Prescaler_4 - AWU counter clock = LSI/4
* AWU_Prescaler_8 - AWU counter clock = LSI/8 * AWU_Prescaler_8 - AWU counter clock = LSI/8
* AWU_Prescaler_16 - AWU counter clock = LSI/16 * AWU_Prescaler_16 - AWU counter clock = LSI/16
* AWU_Prescaler_32 - AWU counter clock = LSI/32 * AWU_Prescaler_32 - AWU counter clock = LSI/32
* AWU_Prescaler_64 - AWU counter clock = LSI/64 * AWU_Prescaler_64 - AWU counter clock = LSI/64
* AWU_Prescaler_128 - AWU counter clock = LSI/128 * AWU_Prescaler_128 - AWU counter clock = LSI/128
* AWU_Prescaler_256 - AWU counter clock = LSI/256 * AWU_Prescaler_256 - AWU counter clock = LSI/256
* AWU_Prescaler_512 - AWU counter clock = LSI/512 * AWU_Prescaler_512 - AWU counter clock = LSI/512
* AWU_Prescaler_1024 - AWU counter clock = LSI/1024 * AWU_Prescaler_1024 - AWU counter clock = LSI/1024
* AWU_Prescaler_2048 - AWU counter clock = LSI/2048 * AWU_Prescaler_2048 - AWU counter clock = LSI/2048
* AWU_Prescaler_4096 - AWU counter clock = LSI/4096 * AWU_Prescaler_4096 - AWU counter clock = LSI/4096
* AWU_Prescaler_10240 - AWU counter clock = LSI/10240 * AWU_Prescaler_10240 - AWU counter clock = LSI/10240
* AWU_Prescaler_61440 - AWU counter clock = LSI/61440 * AWU_Prescaler_61440 - AWU counter clock = LSI/61440
* *
* @return none * @return none
*/ */
void AWU_SetPrescaler(uint32_t AWU_Prescaler) void AWU_SetPrescaler(uint32_t AWU_Prescaler)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = AWU->PSC & AWUPSC_MASK; tmpreg = AWU->PSC & AWUPSC_MASK;
tmpreg |= AWU_Prescaler; tmpreg |= AWU_Prescaler;
AWU->PSC = tmpreg; AWU->PSC = tmpreg;
} }
/********************************************************************* /*********************************************************************
* @fn AWU_SetWindowValue * @fn AWU_SetWindowValue
* *
* @brief Sets the WWDG window value * @brief Sets the WWDG window value
* *
* @param WindowValue - specifies the window value to be compared to the * @param WindowValue - specifies the window value to be compared to the
* downcounter,which must be lower than 0x3F * downcounter,which must be lower than 0x3F
* *
* @return none * @return none
*/ */
void AWU_SetWindowValue(uint8_t WindowValue) void AWU_SetWindowValue(uint8_t WindowValue)
{ {
__IO uint32_t tmpreg = 0; __IO uint32_t tmpreg = 0;
tmpreg = AWU->WR & AWUWR_MASK; tmpreg = AWU->WR & AWUWR_MASK;
tmpreg |= WindowValue; tmpreg |= WindowValue;
AWU->WR = tmpreg; AWU->WR = tmpreg;
} }

240
Peripheral/src/ch32x035_dbgmcu.c
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/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_dbgmcu.c * File Name : ch32x035_dbgmcu.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the DBGMCU firmware functions. * Description : This file provides all the DBGMCU firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_dbgmcu.h" #include "ch32x035_dbgmcu.h"
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
/********************************************************************* /*********************************************************************
* @fn DBGMCU_GetREVID * @fn DBGMCU_GetREVID
* *
* @brief Returns the device revision identifier. * @brief Returns the device revision identifier.
* *
* @return Revision identifier. * @return Revision identifier.
*/ */
uint32_t DBGMCU_GetREVID(void) uint32_t DBGMCU_GetREVID(void)
{ {
return ((*(uint32_t *)0x1FFFF704) >> 16); return ((*(uint32_t *)0x1FFFF704) >> 16);
} }
/********************************************************************* /*********************************************************************
* @fn DBGMCU_GetDEVID * @fn DBGMCU_GetDEVID
* *
* @brief Returns the device identifier. * @brief Returns the device identifier.
* *
* @return Device identifier. * @return Device identifier.
*/ */
uint32_t DBGMCU_GetDEVID(void) uint32_t DBGMCU_GetDEVID(void)
{ {
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
} }
/********************************************************************* /*********************************************************************
* @fn __get_DEBUG_CR * @fn __get_DEBUG_CR
* *
* @brief Return the DEBUGE Control Register * @brief Return the DEBUGE Control Register
* *
* @return DEBUGE Control value * @return DEBUGE Control value
*/ */
uint32_t __get_DEBUG_CR(void) uint32_t __get_DEBUG_CR(void)
{ {
uint32_t result; uint32_t result;
__asm volatile("csrr %0,""0x7C0" : "=r"(result)); __asm volatile("csrr %0,""0x7C0" : "=r"(result));
return (result); return (result);
} }
/********************************************************************* /*********************************************************************
* @fn __set_DEBUG_CR * @fn __set_DEBUG_CR
* *
* @brief Set the DEBUGE Control Register * @brief Set the DEBUGE Control Register
* *
* @param value - set DEBUGE Control value * @param value - set DEBUGE Control value
* *
* @return none * @return none
*/ */
void __set_DEBUG_CR(uint32_t value) void __set_DEBUG_CR(uint32_t value)
{ {
__asm volatile("csrw 0x7C0, %0" : : "r"(value)); __asm volatile("csrw 0x7C0, %0" : : "r"(value));
} }
/********************************************************************* /*********************************************************************
* @fn DBGMCU_Config * @fn DBGMCU_Config
* *
* @brief Configures the specified peripheral and low power mode behavior * @brief Configures the specified peripheral and low power mode behavior
* when the MCU under Debug mode. * when the MCU under Debug mode.
* *
* @param DBGMCU_Periph - specifies the peripheral and low power mode. * @param DBGMCU_Periph - specifies the peripheral and low power mode.
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
* DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted * DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted
* NewState - ENABLE or DISABLE. * NewState - ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
{ {
uint32_t val; uint32_t val;
if(NewState != DISABLE) if(NewState != DISABLE)
{ {
__set_DEBUG_CR(DBGMCU_Periph); __set_DEBUG_CR(DBGMCU_Periph);
} }
else else
{ {
val = __get_DEBUG_CR(); val = __get_DEBUG_CR();
val &= ~(uint32_t)DBGMCU_Periph; val &= ~(uint32_t)DBGMCU_Periph;
__set_DEBUG_CR(val); __set_DEBUG_CR(val);
} }
} }
/********************************************************************* /*********************************************************************
* @fn DBGMCU_GetCHIPID * @fn DBGMCU_GetCHIPID
* *
* @brief Returns the CHIP identifier. * @brief Returns the CHIP identifier.
* *
* @return Device identifier. * @return Device identifier.
* ChipID List- * ChipID List-
* CH32X035R8T6-0x035006x1 * CH32X035R8T6-0x035006x1
* CH32X035C8T6-0x035106x1 * CH32X035C8T6-0x035106x1
* CH32X035F8U6-0x035E06x1 * CH32X035F8U6-0x035E06x1
* CH32X035G8U6-0x035606x1 * CH32X035G8U6-0x035606x1
* CH32X035G8R6-0x035B06x1 * CH32X035G8R6-0x035B06x1
* CH32X035F7P6-0x035706x1 * CH32X035F7P6-0x035706x1
* CH32X033F8P6-0x035A06x1 * CH32X033F8P6-0x035A06x1
*/ */
uint32_t DBGMCU_GetCHIPID( void ) uint32_t DBGMCU_GetCHIPID( void )
{ {
return( *( uint32_t * )0x1FFFF704 ); return( *( uint32_t * )0x1FFFF704 );
} }

864
Peripheral/src/ch32x035_dma.c
View file

@ -1,432 +1,432 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_dma.c * File Name : ch32x035_dma.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the DMA firmware functions. * Description : This file provides all the DMA firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_dma.h" #include "ch32x035_dma.h"
#include "ch32x035_rcc.h" #include "ch32x035_rcc.h"
/* DMA1 Channelx interrupt pending bit masks */ /* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) #define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) #define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) #define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) #define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) #define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) #define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) #define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) #define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
/* DMA2 FLAG mask */ /* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000000) #define FLAG_Mask ((uint32_t)0x10000000)
/* DMA registers Masks */ /* DMA registers Masks */
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) #define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/********************************************************************* /*********************************************************************
* @fn DMA_DeInit * @fn DMA_DeInit
* *
* @brief Deinitializes the DMAy Channelx registers to their default * @brief Deinitializes the DMAy Channelx registers to their default
* reset values. * reset values.
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA1 to select the DMA Channel. * 1 to 8 for DMA1 to select the DMA Channel.
* *
* @return none * @return none
*/ */
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
{ {
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
DMAy_Channelx->CFGR = 0; DMAy_Channelx->CFGR = 0;
DMAy_Channelx->CNTR = 0; DMAy_Channelx->CNTR = 0;
DMAy_Channelx->PADDR = 0; DMAy_Channelx->PADDR = 0;
DMAy_Channelx->MADDR = 0; DMAy_Channelx->MADDR = 0;
if(DMAy_Channelx == DMA1_Channel1) if(DMAy_Channelx == DMA1_Channel1)
{ {
DMA1->INTFCR |= DMA1_Channel1_IT_Mask; DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
} }
else if(DMAy_Channelx == DMA1_Channel2) else if(DMAy_Channelx == DMA1_Channel2)
{ {
DMA1->INTFCR |= DMA1_Channel2_IT_Mask; DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
} }
else if(DMAy_Channelx == DMA1_Channel3) else if(DMAy_Channelx == DMA1_Channel3)
{ {
DMA1->INTFCR |= DMA1_Channel3_IT_Mask; DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
} }
else if(DMAy_Channelx == DMA1_Channel4) else if(DMAy_Channelx == DMA1_Channel4)
{ {
DMA1->INTFCR |= DMA1_Channel4_IT_Mask; DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
} }
else if(DMAy_Channelx == DMA1_Channel5) else if(DMAy_Channelx == DMA1_Channel5)
{ {
DMA1->INTFCR |= DMA1_Channel5_IT_Mask; DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
} }
else if(DMAy_Channelx == DMA1_Channel6) else if(DMAy_Channelx == DMA1_Channel6)
{ {
DMA1->INTFCR |= DMA1_Channel6_IT_Mask; DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
} }
else if(DMAy_Channelx == DMA1_Channel7) else if(DMAy_Channelx == DMA1_Channel7)
{ {
DMA1->INTFCR |= DMA1_Channel7_IT_Mask; DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
} }
else if(DMAy_Channelx == DMA1_Channel8) else if(DMAy_Channelx == DMA1_Channel8)
{ {
DMA1->INTFCR |= DMA1_Channel8_IT_Mask; DMA1->INTFCR |= DMA1_Channel8_IT_Mask;
} }
} }
/********************************************************************* /*********************************************************************
* @fn DMA_Init * @fn DMA_Init
* *
* @brief Initializes the DMAy Channelx according to the specified * @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct. * parameters in the DMA_InitStruct.
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA1 to select the DMA Channel. * 1 to 8 for DMA1 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel. * contains the configuration information for the specified DMA Channel.
* *
* @return none * @return none
*/ */
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = DMAy_Channelx->CFGR; tmpreg = DMAy_Channelx->CFGR;
tmpreg &= CFGR_CLEAR_Mask; tmpreg &= CFGR_CLEAR_Mask;
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
DMAy_Channelx->CFGR = tmpreg; DMAy_Channelx->CFGR = tmpreg;
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
} }
/********************************************************************* /*********************************************************************
* @fn DMA_StructInit * @fn DMA_StructInit
* *
* @brief Fills each DMA_InitStruct member with its default value. * @brief Fills each DMA_InitStruct member with its default value.
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA1 to select the DMA Channel. * 1 to 8 for DMA1 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel. * contains the configuration information for the specified DMA Channel.
* *
* @return none * @return none
*/ */
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
{ {
DMA_InitStruct->DMA_PeripheralBaseAddr = 0; DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
DMA_InitStruct->DMA_MemoryBaseAddr = 0; DMA_InitStruct->DMA_MemoryBaseAddr = 0;
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStruct->DMA_BufferSize = 0; DMA_InitStruct->DMA_BufferSize = 0;
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
DMA_InitStruct->DMA_Priority = DMA_Priority_Low; DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
} }
/********************************************************************* /*********************************************************************
* @fn DMA_Cmd * @fn DMA_Cmd
* *
* @brief Enables or disables the specified DMAy Channelx. * @brief Enables or disables the specified DMAy Channelx.
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA1 to select the DMA Channel. * 1 to 8 for DMA1 to select the DMA Channel.
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE). * NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
* *
* @return none * @return none
*/ */
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
{ {
if(NewState != DISABLE) if(NewState != DISABLE)
{ {
DMAy_Channelx->CFGR |= DMA_CFGR1_EN; DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
} }
else else
{ {
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
} }
} }
/********************************************************************* /*********************************************************************
* @fn DMA_ITConfig * @fn DMA_ITConfig
* *
* @brief Enables or disables the specified DMAy Channelx interrupts. * @brief Enables or disables the specified DMAy Channelx interrupts.
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA1 to select the DMA Channel. * 1 to 8 for DMA1 to select the DMA Channel.
* DMA_IT - specifies the DMA interrupts sources to be enabled * DMA_IT - specifies the DMA interrupts sources to be enabled
* or disabled. * or disabled.
* DMA_IT_TC - Transfer complete interrupt mask * DMA_IT_TC - Transfer complete interrupt mask
* DMA_IT_HT - Half transfer interrupt mask * DMA_IT_HT - Half transfer interrupt mask
* DMA_IT_TE - Transfer error interrupt mask * DMA_IT_TE - Transfer error interrupt mask
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE). * NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
* *
* @return none * @return none
*/ */
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{ {
if(NewState != DISABLE) if(NewState != DISABLE)
{ {
DMAy_Channelx->CFGR |= DMA_IT; DMAy_Channelx->CFGR |= DMA_IT;
} }
else else
{ {
DMAy_Channelx->CFGR &= ~DMA_IT; DMAy_Channelx->CFGR &= ~DMA_IT;
} }
} }
/********************************************************************* /*********************************************************************
* @fn DMA_SetCurrDataCounter * @fn DMA_SetCurrDataCounter
* *
* @brief Sets the number of data units in the current DMAy Channelx transfer. * @brief Sets the number of data units in the current DMAy Channelx transfer.
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA1 to select the DMA Channel. * 1 to 8 for DMA1 to select the DMA Channel.
* DataNumber - The number of data units in the current DMAy Channelx * DataNumber - The number of data units in the current DMAy Channelx
* transfer. * transfer.
* *
* @return none * @return none
*/ */
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
{ {
DMAy_Channelx->CNTR = DataNumber; DMAy_Channelx->CNTR = DataNumber;
} }
/********************************************************************* /*********************************************************************
* @fn DMA_GetCurrDataCounter * @fn DMA_GetCurrDataCounter
* *
* @brief Returns the number of remaining data units in the current * @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer. * DMAy Channelx transfer.
* *
* @param DMAy_Channelx - here y can be 1 to select the DMA and x can be * @param DMAy_Channelx - here y can be 1 to select the DMA and x can be
* 1 to 8 for DMA1 to select the DMA Channel. * 1 to 8 for DMA1 to select the DMA Channel.
* *
* @return DataNumber - The number of remaining data units in the current * @return DataNumber - The number of remaining data units in the current
* DMAy Channelx transfer. * DMAy Channelx transfer.
*/ */
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
{ {
return ((uint16_t)(DMAy_Channelx->CNTR)); return ((uint16_t)(DMAy_Channelx->CNTR));
} }
/********************************************************************* /*********************************************************************
* @fn DMA_GetFlagStatus * @fn DMA_GetFlagStatus
* *
* @brief Checks whether the specified DMAy Channelx flag is set or not. * @brief Checks whether the specified DMAy Channelx flag is set or not.
* *
* @param DMAy_FLAG - specifies the flag to check. * @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag. * DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag. * DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag. * DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag. * DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag. * DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag. * DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag. * DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA1_FLAG_GL8 - DMA1 Channel8 global flag. * DMA1_FLAG_GL8 - DMA1 Channel8 global flag.
* DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag.
* @return The new state of DMAy_FLAG (SET or RESET). * @return The new state of DMAy_FLAG (SET or RESET).
*/ */
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{ {
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = DMA1->INTFR; tmpreg = DMA1->INTFR;
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/********************************************************************* /*********************************************************************
* @fn DMA_ClearFlag * @fn DMA_ClearFlag
* *
* @brief Clears the DMAy Channelx's pending flags. * @brief Clears the DMAy Channelx's pending flags.
* *
* @param DMAy_FLAG - specifies the flag to check. * @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag. * DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag. * DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag. * DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag. * DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag. * DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag. * DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag. * DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA1_FLAG_GL8 - DMA1 Channel8 global flag. * DMA1_FLAG_GL8 - DMA1 Channel8 global flag.
* DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag. * DMA1_FLAG_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag. * DMA1_FLAG_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag. * DMA1_FLAG_TE8 - DMA1 Channel8 transfer error flag.
* @return none * @return none
*/ */
void DMA_ClearFlag(uint32_t DMAy_FLAG) void DMA_ClearFlag(uint32_t DMAy_FLAG)
{ {
DMA1->INTFCR = DMAy_FLAG; DMA1->INTFCR = DMAy_FLAG;
} }
/********************************************************************* /*********************************************************************
* @fn DMA_GetITStatus * @fn DMA_GetITStatus
* *
* @brief Checks whether the specified DMAy Channelx interrupt has * @brief Checks whether the specified DMAy Channelx interrupt has
* occurred or not. * occurred or not.
* *
* @param DMAy_IT - specifies the DMAy interrupt source to check. * @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag. * DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag. * DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag. * DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag. * DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag. * DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag. * DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag. * DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA1_IT_GL8 - DMA1 Channel8 global flag. * DMA1_IT_GL8 - DMA1 Channel8 global flag.
* DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag.
* @return The new state of DMAy_IT (SET or RESET). * @return The new state of DMAy_IT (SET or RESET).
*/ */
ITStatus DMA_GetITStatus(uint32_t DMAy_IT) ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{ {
ITStatus bitstatus = RESET; ITStatus bitstatus = RESET;
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = DMA1->INTFR; tmpreg = DMA1->INTFR;
if((tmpreg & DMAy_IT) != (uint32_t)RESET) if((tmpreg & DMAy_IT) != (uint32_t)RESET)
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/********************************************************************* /*********************************************************************
* @fn DMA_ClearITPendingBit * @fn DMA_ClearITPendingBit
* *
* @brief Clears the DMAy Channelx's interrupt pending bits. * @brief Clears the DMAy Channelx's interrupt pending bits.
* *
* @param DMAy_IT - specifies the DMAy interrupt source to check. * @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag. * DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag. * DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag. * DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag. * DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag. * DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag. * DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag. * DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA1_IT_GL8 - DMA1 Channel8 global flag. * DMA1_IT_GL8 - DMA1 Channel8 global flag.
* DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag. * DMA1_IT_TC8 - DMA1 Channel8 transfer complete flag.
* DMA1_IT_HT8 - DMA1 Channel8 half transfer flag. * DMA1_IT_HT8 - DMA1 Channel8 half transfer flag.
* DMA1_IT_TE8 - DMA1 Channel8 transfer error flag. * DMA1_IT_TE8 - DMA1 Channel8 transfer error flag.
* @return none * @return none
*/ */
void DMA_ClearITPendingBit(uint32_t DMAy_IT) void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{ {
DMA1->INTFCR = DMAy_IT; DMA1->INTFCR = DMAy_IT;
} }

364
Peripheral/src/ch32x035_exti.c
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@ -1,182 +1,182 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_exti.c * File Name : ch32x035_exti.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the EXTI firmware functions. * Description : This file provides all the EXTI firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_exti.h" #include "ch32x035_exti.h"
/* No interrupt selected */ /* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000) #define EXTI_LINENONE ((uint32_t)0x00000)
/********************************************************************* /*********************************************************************
* @fn EXTI_DeInit * @fn EXTI_DeInit
* *
* @brief Deinitializes the EXTI peripheral registers to their default * @brief Deinitializes the EXTI peripheral registers to their default
* reset values. * reset values.
* *
* @return none. * @return none.
*/ */
void EXTI_DeInit(void) void EXTI_DeInit(void)
{ {
EXTI->INTENR = 0x00000000; EXTI->INTENR = 0x00000000;
EXTI->EVENR = 0x00000000; EXTI->EVENR = 0x00000000;
EXTI->RTENR = 0x00000000; EXTI->RTENR = 0x00000000;
EXTI->FTENR = 0x00000000; EXTI->FTENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF; EXTI->INTFR = 0x000FFFFF;
} }
/********************************************************************* /*********************************************************************
* @fn EXTI_Init * @fn EXTI_Init
* *
* @brief Initializes the EXTI peripheral according to the specified * @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct. * parameters in the EXTI_InitStruct.
* *
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* *
* @return none. * @return none.
*/ */
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
{ {
uint32_t tmp = 0; uint32_t tmp = 0;
tmp = (uint32_t)EXTI_BASE; tmp = (uint32_t)EXTI_BASE;
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{ {
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode; tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{ {
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
} }
else else
{ {
tmp = (uint32_t)EXTI_BASE; tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger; tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
} }
} }
else else
{ {
tmp += EXTI_InitStruct->EXTI_Mode; tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
} }
} }
/********************************************************************* /*********************************************************************
* @fn EXTI_StructInit * @fn EXTI_StructInit
* *
* @brief Fills each EXTI_InitStruct member with its reset value. * @brief Fills each EXTI_InitStruct member with its reset value.
* *
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
* *
* @return none. * @return none.
*/ */
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
{ {
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE; EXTI_InitStruct->EXTI_LineCmd = DISABLE;
} }
/********************************************************************* /*********************************************************************
* @fn EXTI_GenerateSWInterrupt * @fn EXTI_GenerateSWInterrupt
* *
* @brief Generates a Software interrupt. * @brief Generates a Software interrupt.
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
* *
* @return none. * @return none.
*/ */
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{ {
EXTI->SWIEVR |= EXTI_Line; EXTI->SWIEVR |= EXTI_Line;
} }
/********************************************************************* /*********************************************************************
* @fn EXTI_GetFlagStatus * @fn EXTI_GetFlagStatus
* *
* @brief Checks whether the specified EXTI line flag is set or not. * @brief Checks whether the specified EXTI line flag is set or not.
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
* *
* @return The new state of EXTI_Line (SET or RESET). * @return The new state of EXTI_Line (SET or RESET).
*/ */
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{ {
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/********************************************************************* /*********************************************************************
* @fn EXTI_ClearFlag * @fn EXTI_ClearFlag
* *
* @brief Clears the EXTI's line pending flags. * @brief Clears the EXTI's line pending flags.
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
* *
* @return None * @return None
*/ */
void EXTI_ClearFlag(uint32_t EXTI_Line) void EXTI_ClearFlag(uint32_t EXTI_Line)
{ {
EXTI->INTFR = EXTI_Line; EXTI->INTFR = EXTI_Line;
} }
/********************************************************************* /*********************************************************************
* @fn EXTI_GetITStatus * @fn EXTI_GetITStatus
* *
* @brief Checks whether the specified EXTI line is asserted or not. * @brief Checks whether the specified EXTI line is asserted or not.
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
* *
* @return The new state of EXTI_Line (SET or RESET). * @return The new state of EXTI_Line (SET or RESET).
*/ */
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{ {
ITStatus bitstatus = RESET; ITStatus bitstatus = RESET;
uint32_t enablestatus = 0; uint32_t enablestatus = 0;
enablestatus = EXTI->INTENR & EXTI_Line; enablestatus = EXTI->INTENR & EXTI_Line;
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/********************************************************************* /*********************************************************************
* @fn EXTI_ClearITPendingBit * @fn EXTI_ClearITPendingBit
* *
* @brief Clears the EXTI's line pending bits. * @brief Clears the EXTI's line pending bits.
* *
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
* *
* @return none * @return none
*/ */
void EXTI_ClearITPendingBit(uint32_t EXTI_Line) void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{ {
EXTI->INTFR = EXTI_Line; EXTI->INTFR = EXTI_Line;
} }

2080
Peripheral/src/ch32x035_flash.c
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1474
Peripheral/src/ch32x035_gpio.c
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1934
Peripheral/src/ch32x035_i2c.c
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244
Peripheral/src/ch32x035_iwdg.c
View file

@ -1,122 +1,122 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_iwdg.c * File Name : ch32x035_iwdg.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the IWDG firmware functions. * Description : This file provides all the IWDG firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_iwdg.h" #include "ch32x035_iwdg.h"
/* CTLR register bit mask */ /* CTLR register bit mask */
#define CTLR_KEY_Reload ((uint16_t)0xAAAA) #define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC) #define CTLR_KEY_Enable ((uint16_t)0xCCCC)
/********************************************************************* /*********************************************************************
* @fn IWDG_WriteAccessCmd * @fn IWDG_WriteAccessCmd
* *
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
* *
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
* IWDG_RLDR registers. * IWDG_RLDR registers.
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
* IWDG_RLDR registers. * IWDG_RLDR registers.
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
* and IWDG_RLDR registers. * and IWDG_RLDR registers.
* *
* @return none * @return none
*/ */
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{ {
IWDG->CTLR = IWDG_WriteAccess; IWDG->CTLR = IWDG_WriteAccess;
} }
/********************************************************************* /*********************************************************************
* @fn IWDG_SetPrescaler * @fn IWDG_SetPrescaler
* *
* @brief Sets IWDG Prescaler value. * @brief Sets IWDG Prescaler value.
* *
* @param IWDG_Prescaler - specifies the IWDG Prescaler value. * @param IWDG_Prescaler - specifies the IWDG Prescaler value.
* IWDG_Prescaler_4 - IWDG prescaler set to 4. * IWDG_Prescaler_4 - IWDG prescaler set to 4.
* IWDG_Prescaler_8 - IWDG prescaler set to 8. * IWDG_Prescaler_8 - IWDG prescaler set to 8.
* IWDG_Prescaler_16 - IWDG prescaler set to 16. * IWDG_Prescaler_16 - IWDG prescaler set to 16.
* IWDG_Prescaler_32 - IWDG prescaler set to 32. * IWDG_Prescaler_32 - IWDG prescaler set to 32.
* IWDG_Prescaler_64 - IWDG prescaler set to 64. * IWDG_Prescaler_64 - IWDG prescaler set to 64.
* IWDG_Prescaler_128 - IWDG prescaler set to 128. * IWDG_Prescaler_128 - IWDG prescaler set to 128.
* IWDG_Prescaler_256 - IWDG prescaler set to 256. * IWDG_Prescaler_256 - IWDG prescaler set to 256.
* *
* @return none * @return none
*/ */
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{ {
IWDG->PSCR = IWDG_Prescaler; IWDG->PSCR = IWDG_Prescaler;
} }
/********************************************************************* /*********************************************************************
* @fn IWDG_SetReload * @fn IWDG_SetReload
* *
* @brief Sets IWDG Reload value. * @brief Sets IWDG Reload value.
* *
* @param Reload - specifies the IWDG Reload value. * @param Reload - specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF. * This parameter must be a number between 0 and 0x0FFF.
* *
* @return none * @return none
*/ */
void IWDG_SetReload(uint16_t Reload) void IWDG_SetReload(uint16_t Reload)
{ {
IWDG->RLDR = Reload; IWDG->RLDR = Reload;
} }
/********************************************************************* /*********************************************************************
* @fn IWDG_ReloadCounter * @fn IWDG_ReloadCounter
* *
* @brief Reloads IWDG counter with value defined in the reload register. * @brief Reloads IWDG counter with value defined in the reload register.
* *
* @return none * @return none
*/ */
void IWDG_ReloadCounter(void) void IWDG_ReloadCounter(void)
{ {
IWDG->CTLR = CTLR_KEY_Reload; IWDG->CTLR = CTLR_KEY_Reload;
} }
/********************************************************************* /*********************************************************************
* @fn IWDG_Enable * @fn IWDG_Enable
* *
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
* *
* @return none * @return none
*/ */
void IWDG_Enable(void) void IWDG_Enable(void)
{ {
IWDG->CTLR = CTLR_KEY_Enable; IWDG->CTLR = CTLR_KEY_Enable;
} }
/********************************************************************* /*********************************************************************
* @fn IWDG_GetFlagStatus * @fn IWDG_GetFlagStatus
* *
* @brief Checks whether the specified IWDG flag is set or not. * @brief Checks whether the specified IWDG flag is set or not.
* *
* @param IWDG_FLAG - specifies the flag to check. * @param IWDG_FLAG - specifies the flag to check.
* IWDG_FLAG_PVU - Prescaler Value Update on going. * IWDG_FLAG_PVU - Prescaler Value Update on going.
* IWDG_FLAG_RVU - Reload Value Update on going. * IWDG_FLAG_RVU - Reload Value Update on going.
* *
* @return none * @return none
*/ */
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{ {
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }

218
Peripheral/src/ch32x035_misc.c
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@ -1,109 +1,109 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_misc.c * File Name : ch32x035_misc.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the miscellaneous firmware functions . * Description : This file provides all the miscellaneous firmware functions .
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_misc.h" #include "ch32x035_misc.h"
__IO uint32_t NVIC_Priority_Group = 0; __IO uint32_t NVIC_Priority_Group = 0;
/********************************************************************* /*********************************************************************
* @fn NVIC_PriorityGroupConfig * @fn NVIC_PriorityGroupConfig
* *
* @brief Configures the priority grouping - pre-emption priority and subpriority. * @brief Configures the priority grouping - pre-emption priority and subpriority.
* *
* @param NVIC_PriorityGroup - specifies the priority grouping bits length. * @param NVIC_PriorityGroup - specifies the priority grouping bits length.
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
* 4 bits for subpriority * 4 bits for subpriority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 3 bits for subpriority * 3 bits for subpriority
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
* 2 bits for subpriority * 2 bits for subpriority
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
* 1 bits for subpriority * 1 bits for subpriority
* NVIC_PriorityGroup_4 - 4 bits for pre-emption priority * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
* 0 bits for subpriority * 0 bits for subpriority
* *
* @return none * @return none
*/ */
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{ {
NVIC_Priority_Group = NVIC_PriorityGroup; NVIC_Priority_Group = NVIC_PriorityGroup;
} }
/********************************************************************* /*********************************************************************
* @fn NVIC_Init * @fn NVIC_Init
* *
* @brief Initializes the NVIC peripheral according to the specified parameters in * @brief Initializes the NVIC peripheral according to the specified parameters in
* the NVIC_InitStruct. * the NVIC_InitStruct.
* *
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
* configuration information for the specified NVIC peripheral. * configuration information for the specified NVIC peripheral.
* *
* @return none * @return none
*/ */
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
{ {
uint8_t tmppre = 0; uint8_t tmppre = 0;
if(NVIC_Priority_Group == NVIC_PriorityGroup_0) if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
{ {
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
} }
else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
{ {
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
{ {
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
} }
else else
{ {
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
} }
} }
else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
{ {
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
{ {
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
} }
else else
{ {
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
} }
} }
else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
{ {
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
{ {
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
} }
else else
{ {
tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
} }
} }
else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
{ {
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
} }
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{ {
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
} }
else else
{ {
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
} }
} }

640
Peripheral/src/ch32x035_opa.c
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@ -1,320 +1,320 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_opa.c * File Name : ch32x035_opa.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the OPA firmware functions. * Description : This file provides all the OPA firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_opa.h" #include "ch32x035_opa.h"
/* FLASH Keys */ /* FLASH Keys */
#define OPA_KEY1 ((uint32_t)0x45670123) #define OPA_KEY1 ((uint32_t)0x45670123)
#define OPA_KEY2 ((uint32_t)0xCDEF89AB) #define OPA_KEY2 ((uint32_t)0xCDEF89AB)
volatile uint32_t CTLR2_tmp = 0; volatile uint32_t CTLR2_tmp = 0;
/******************************************************************************** /********************************************************************************
* @fn OPA_Unlock * @fn OPA_Unlock
* *
* @brief Unlocks the OPA Controller. * @brief Unlocks the OPA Controller.
* *
* @return None * @return None
*/ */
void OPA_Unlock(void) void OPA_Unlock(void)
{ {
OPA->OPAKEY = OPA_KEY1; OPA->OPAKEY = OPA_KEY1;
OPA->OPAKEY = OPA_KEY2; OPA->OPAKEY = OPA_KEY2;
} }
/******************************************************************************** /********************************************************************************
* @fn OPA_Lock * @fn OPA_Lock
* *
* @brief Locks the OPA Controller. * @brief Locks the OPA Controller.
* *
* @return None * @return None
*/ */
void OPA_Lock(void) void OPA_Lock(void)
{ {
OPA->CTLR1 |= (1<<31); OPA->CTLR1 |= (1<<31);
} }
/******************************************************************************** /********************************************************************************
* @fn OPA_POLL_Unlock * @fn OPA_POLL_Unlock
* *
* @brief Unlocks the OPA POLL Controller. * @brief Unlocks the OPA POLL Controller.
* *
* @return None * @return None
*/ */
void OPA_POLL_Unlock(void) void OPA_POLL_Unlock(void)
{ {
OPA->POLLKEY = OPA_KEY1; OPA->POLLKEY = OPA_KEY1;
OPA->POLLKEY = OPA_KEY2; OPA->POLLKEY = OPA_KEY2;
} }
/******************************************************************************** /********************************************************************************
* @fn OPA_POLL_Lock * @fn OPA_POLL_Lock
* *
* @brief Locks the OPA POLL Controller. * @brief Locks the OPA POLL Controller.
* *
* @return None * @return None
*/ */
void OPA_POLL_Lock(void) void OPA_POLL_Lock(void)
{ {
OPA->CFGR1 |= (1<<7); OPA->CFGR1 |= (1<<7);
} }
/******************************************************************************** /********************************************************************************
* @fn OPA_CMP_Unlock * @fn OPA_CMP_Unlock
* *
* @brief Unlocks the CMP Controller. * @brief Unlocks the CMP Controller.
* *
* @return None * @return None
*/ */
void OPA_CMP_Unlock(void) void OPA_CMP_Unlock(void)
{ {
OPA->CMPKEY = OPA_KEY1; OPA->CMPKEY = OPA_KEY1;
OPA->CMPKEY = OPA_KEY2; OPA->CMPKEY = OPA_KEY2;
} }
/******************************************************************************** /********************************************************************************
* @fn OPA_CMP_Lock * @fn OPA_CMP_Lock
* *
* @brief Locks the CMP Controller. * @brief Locks the CMP Controller.
* *
* @return None * @return None
*/ */
void OPA_CMP_Lock(void) void OPA_CMP_Lock(void)
{ {
CTLR2_tmp |= (1<<31); CTLR2_tmp |= (1<<31);
OPA->CTLR2 = CTLR2_tmp; OPA->CTLR2 = CTLR2_tmp;
CTLR2_tmp &= ~(1<<31); CTLR2_tmp &= ~(1<<31);
} }
/********************************************************************* /*********************************************************************
* @fn OPA_Init * @fn OPA_Init
* *
* @brief Initializes the OPA peripheral according to the specified * @brief Initializes the OPA peripheral according to the specified
* parameters in the OPA_InitStruct. * parameters in the OPA_InitStruct.
* *
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
* *
* @return none * @return none
*/ */
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
{ {
uint16_t tmp0 = 0, tmp1 = 0; uint16_t tmp0 = 0, tmp1 = 0;
uint32_t tmp2 = 0; uint32_t tmp2 = 0;
tmp0 = OPA->CFGR1; tmp0 = OPA->CFGR1;
tmp1 = OPA->CFGR2; tmp1 = OPA->CFGR2;
tmp2 = OPA->CTLR1; tmp2 = OPA->CTLR1;
if(OPA_InitStruct->OPA_NUM == OPA1) if(OPA_InitStruct->OPA_NUM == OPA1)
{ {
tmp1 &= 0xFCFF; tmp1 &= 0xFCFF;
tmp2 &= 0xFFFF0001; tmp2 &= 0xFFFF0001;
tmp1 |= (OPA_InitStruct->POLL_NUM << 9); tmp1 |= (OPA_InitStruct->POLL_NUM << 9);
tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 3) tmp2 |= (OPA_InitStruct->Mode << 1) | (OPA_InitStruct->PSEL << 3)
| (OPA_InitStruct->FB << 5) | (OPA_InitStruct->NSEL << 6); | (OPA_InitStruct->FB << 5) | (OPA_InitStruct->NSEL << 6);
} }
else if(OPA_InitStruct->OPA_NUM == OPA2) else if(OPA_InitStruct->OPA_NUM == OPA2)
{ {
tmp1 &= 0xF3FF; tmp1 &= 0xF3FF;
tmp2 &= 0x0001FFFF; tmp2 &= 0x0001FFFF;
tmp1 |= (OPA_InitStruct->POLL_NUM << 11); tmp1 |= (OPA_InitStruct->POLL_NUM << 11);
tmp2 |= (OPA_InitStruct->Mode << 17) | (OPA_InitStruct->PSEL << 19) tmp2 |= (OPA_InitStruct->Mode << 17) | (OPA_InitStruct->PSEL << 19)
| (OPA_InitStruct->FB << 21) | (OPA_InitStruct->NSEL << 22); | (OPA_InitStruct->FB << 21) | (OPA_InitStruct->NSEL << 22);
} }
tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2) tmp0 |= (OPA_InitStruct->PSEL_POLL) | (OPA_InitStruct->BKIN_EN << 2)
| (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->BKIN_SEL << 6) | (OPA_InitStruct->RST_EN << 4) | (OPA_InitStruct->BKIN_SEL << 6)
| (OPA_InitStruct->OUT_IE << 8) | (OPA_InitStruct->CNT_IE << 10) | (OPA_InitStruct->OUT_IE << 8) | (OPA_InitStruct->CNT_IE << 10)
| (OPA_InitStruct->NMI_IE << 11); | (OPA_InitStruct->NMI_IE << 11);
tmp1 &= 0xFF00; tmp1 &= 0xFF00;
tmp1 |= OPA_InitStruct->OPA_POLL_Interval; tmp1 |= OPA_InitStruct->OPA_POLL_Interval;
OPA->CFGR1 = tmp0; OPA->CFGR1 = tmp0;
OPA->CFGR2 = tmp1; OPA->CFGR2 = tmp1;
OPA->CTLR1 = tmp2; OPA->CTLR1 = tmp2;
} }
/********************************************************************* /*********************************************************************
* @fn OPA_StructInit * @fn OPA_StructInit
* *
* @brief Fills each OPA_StructInit member with its reset value. * @brief Fills each OPA_StructInit member with its reset value.
* *
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
* *
* @return none * @return none
*/ */
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
{ {
OPA_InitStruct->OPA_POLL_Interval = 0; OPA_InitStruct->OPA_POLL_Interval = 0;
OPA_InitStruct->OPA_NUM = OPA1; OPA_InitStruct->OPA_NUM = OPA1;
OPA_InitStruct->Mode = OUT_IO_OUT0; OPA_InitStruct->Mode = OUT_IO_OUT0;
OPA_InitStruct->PSEL = CHP0; OPA_InitStruct->PSEL = CHP0;
OPA_InitStruct->FB = FB_OFF; OPA_InitStruct->FB = FB_OFF;
OPA_InitStruct->NSEL = CHN0; OPA_InitStruct->NSEL = CHN0;
OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF_OPA2_OFF; OPA_InitStruct->PSEL_POLL = CHP_OPA1_OFF_OPA2_OFF;
OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF_OPA2_OFF; OPA_InitStruct->BKIN_EN = BKIN_OPA1_OFF_OPA2_OFF;
OPA_InitStruct->RST_EN = RST_OPA1_OFF_OPA2_OFF; OPA_InitStruct->RST_EN = RST_OPA1_OFF_OPA2_OFF;
OPA_InitStruct->BKIN_SEL = BKIN_OPA1_TIM1_OPA2_TIM2; OPA_InitStruct->BKIN_SEL = BKIN_OPA1_TIM1_OPA2_TIM2;
OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF_OPA2_OFF; OPA_InitStruct->OUT_IE = OUT_IE_OPA1_OFF_OPA2_OFF;
OPA_InitStruct->CNT_IE = CNT_IE_OFF; OPA_InitStruct->CNT_IE = CNT_IE_OFF;
OPA_InitStruct->NMI_IE = NMI_IE_OFF; OPA_InitStruct->NMI_IE = NMI_IE_OFF;
OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1; OPA_InitStruct->POLL_NUM = CHP_POLL_NUM_1;
} }
/********************************************************************* /*********************************************************************
* @fn OPA_Cmd * @fn OPA_Cmd
* *
* @brief Enables or disables the specified OPA peripheral. * @brief Enables or disables the specified OPA peripheral.
* *
* @param OPA_NUM - Select OPA * @param OPA_NUM - Select OPA
* NewState - ENABLE or DISABLE. * NewState - ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
{ {
if(NewState == ENABLE) if(NewState == ENABLE)
{ {
OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16)); OPA->CTLR1 |= (uint32_t)(1 << (OPA_NUM*16));
} }
else else
{ {
OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16)); OPA->CTLR1 &= ~(uint32_t)(1 << (OPA_NUM*16));
} }
} }
/********************************************************************* /*********************************************************************
* @fn OPA_CMP_Init * @fn OPA_CMP_Init
* *
* @brief Initializes the CMP peripheral according to the specified * @brief Initializes the CMP peripheral according to the specified
* parameters in the CMP_InitTypeDef. * parameters in the CMP_InitTypeDef.
* *
* @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure * @param CMP_InitStruct - pointer to a CMP_InitTypeDef structure
* *
* @return none * @return none
*/ */
void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct) void OPA_CMP_Init(CMP_InitTypeDef *CMP_InitStruct)
{ {
uint32_t tmp1 = 0; uint32_t tmp1 = 0;
tmp1 = CTLR2_tmp; tmp1 = CTLR2_tmp;
if(CMP_InitStruct->CMP_NUM == CMP1) if(CMP_InitStruct->CMP_NUM == CMP1)
{ {
tmp1 &= 0xFFFFFFE1; tmp1 &= 0xFFFFFFE1;
tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 2) tmp1 |= (CMP_InitStruct->Mode << 1) | (CMP_InitStruct->NSEL << 2)
| (CMP_InitStruct->PSEL << 3) | (CMP_InitStruct->HYEN << 4); | (CMP_InitStruct->PSEL << 3) | (CMP_InitStruct->HYEN << 4);
} }
else if(CMP_InitStruct->CMP_NUM == CMP2) else if(CMP_InitStruct->CMP_NUM == CMP2)
{ {
tmp1 &= 0xFFFFFC3F; tmp1 &= 0xFFFFFC3F;
tmp1 |= (CMP_InitStruct->Mode << 6) | (CMP_InitStruct->NSEL << 7) tmp1 |= (CMP_InitStruct->Mode << 6) | (CMP_InitStruct->NSEL << 7)
| (CMP_InitStruct->PSEL << 8) | (CMP_InitStruct->HYEN << 9); | (CMP_InitStruct->PSEL << 8) | (CMP_InitStruct->HYEN << 9);
} }
else if(CMP_InitStruct->CMP_NUM == CMP3) else if(CMP_InitStruct->CMP_NUM == CMP3)
{ {
tmp1 &= 0xFFFF87FF; tmp1 &= 0xFFFF87FF;
tmp1 |= (CMP_InitStruct->Mode << 11) | (CMP_InitStruct->NSEL << 12) tmp1 |= (CMP_InitStruct->Mode << 11) | (CMP_InitStruct->NSEL << 12)
| (CMP_InitStruct->PSEL << 13) | (CMP_InitStruct->HYEN << 14); | (CMP_InitStruct->PSEL << 13) | (CMP_InitStruct->HYEN << 14);
} }
CTLR2_tmp = tmp1; CTLR2_tmp = tmp1;
OPA->CTLR2 = tmp1; OPA->CTLR2 = tmp1;
} }
/********************************************************************* /*********************************************************************
* @fn OPA_CMP_StructInit * @fn OPA_CMP_StructInit
* *
* @brief Fills each OPA_CMP_StructInit member with its reset value. * @brief Fills each OPA_CMP_StructInit member with its reset value.
* *
* @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure * @param CMP_StructInit - pointer to a OPA_CMP_StructInit structure
* *
* @return none * @return none
*/ */
void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct) void OPA_CMP_StructInit(CMP_InitTypeDef *CMP_InitStruct)
{ {
CMP_InitStruct->CMP_NUM = CMP1; CMP_InitStruct->CMP_NUM = CMP1;
CMP_InitStruct->Mode = OUT_IO_TIM2; CMP_InitStruct->Mode = OUT_IO_TIM2;
CMP_InitStruct->NSEL = CMP_CHN0; CMP_InitStruct->NSEL = CMP_CHN0;
CMP_InitStruct->PSEL = CMP_CHP1; CMP_InitStruct->PSEL = CMP_CHP1;
CMP_InitStruct->HYEN = CMP_HYEN1; CMP_InitStruct->HYEN = CMP_HYEN1;
} }
/********************************************************************* /*********************************************************************
* @fn OPA_CMP_Cmd * @fn OPA_CMP_Cmd
* *
* @brief Enables or disables the specified CMP peripheral. * @brief Enables or disables the specified CMP peripheral.
* *
* @param CMP_NUM - Select CMP * @param CMP_NUM - Select CMP
* NewState - ENABLE or DISABLE. * NewState - ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState) void OPA_CMP_Cmd(CMP_Num_TypeDef CMP_NUM, FunctionalState NewState)
{ {
if(NewState == ENABLE) if(NewState == ENABLE)
{ {
CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*5)); CTLR2_tmp |= (uint32_t)(1 << (CMP_NUM*5));
} }
else else
{ {
CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*5)); CTLR2_tmp &= ~(uint32_t)(1 << (CMP_NUM*5));
} }
OPA->CTLR2 = CTLR2_tmp; OPA->CTLR2 = CTLR2_tmp;
} }
/********************************************************************* /*********************************************************************
* @fn OPA_GetFlagStatus * @fn OPA_GetFlagStatus
* *
* @brief Checks whether the OPA flag is set or not. * @brief Checks whether the OPA flag is set or not.
* *
* @param OPA_FLAG - specifies the SPI/I2S flag to check. * @param OPA_FLAG - specifies the SPI/I2S flag to check.
* OPA_FLAG_OUT_OPA1 - OPA1 out flag * OPA_FLAG_OUT_OPA1 - OPA1 out flag
* OPA_FLAG_OUT_OPA2 - OPA2 out flag * OPA_FLAG_OUT_OPA2 - OPA2 out flag
* OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data
* *
* @return FlagStatus: SET or RESET. * @return FlagStatus: SET or RESET.
*/ */
FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG) FlagStatus OPA_GetFlagStatus(uint16_t OPA_FLAG)
{ {
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET) if((OPA->CFGR1 & OPA_FLAG) != (uint16_t)RESET)
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/********************************************************************* /*********************************************************************
* @fn OPA_ClearFlag * @fn OPA_ClearFlag
* *
* @brief Clears the OPA flag. * @brief Clears the OPA flag.
* *
* @param OPA_FLAG - specifies the OPA flag to clear. * @param OPA_FLAG - specifies the OPA flag to clear.
* OPA_FLAG_OUT_OPA1 - OPA1 out flag * OPA_FLAG_OUT_OPA1 - OPA1 out flag
* OPA_FLAG_OUT_OPA2 - OPA2 out flag * OPA_FLAG_OUT_OPA2 - OPA2 out flag
* OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data * OPA_FLAG_OUT_CNT - OPA out flag rising edge of sampling data
* @return none * @return none
*/ */
void OPA_ClearFlag(uint16_t OPA_FLAG) void OPA_ClearFlag(uint16_t OPA_FLAG)
{ {
OPA->CFGR1 &= (uint16_t)~OPA_FLAG; OPA->CFGR1 &= (uint16_t)~OPA_FLAG;
} }

312
Peripheral/src/ch32x035_pwr.c
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@ -1,156 +1,156 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_pwr.c * File Name : ch32x035_pwr.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the PWR firmware functions. * Description : This file provides all the PWR firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_pwr.h" #include "ch32x035_pwr.h"
#include "ch32x035_rcc.h" #include "ch32x035_rcc.h"
/* PWR registers bit mask */ /* PWR registers bit mask */
/* CTLR register bit mask */ /* CTLR register bit mask */
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD) #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF9F) #define CTLR_PLS_MASK ((uint32_t)0xFFFFFF9F)
/********************************************************************* /*********************************************************************
* @fn PWR_DeInit * @fn PWR_DeInit
* *
* @brief Deinitializes the PWR peripheral registers to their default * @brief Deinitializes the PWR peripheral registers to their default
* reset values. * reset values.
* *
* @return none * @return none
*/ */
void PWR_DeInit(void) void PWR_DeInit(void)
{ {
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
} }
/********************************************************************* /*********************************************************************
* @fn PWR_PVDLevelConfig * @fn PWR_PVDLevelConfig
* *
* @brief Configures the voltage threshold detected by the Power Voltage * @brief Configures the voltage threshold detected by the Power Voltage
* Detector(PVD). * Detector(PVD).
* *
* @param PWR_PVDLevel - specifies the PVD detection level * @param PWR_PVDLevel - specifies the PVD detection level
* PWR_PVDLevel_2V1 - PVD detection level set to 2.1V * PWR_PVDLevel_2V1 - PVD detection level set to 2.1V
* PWR_PVDLevel_2V3 - PVD detection level set to 2.3V * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
* PWR_PVDLevel_3V0 - PVD detection level set to 3.0V * PWR_PVDLevel_3V0 - PVD detection level set to 3.0V
* PWR_PVDLevel_4V0 - PVD detection level set to 4.0V * PWR_PVDLevel_4V0 - PVD detection level set to 4.0V
* *
* @return none * @return none
*/ */
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = PWR->CTLR; tmpreg = PWR->CTLR;
tmpreg &= CTLR_PLS_MASK; tmpreg &= CTLR_PLS_MASK;
tmpreg |= PWR_PVDLevel; tmpreg |= PWR_PVDLevel;
PWR->CTLR = tmpreg; PWR->CTLR = tmpreg;
} }
/********************************************************************* /*********************************************************************
* @fn PWR_EnterSTOPMode * @fn PWR_EnterSTOPMode
* *
* @brief Enters STOP mode. * @brief Enters STOP mode.
* *
* @param PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. * @param PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
* *
* @return none * @return none
*/ */
void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry) void PWR_EnterSTOPMode(uint8_t PWR_STOPEntry)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = PWR->CTLR; tmpreg = PWR->CTLR;
tmpreg &= CTLR_DS_MASK; tmpreg &= CTLR_DS_MASK;
PWR->CTLR = tmpreg; PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2); NVIC->SCTLR |= (1 << 2);
if(PWR_STOPEntry == PWR_STOPEntry_WFI) if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{ {
__WFI(); __WFI();
} }
else else
{ {
__WFE(); __WFE();
} }
NVIC->SCTLR &= ~(1 << 2); NVIC->SCTLR &= ~(1 << 2);
} }
/********************************************************************* /*********************************************************************
* @fn PWR_EnterSTANDBYMode * @fn PWR_EnterSTANDBYMode
* *
* @brief Enters STANDBY mode. * @brief Enters STANDBY mode.
* *
* @return none * @return none
*/ */
void PWR_EnterSTANDBYMode(void) void PWR_EnterSTANDBYMode(void)
{ {
PWR->CTLR |= PWR_CTLR_PDDS; PWR->CTLR |= PWR_CTLR_PDDS;
NVIC->SCTLR |= (1 << 2); NVIC->SCTLR |= (1 << 2);
__WFI(); __WFI();
} }
/********************************************************************* /*********************************************************************
* @fn PWR_GetFlagStatus * @fn PWR_GetFlagStatus
* *
* @brief Checks whether the specified PWR flag is set or not. * @brief Checks whether the specified PWR flag is set or not.
* *
* @param PWR_FLAG - specifies the flag to check. * @param PWR_FLAG - specifies the flag to check.
* PWR_FLAG_PVDO - PVD Output * PWR_FLAG_PVDO - PVD Output
* PWR_FLAG_FLASH - Flash low power flag * PWR_FLAG_FLASH - Flash low power flag
* *
* @return The new state of PWR_FLAG (SET or RESET). * @return The new state of PWR_FLAG (SET or RESET).
*/ */
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{ {
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/********************************************************************* /*********************************************************************
* @fn PWR_VDD_SupplyVoltage * @fn PWR_VDD_SupplyVoltage
* *
* @brief Checks VDD Supply Voltage. * @brief Checks VDD Supply Voltage.
* *
* @param none * @param none
* *
* @return PWR_VDD - VDD Supply Voltage. * @return PWR_VDD - VDD Supply Voltage.
* PWR_VDD_5V - VDD = 5V * PWR_VDD_5V - VDD = 5V
* PWR_VDD_3V3 - VDD = 3.3V * PWR_VDD_3V3 - VDD = 3.3V
*/ */
PWR_VDD PWR_VDD_SupplyVoltage(void) PWR_VDD PWR_VDD_SupplyVoltage(void)
{ {
PWR_VDD VDD_Voltage = PWR_VDD_3V3; PWR_VDD VDD_Voltage = PWR_VDD_3V3;
Delay_Init(); Delay_Init();
RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE); RCC_APB1PeriphClockCmd( RCC_APB1Periph_PWR, ENABLE);
PWR_PVDLevelConfig(PWR_PVDLevel_4V0); PWR_PVDLevelConfig(PWR_PVDLevel_4V0);
Delay_Us(10); Delay_Us(10);
if( PWR_GetFlagStatus(PWR_FLAG_PVDO) == (uint32_t)RESET) if( PWR_GetFlagStatus(PWR_FLAG_PVDO) == (uint32_t)RESET)
{ {
VDD_Voltage = PWR_VDD_5V; VDD_Voltage = PWR_VDD_5V;
} }
PWR_PVDLevelConfig(PWR_PVDLevel_2V1); PWR_PVDLevelConfig(PWR_PVDLevel_2V1);
return VDD_Voltage; return VDD_Voltage;
} }

822
Peripheral/src/ch32x035_rcc.c
View file

@ -1,411 +1,411 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_rcc.c * File Name : ch32x035_rcc.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the RCC firmware functions. * Description : This file provides all the RCC firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_rcc.h" #include "ch32x035_rcc.h"
/* RCC registers bit mask */ /* RCC registers bit mask */
/* CTLR register bit mask */ /* CTLR register bit mask */
#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) #define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
/* CFGR0 register bit mask */ /* CFGR0 register bit mask */
#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) #define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) #define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
/* RSTSCKR register bit mask */ /* RSTSCKR register bit mask */
#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) #define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
/* RCC Flag Mask */ /* RCC Flag Mask */
#define FLAG_Mask ((uint8_t)0x1F) #define FLAG_Mask ((uint8_t)0x1F)
/* CFGR0 register byte 4 (Bits[31:24]) base address */ /* CFGR0 register byte 4 (Bits[31:24]) base address */
#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) #define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
/********************************************************************* /*********************************************************************
* @fn RCC_DeInit * @fn RCC_DeInit
* *
* @brief Resets the RCC clock configuration to the default reset state. * @brief Resets the RCC clock configuration to the default reset state.
* Note- * Note-
* HSE can not be stopped if it is used directly or through the PLL as system clock. * HSE can not be stopped if it is used directly or through the PLL as system clock.
* @return none * @return none
*/ */
void RCC_DeInit(void) void RCC_DeInit(void)
{ {
RCC->CTLR |= (uint32_t)0x00000001; RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 |= (uint32_t)0x00000050; RCC->CFGR0 |= (uint32_t)0x00000050;
RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; RCC->CFGR0 &= (uint32_t)0xF8FFFF5F;
} }
/********************************************************************* /*********************************************************************
* @fn RCC_AdjustHSICalibrationValue * @fn RCC_AdjustHSICalibrationValue
* *
* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
* *
* @param HSICalibrationValue - specifies the calibration trimming value. * @param HSICalibrationValue - specifies the calibration trimming value.
* This parameter must be a number between 0 and 0x1F. * This parameter must be a number between 0 and 0x1F.
* *
* @return none * @return none
*/ */
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = RCC->CTLR; tmpreg = RCC->CTLR;
tmpreg &= CTLR_HSITRIM_Mask; tmpreg &= CTLR_HSITRIM_Mask;
tmpreg |= (uint32_t)HSICalibrationValue << 3; tmpreg |= (uint32_t)HSICalibrationValue << 3;
RCC->CTLR = tmpreg; RCC->CTLR = tmpreg;
} }
/********************************************************************* /*********************************************************************
* @fn RCC_HSICmd * @fn RCC_HSICmd
* *
* @brief Enables or disables the Internal High Speed oscillator (HSI). * @brief Enables or disables the Internal High Speed oscillator (HSI).
* *
* @param NewState - ENABLE or DISABLE. * @param NewState - ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void RCC_HSICmd(FunctionalState NewState) void RCC_HSICmd(FunctionalState NewState)
{ {
if(NewState) if(NewState)
{ {
RCC->CTLR |= (1<<0); RCC->CTLR |= (1<<0);
} }
else{ else{
RCC->CTLR &= ~(1<<0); RCC->CTLR &= ~(1<<0);
} }
} }
/********************************************************************* /*********************************************************************
* @fn RCC_HCLKConfig * @fn RCC_HCLKConfig
* *
* @brief Configures the AHB clock (HCLK). * @brief Configures the AHB clock (HCLK).
* *
* @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
* the system clock (SYSCLK). * the system clock (SYSCLK).
* RCC_SYSCLK_Div1 - AHB clock = SYSCLK. * RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
* RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
* RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3. * RCC_SYSCLK_Div3 - AHB clock = SYSCLK/3.
* RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
* RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5. * RCC_SYSCLK_Div5 - AHB clock = SYSCLK/5.
* RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6. * RCC_SYSCLK_Div6 - AHB clock = SYSCLK/6.
* RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7. * RCC_SYSCLK_Div7 - AHB clock = SYSCLK/7.
* RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
* RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
* RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32. * RCC_SYSCLK_Div32 - AHB clock = SYSCLK/32.
* RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
* RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
* RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
* *
* @return none * @return none
*/ */
void RCC_HCLKConfig(uint32_t RCC_SYSCLK) void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = RCC->CFGR0; tmpreg = RCC->CFGR0;
tmpreg &= CFGR0_HPRE_Reset_Mask; tmpreg &= CFGR0_HPRE_Reset_Mask;
tmpreg |= RCC_SYSCLK; tmpreg |= RCC_SYSCLK;
RCC->CFGR0 = tmpreg; RCC->CFGR0 = tmpreg;
} }
/********************************************************************* /*********************************************************************
* @fn RCC_GetClocksFreq * @fn RCC_GetClocksFreq
* *
* @brief The result of this function could be not correct when using * @brief The result of this function could be not correct when using
* fractional value for HSE crystal. * fractional value for HSE crystal.
* *
* @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
* the clocks frequencies. * the clocks frequencies.
* *
* @return none * @return none
*/ */
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{ {
uint32_t tmp = 0, presc = 0; uint32_t tmp = 0, presc = 0;
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
tmp = tmp >> 4; tmp = tmp >> 4;
presc = APBAHBPrescTable[tmp]; presc = APBAHBPrescTable[tmp];
if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8) if(((RCC->CFGR0 & CFGR0_HPRE_Set_Mask) >> 4) < 8)
{ {
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc; RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency / presc;
} }
else else
{ {
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
} }
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency; RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency;
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency; RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency;
} }
/********************************************************************* /*********************************************************************
* @fn RCC_AHBPeriphClockCmd * @fn RCC_AHBPeriphClockCmd
* *
* @brief Enables or disables the AHB peripheral clock. * @brief Enables or disables the AHB peripheral clock.
* *
* @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
* RCC_AHBPeriph_DMA1. * RCC_AHBPeriph_DMA1.
* RCC_AHBPeriph_SRAM. * RCC_AHBPeriph_SRAM.
* RCC_AHBPeriph_USBFS. * RCC_AHBPeriph_USBFS.
* RCC_AHBPeriph_USBPD * RCC_AHBPeriph_USBPD
* Note- * Note-
* SRAM clock can be disabled only during sleep mode. * SRAM clock can be disabled only during sleep mode.
* NewState: ENABLE or DISABLE. * NewState: ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{ {
if (NewState != DISABLE) if (NewState != DISABLE)
{ {
RCC->AHBPCENR |= RCC_AHBPeriph; RCC->AHBPCENR |= RCC_AHBPeriph;
} }
else else
{ {
RCC->AHBPCENR &= ~RCC_AHBPeriph; RCC->AHBPCENR &= ~RCC_AHBPeriph;
} }
} }
/********************************************************************* /*********************************************************************
* @fn RCC_APB2PeriphClockCmd * @fn RCC_APB2PeriphClockCmd
* *
* @brief Enables or disables the High Speed APB (APB2) peripheral clock. * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
* *
* @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
* RCC_APB2Periph_AFIO. * RCC_APB2Periph_AFIO.
* RCC_APB2Periph_GPIOA. * RCC_APB2Periph_GPIOA.
* RCC_APB2Periph_GPIOB. * RCC_APB2Periph_GPIOB.
* RCC_APB2Periph_GPIOC. * RCC_APB2Periph_GPIOC.
* RCC_APB2Periph_ADC1. * RCC_APB2Periph_ADC1.
* RCC_APB2Periph_TIM1. * RCC_APB2Periph_TIM1.
* RCC_APB2Periph_SPI1. * RCC_APB2Periph_SPI1.
* RCC_APB2Periph_USART1. * RCC_APB2Periph_USART1.
* NewState - ENABLE or DISABLE * NewState - ENABLE or DISABLE
* *
* @return none * @return none
*/ */
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{ {
if (NewState != DISABLE) if (NewState != DISABLE)
{ {
RCC->APB2PCENR |= RCC_APB2Periph; RCC->APB2PCENR |= RCC_APB2Periph;
} }
else else
{ {
RCC->APB2PCENR &= ~RCC_APB2Periph; RCC->APB2PCENR &= ~RCC_APB2Periph;
} }
} }
/********************************************************************* /*********************************************************************
* @fn RCC_APB1PeriphClockCmd * @fn RCC_APB1PeriphClockCmd
* *
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock. * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
* *
* @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
* RCC_APB1Periph_TIM2. * RCC_APB1Periph_TIM2.
* RCC_APB1Periph_TIM3. * RCC_APB1Periph_TIM3.
* RCC_APB1Periph_WWDG. * RCC_APB1Periph_WWDG.
* RCC_APB1Periph_USART2. * RCC_APB1Periph_USART2.
* RCC_APB1Periph_USART3. * RCC_APB1Periph_USART3.
* RCC_APB1Periph_USART4 * RCC_APB1Periph_USART4
* RCC_APB1Periph_I2C1. * RCC_APB1Periph_I2C1.
* RCC_APB1Periph_PWR. * RCC_APB1Periph_PWR.
* NewState - ENABLE or DISABLE. * NewState - ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{ {
if (NewState != DISABLE) if (NewState != DISABLE)
{ {
RCC->APB1PCENR |= RCC_APB1Periph; RCC->APB1PCENR |= RCC_APB1Periph;
} }
else else
{ {
RCC->APB1PCENR &= ~RCC_APB1Periph; RCC->APB1PCENR &= ~RCC_APB1Periph;
} }
} }
/********************************************************************* /*********************************************************************
* @fn RCC_AHBPeriphResetCmd * @fn RCC_AHBPeriphResetCmd
* *
* @brief Forces or releases AHB peripheral reset. * @brief Forces or releases AHB peripheral reset.
* *
* @param RCC_AHBPeriph - specifies the AHB peripheral to reset. * @param RCC_AHBPeriph - specifies the AHB peripheral to reset.
* RCC_AHBPeriph_USBFS. * RCC_AHBPeriph_USBFS.
* RCC_AHBPeriph_IO2W. * RCC_AHBPeriph_IO2W.
* RCC_AHBPeriph_USBPD. * RCC_AHBPeriph_USBPD.
* NewState: ENABLE or DISABLE. * NewState: ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
{ {
if (NewState != DISABLE) if (NewState != DISABLE)
{ {
RCC->AHBPCENR |= RCC_AHBPeriph; RCC->AHBPCENR |= RCC_AHBPeriph;
} }
else else
{ {
RCC->AHBPCENR &= ~RCC_AHBPeriph; RCC->AHBPCENR &= ~RCC_AHBPeriph;
} }
} }
/********************************************************************* /*********************************************************************
* @fn RCC_APB2PeriphResetCmd * @fn RCC_APB2PeriphResetCmd
* *
* @brief Forces or releases APB (APB2) peripheral reset. * @brief Forces or releases APB (APB2) peripheral reset.
* *
* @param RCC_APB2Periph - specifies the APB2 peripheral to reset. * @param RCC_APB2Periph - specifies the APB2 peripheral to reset.
* RCC_APB2Periph_AFIO. * RCC_APB2Periph_AFIO.
* RCC_APB2Periph_GPIOA. * RCC_APB2Periph_GPIOA.
* RCC_APB2Periph_GPIOB. * RCC_APB2Periph_GPIOB.
* RCC_APB2Periph_GPIOC. * RCC_APB2Periph_GPIOC.
* RCC_APB2Periph_ADC1. * RCC_APB2Periph_ADC1.
* RCC_APB2Periph_TIM1. * RCC_APB2Periph_TIM1.
* RCC_APB2Periph_SPI1. * RCC_APB2Periph_SPI1.
* RCC_APB2Periph_USART1. * RCC_APB2Periph_USART1.
* NewState - ENABLE or DISABLE * NewState - ENABLE or DISABLE
* *
* @return none * @return none
*/ */
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
{ {
if (NewState != DISABLE) if (NewState != DISABLE)
{ {
RCC->APB2PRSTR |= RCC_APB2Periph; RCC->APB2PRSTR |= RCC_APB2Periph;
} }
else else
{ {
RCC->APB2PRSTR &= ~RCC_APB2Periph; RCC->APB2PRSTR &= ~RCC_APB2Periph;
} }
} }
/********************************************************************* /*********************************************************************
* @fn RCC_APB1PeriphResetCmd * @fn RCC_APB1PeriphResetCmd
* *
* @brief Forces or releases APB (APB1) peripheral reset. * @brief Forces or releases APB (APB1) peripheral reset.
* *
* @param RCC_APB1Periph - specifies the APB1 peripheral to reset. * @param RCC_APB1Periph - specifies the APB1 peripheral to reset.
* RCC_APB1Periph_TIM2. * RCC_APB1Periph_TIM2.
* RCC_APB1Periph_TIM3. * RCC_APB1Periph_TIM3.
* RCC_APB1Periph_WWDG. * RCC_APB1Periph_WWDG.
* RCC_APB1Periph_USART2. * RCC_APB1Periph_USART2.
* RCC_APB1Periph_USART3. * RCC_APB1Periph_USART3.
* RCC_APB1Periph_USART4 * RCC_APB1Periph_USART4
* RCC_APB1Periph_I2C1. * RCC_APB1Periph_I2C1.
* RCC_APB1Periph_PWR. * RCC_APB1Periph_PWR.
* NewState - ENABLE or DISABLE. * NewState - ENABLE or DISABLE.
* *
* @return none * @return none
*/ */
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
{ {
if (NewState != DISABLE) if (NewState != DISABLE)
{ {
RCC->APB1PRSTR |= RCC_APB1Periph; RCC->APB1PRSTR |= RCC_APB1Periph;
} }
else else
{ {
RCC->APB1PRSTR &= ~RCC_APB1Periph; RCC->APB1PRSTR &= ~RCC_APB1Periph;
} }
} }
/********************************************************************* /*********************************************************************
* @fn RCC_MCOConfig * @fn RCC_MCOConfig
* *
* @brief Selects the clock source to output on MCO pin. * @brief Selects the clock source to output on MCO pin.
* *
* @param RCC_MCO - specifies the clock source to output. * @param RCC_MCO - specifies the clock source to output.
* RCC_MCO_NoClock - No clock selected. * RCC_MCO_NoClock - No clock selected.
* RCC_MCO_SYSCLK - System clock selected. * RCC_MCO_SYSCLK - System clock selected.
* RCC_MCO_HSI - HSI oscillator clock selected. * RCC_MCO_HSI - HSI oscillator clock selected.
* *
* @return none * @return none
*/ */
void RCC_MCOConfig(uint8_t RCC_MCO) void RCC_MCOConfig(uint8_t RCC_MCO)
{ {
*(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO; *(__IO uint8_t *) CFGR0_BYTE4_ADDRESS = RCC_MCO;
} }
/********************************************************************* /*********************************************************************
* @fn RCC_GetFlagStatus * @fn RCC_GetFlagStatus
* *
* @brief Checks whether the specified RCC flag is set or not. * @brief Checks whether the specified RCC flag is set or not.
* *
* @param RCC_FLAG - specifies the flag to check. * @param RCC_FLAG - specifies the flag to check.
* RCC_FLAG_HSIRDY - HSI oscillator clock ready. * RCC_FLAG_HSIRDY - HSI oscillator clock ready.
* RCC_FLAG_OPARST - OPA reset. * RCC_FLAG_OPARST - OPA reset.
* RCC_FLAG_PINRST - Pin reset. * RCC_FLAG_PINRST - Pin reset.
* RCC_FLAG_PORRST - POR/PDR reset. * RCC_FLAG_PORRST - POR/PDR reset.
* RCC_FLAG_SFTRST - Software reset. * RCC_FLAG_SFTRST - Software reset.
* RCC_FLAG_IWDGRST - Independent Watchdog reset. * RCC_FLAG_IWDGRST - Independent Watchdog reset.
* RCC_FLAG_WWDGRST - Window Watchdog reset. * RCC_FLAG_WWDGRST - Window Watchdog reset.
* RCC_FLAG_LPWRRST - Low Power reset. * RCC_FLAG_LPWRRST - Low Power reset.
* *
* @return FlagStatus - SET or RESET. * @return FlagStatus - SET or RESET.
*/ */
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
{ {
uint32_t tmp = 0; uint32_t tmp = 0;
uint32_t statusreg = 0; uint32_t statusreg = 0;
FlagStatus bitstatus = RESET; FlagStatus bitstatus = RESET;
tmp = RCC_FLAG >> 5; tmp = RCC_FLAG >> 5;
if (tmp == 1) if (tmp == 1)
{ {
statusreg = RCC->CTLR; statusreg = RCC->CTLR;
} }
else else
{ {
statusreg = RCC->RSTSCKR; statusreg = RCC->RSTSCKR;
} }
tmp = RCC_FLAG & FLAG_Mask; tmp = RCC_FLAG & FLAG_Mask;
if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
{ {
bitstatus = SET; bitstatus = SET;
} }
else else
{ {
bitstatus = RESET; bitstatus = RESET;
} }
return bitstatus; return bitstatus;
} }
/********************************************************************* /*********************************************************************
* @fn RCC_ClearFlag * @fn RCC_ClearFlag
* *
* @brief Clears the RCC reset flags. * @brief Clears the RCC reset flags.
* Note- * Note-
* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
* @return none * @return none
*/ */
void RCC_ClearFlag(void) void RCC_ClearFlag(void)
{ {
RCC->RSTSCKR |= RSTSCKR_RMVF_Set; RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
} }

1012
Peripheral/src/ch32x035_spi.c
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4914
Peripheral/src/ch32x035_tim.c
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1486
Peripheral/src/ch32x035_usart.c
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282
Peripheral/src/ch32x035_wwdg.c
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@ -1,141 +1,141 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_wwdg.c * File Name : ch32x035_wwdg.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : This file provides all the WWDG firmware functions. * Description : This file provides all the WWDG firmware functions.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_wwdg.h" #include "ch32x035_wwdg.h"
#include "ch32x035_rcc.h" #include "ch32x035_rcc.h"
/* CTLR register bit mask */ /* CTLR register bit mask */
#define CTLR_WDGA_Set ((uint32_t)0x00000080) #define CTLR_WDGA_Set ((uint32_t)0x00000080)
/* CFGR register bit mask */ /* CFGR register bit mask */
#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) #define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) #define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
#define BIT_Mask ((uint8_t)0x7F) #define BIT_Mask ((uint8_t)0x7F)
/********************************************************************* /*********************************************************************
* @fn WWDG_DeInit * @fn WWDG_DeInit
* *
* @brief Deinitializes the WWDG peripheral registers to their default reset values * @brief Deinitializes the WWDG peripheral registers to their default reset values
* *
* @return none * @return none
*/ */
void WWDG_DeInit(void) void WWDG_DeInit(void)
{ {
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
} }
/********************************************************************* /*********************************************************************
* @fn WWDG_SetPrescaler * @fn WWDG_SetPrescaler
* *
* @brief Sets the WWDG Prescaler * @brief Sets the WWDG Prescaler
* *
* @param WWDG_Prescaler - specifies the WWDG Prescaler * @param WWDG_Prescaler - specifies the WWDG Prescaler
* WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
* WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
* WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
* WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
* *
* @return none * @return none
*/ */
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
{ {
uint32_t tmpreg = 0; uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
tmpreg |= WWDG_Prescaler; tmpreg |= WWDG_Prescaler;
WWDG->CFGR = tmpreg; WWDG->CFGR = tmpreg;
} }
/********************************************************************* /*********************************************************************
* @fn WWDG_SetWindowValue * @fn WWDG_SetWindowValue
* *
* @brief Sets the WWDG window value * @brief Sets the WWDG window value
* *
* @param WindowValue - specifies the window value to be compared to the * @param WindowValue - specifies the window value to be compared to the
* downcounter,which must be lower than 0x80 * downcounter,which must be lower than 0x80
* *
* @return none * @return none
*/ */
void WWDG_SetWindowValue(uint8_t WindowValue) void WWDG_SetWindowValue(uint8_t WindowValue)
{ {
__IO uint32_t tmpreg = 0; __IO uint32_t tmpreg = 0;
tmpreg = WWDG->CFGR & CFGR_W_Mask; tmpreg = WWDG->CFGR & CFGR_W_Mask;
tmpreg |= WindowValue & (uint32_t)BIT_Mask; tmpreg |= WindowValue & (uint32_t)BIT_Mask;
WWDG->CFGR = tmpreg; WWDG->CFGR = tmpreg;
} }
/********************************************************************* /*********************************************************************
* @fn WWDG_EnableIT * @fn WWDG_EnableIT
* *
* @brief Enables the WWDG Early Wakeup interrupt(EWI) * @brief Enables the WWDG Early Wakeup interrupt(EWI)
* *
* @return none * @return none
*/ */
void WWDG_EnableIT(void) void WWDG_EnableIT(void)
{ {
WWDG->CFGR |= (1 << 9); WWDG->CFGR |= (1 << 9);
} }
/********************************************************************* /*********************************************************************
* @fn WWDG_SetCounter * @fn WWDG_SetCounter
* *
* @brief Sets the WWDG counter value * @brief Sets the WWDG counter value
* *
* @param Counter - specifies the watchdog counter value,which must be a * @param Counter - specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F * number between 0x40 and 0x7F
* *
* @return none * @return none
*/ */
void WWDG_SetCounter(uint8_t Counter) void WWDG_SetCounter(uint8_t Counter)
{ {
WWDG->CTLR = Counter & BIT_Mask; WWDG->CTLR = Counter & BIT_Mask;
} }
/********************************************************************* /*********************************************************************
* @fn WWDG_Enable * @fn WWDG_Enable
* *
* @brief Enables WWDG and load the counter value * @brief Enables WWDG and load the counter value
* *
* @param Counter - specifies the watchdog counter value,which must be a * @param Counter - specifies the watchdog counter value,which must be a
* number between 0x40 and 0x7F * number between 0x40 and 0x7F
* @return none * @return none
*/ */
void WWDG_Enable(uint8_t Counter) void WWDG_Enable(uint8_t Counter)
{ {
WWDG->CTLR = CTLR_WDGA_Set | Counter; WWDG->CTLR = CTLR_WDGA_Set | Counter;
} }
/********************************************************************* /*********************************************************************
* @fn WWDG_GetFlagStatus * @fn WWDG_GetFlagStatus
* *
* @brief Checks whether the Early Wakeup interrupt flag is set or not * @brief Checks whether the Early Wakeup interrupt flag is set or not
* *
* @return The new state of the Early Wakeup interrupt flag (SET or RESET) * @return The new state of the Early Wakeup interrupt flag (SET or RESET)
*/ */
FlagStatus WWDG_GetFlagStatus(void) FlagStatus WWDG_GetFlagStatus(void)
{ {
return (FlagStatus)(WWDG->STATR); return (FlagStatus)(WWDG->STATR);
} }
/********************************************************************* /*********************************************************************
* @fn WWDG_ClearFlag * @fn WWDG_ClearFlag
* *
* @brief Clears Early Wakeup interrupt flag * @brief Clears Early Wakeup interrupt flag
* *
* @return none * @return none
*/ */
void WWDG_ClearFlag(void) void WWDG_ClearFlag(void)
{ {
WWDG->STATR = (uint32_t)RESET; WWDG->STATR = (uint32_t)RESET;
} }

78
User/ch32x035_conf.h
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@ -1,39 +1,39 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_conf.h * File Name : ch32x035_conf.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : Library configuration file. * Description : Library configuration file.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __CH32X035_CONF_H #ifndef __CH32X035_CONF_H
#define __CH32X035_CONF_H #define __CH32X035_CONF_H
#include "ch32x035_adc.h" #include "ch32x035_adc.h"
#include "ch32x035_awu.h" #include "ch32x035_awu.h"
#include "ch32x035_dbgmcu.h" #include "ch32x035_dbgmcu.h"
#include "ch32x035_dma.h" #include "ch32x035_dma.h"
#include "ch32x035_exti.h" #include "ch32x035_exti.h"
#include "ch32x035_flash.h" #include "ch32x035_flash.h"
#include "ch32x035_gpio.h" #include "ch32x035_gpio.h"
#include "ch32x035_i2c.h" #include "ch32x035_i2c.h"
#include "ch32x035_iwdg.h" #include "ch32x035_iwdg.h"
#include "ch32x035_pwr.h" #include "ch32x035_pwr.h"
#include "ch32x035_rcc.h" #include "ch32x035_rcc.h"
#include "ch32x035_spi.h" #include "ch32x035_spi.h"
#include "ch32x035_tim.h" #include "ch32x035_tim.h"
#include "ch32x035_usart.h" #include "ch32x035_usart.h"
#include "ch32x035_wwdg.h" #include "ch32x035_wwdg.h"
#include "ch32x035_it.h" #include "ch32x035_it.h"
#include "ch32x035_misc.h" #include "ch32x035_misc.h"
#endif #endif

84
User/ch32x035_it.c
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@ -1,42 +1,42 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : ch32x035_it.c * File Name : ch32x035_it.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : Main Interrupt Service Routines. * Description : Main Interrupt Service Routines.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035_it.h" #include "ch32x035_it.h"
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
/********************************************************************* /*********************************************************************
* @fn NMI_Handler * @fn NMI_Handler
* *
* @brief This function handles NMI exception. * @brief This function handles NMI exception.
* *
* @return none * @return none
*/ */
void NMI_Handler(void) void NMI_Handler(void)
{ {
} }
/********************************************************************* /*********************************************************************
* @fn HardFault_Handler * @fn HardFault_Handler
* *
* @brief This function handles Hard Fault exception. * @brief This function handles Hard Fault exception.
* *
* @return none * @return none
*/ */
void HardFault_Handler(void) void HardFault_Handler(void)
{ {
while (1) while (1)
{ {
} }
} }

82
User/main.c
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@ -1,41 +1,41 @@
#include "debug.h" #include "debug.h"
void GPIO_LED_Init(void) void GPIO_LED_Init(void)
{ {
GPIO_InitTypeDef GPIO_InitStructure = {0}; GPIO_InitTypeDef GPIO_InitStructure = {0};
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_Init(GPIOA, &GPIO_InitStructure); GPIO_Init(GPIOA, &GPIO_InitStructure);
} }
int main(void) int main(void)
{ {
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
SystemCoreClockUpdate(); SystemCoreClockUpdate();
Delay_Init(); Delay_Init();
#if (SDI_PRINT == SDI_PR_OPEN) #if (SDI_PRINT == SDI_PR_OPEN)
SDI_Printf_Enable(); SDI_Printf_Enable();
#else #else
USART_Printf_Init(115200); USART_Printf_Init(115200);
#endif #endif
printf("SystemClk: %ld\r\n", SystemCoreClock); printf("SystemClk: %ld\r\n", SystemCoreClock);
printf("DeviceID: %08lx\r\n", DBGMCU_GetDEVID()); printf("DeviceID: %08lx\r\n", DBGMCU_GetDEVID());
printf("ChipID: %08lx\r\n", DBGMCU_GetCHIPID()); printf("ChipID: %08lx\r\n", DBGMCU_GetCHIPID());
GPIO_LED_Init(); GPIO_LED_Init();
while(1) while(1)
{ {
Delay_Ms(1000); Delay_Ms(1000);
printf("On\r\n"); printf("On\r\n");
GPIO_WriteBit(GPIOA, GPIO_Pin_0, Bit_SET); GPIO_WriteBit(GPIOA, GPIO_Pin_0, Bit_SET);
Delay_Ms(1000); Delay_Ms(1000);
printf("Off\r\n"); printf("Off\r\n");
GPIO_WriteBit(GPIOA, GPIO_Pin_0, Bit_RESET); GPIO_WriteBit(GPIOA, GPIO_Pin_0, Bit_RESET);
} }
} }

482
User/system_ch32x035.c
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@ -1,241 +1,241 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32x035.c * File Name : system_ch32x035.c
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : CH32X035 Device Peripheral Access Layer System Source File. * Description : CH32X035 Device Peripheral Access Layer System Source File.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#include "ch32x035.h" #include "ch32x035.h"
/* /*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source). * reset the HSI is used as SYSCLK source).
*/ */
//#define SYSCLK_FREQ_8MHz_HSI 8000000 //#define SYSCLK_FREQ_8MHz_HSI 8000000
//#define SYSCLK_FREQ_12MHz_HSI 12000000 //#define SYSCLK_FREQ_12MHz_HSI 12000000
//#define SYSCLK_FREQ_16MHz_HSI 16000000 //#define SYSCLK_FREQ_16MHz_HSI 16000000
//#define SYSCLK_FREQ_24MHz_HSI 24000000 //#define SYSCLK_FREQ_24MHz_HSI 24000000
#define SYSCLK_FREQ_48MHz_HSI HSI_VALUE #define SYSCLK_FREQ_48MHz_HSI HSI_VALUE
/* Clock Definitions */ /* Clock Definitions */
#ifdef SYSCLK_FREQ_8MHz_HSI #ifdef SYSCLK_FREQ_8MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = SYSCLK_FREQ_8MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_12MHz_HSI #elif defined SYSCLK_FREQ_12MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_12MHz_HSI; /* System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = SYSCLK_FREQ_12MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_16MHz_HSI #elif defined SYSCLK_FREQ_16MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz_HSI; /* System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = SYSCLK_FREQ_16MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_24MHz_HSI #elif defined SYSCLK_FREQ_24MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz_HSI; /* System Clock Frequency (Core Clock) */
#else #else
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
#endif #endif
__I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8}; __I uint8_t AHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
/* system_private_function_proto_types */ /* system_private_function_proto_types */
static void SetSysClock(void); static void SetSysClock(void);
#ifdef SYSCLK_FREQ_8MHz_HSI #ifdef SYSCLK_FREQ_8MHz_HSI
static void SetSysClockTo8_HSI( void ); static void SetSysClockTo8_HSI( void );
#elif defined SYSCLK_FREQ_12MHz_HSI #elif defined SYSCLK_FREQ_12MHz_HSI
static void SetSysClockTo12_HSI( void ); static void SetSysClockTo12_HSI( void );
#elif defined SYSCLK_FREQ_16MHz_HSI #elif defined SYSCLK_FREQ_16MHz_HSI
static void SetSysClockTo16_HSI( void ); static void SetSysClockTo16_HSI( void );
#elif defined SYSCLK_FREQ_24MHz_HSI #elif defined SYSCLK_FREQ_24MHz_HSI
static void SetSysClockTo24_HSI( void ); static void SetSysClockTo24_HSI( void );
#elif defined SYSCLK_FREQ_48MHz_HSI #elif defined SYSCLK_FREQ_48MHz_HSI
static void SetSysClockTo48_HSI( void ); static void SetSysClockTo48_HSI( void );
#endif #endif
/********************************************************************* /*********************************************************************
* @fn SystemInit * @fn SystemInit
* *
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface, * @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
* update the SystemCoreClock variable. * update the SystemCoreClock variable.
* *
* @return none * @return none
*/ */
void SystemInit (void) void SystemInit (void)
{ {
RCC->CTLR |= (uint32_t)0x00000001; RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 |= (uint32_t)0x00000050; RCC->CFGR0 |= (uint32_t)0x00000050;
RCC->CFGR0 &= (uint32_t)0xF8FFFF5F; RCC->CFGR0 &= (uint32_t)0xF8FFFF5F;
SetSysClock(); SetSysClock();
} }
/********************************************************************* /*********************************************************************
* @fn SystemCoreClockUpdate * @fn SystemCoreClockUpdate
* *
* @brief Update SystemCoreClock variable according to Clock Register Values. * @brief Update SystemCoreClock variable according to Clock Register Values.
* *
* @return none * @return none
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate (void)
{ {
uint32_t tmp = 0; uint32_t tmp = 0;
SystemCoreClock = HSI_VALUE; SystemCoreClock = HSI_VALUE;
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8) if(((RCC->CFGR0 & RCC_HPRE) >> 4) < 8)
{ {
SystemCoreClock /= tmp; SystemCoreClock /= tmp;
} }
else else
{ {
SystemCoreClock >>= tmp; SystemCoreClock >>= tmp;
} }
} }
/********************************************************************* /*********************************************************************
* @fn SetSysClock * @fn SetSysClock
* *
* @brief Configures the System clock frequency, HCLK prescalers. * @brief Configures the System clock frequency, HCLK prescalers.
* *
* @return none * @return none
*/ */
static void SetSysClock(void) static void SetSysClock(void)
{ {
// GPIO_IPD_Unused(); // GPIO_IPD_Unused();
#ifdef SYSCLK_FREQ_8MHz_HSI #ifdef SYSCLK_FREQ_8MHz_HSI
SetSysClockTo8_HSI(); SetSysClockTo8_HSI();
#elif defined SYSCLK_FREQ_12MHz_HSI #elif defined SYSCLK_FREQ_12MHz_HSI
SetSysClockTo12_HSI(); SetSysClockTo12_HSI();
#elif defined SYSCLK_FREQ_16MHz_HSI #elif defined SYSCLK_FREQ_16MHz_HSI
SetSysClockTo16_HSI(); SetSysClockTo16_HSI();
#elif defined SYSCLK_FREQ_24MHz_HSI #elif defined SYSCLK_FREQ_24MHz_HSI
SetSysClockTo24_HSI(); SetSysClockTo24_HSI();
#elif defined SYSCLK_FREQ_48MHz_HSI #elif defined SYSCLK_FREQ_48MHz_HSI
SetSysClockTo48_HSI(); SetSysClockTo48_HSI();
#endif #endif
} }
#ifdef SYSCLK_FREQ_8MHz_HSI #ifdef SYSCLK_FREQ_8MHz_HSI
/********************************************************************* /*********************************************************************
* @fn SetSysClockTo8_HSI * @fn SetSysClockTo8_HSI
* *
* @brief Sets HSE as System clock source and configure HCLK prescalers. * @brief Sets HSE as System clock source and configure HCLK prescalers.
* *
* @return none * @return none
*/ */
static void SetSysClockTo8_HSI(void) static void SetSysClockTo8_HSI(void)
{ {
/* Flash 2 wait state */ /* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK = APB1 */ /* HCLK = SYSCLK = APB1 */
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV6; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV6;
/* Flash 0 wait state */ /* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
} }
#elif defined SYSCLK_FREQ_12MHz_HSI #elif defined SYSCLK_FREQ_12MHz_HSI
/********************************************************************* /*********************************************************************
* @fn SetSysClockTo12_HSI * @fn SetSysClockTo12_HSI
* *
* @brief Sets System clock frequency to 12MHz and configure HCLK prescalers. * @brief Sets System clock frequency to 12MHz and configure HCLK prescalers.
* *
* @return none * @return none
*/ */
static void SetSysClockTo12_HSI(void) static void SetSysClockTo12_HSI(void)
{ {
/* Flash 2 wait state */ /* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK = APB1 */ /* HCLK = SYSCLK = APB1 */
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV4; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV4;
/* Flash 0 wait state */ /* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
} }
#elif defined SYSCLK_FREQ_16MHz_HSI #elif defined SYSCLK_FREQ_16MHz_HSI
/********************************************************************* /*********************************************************************
* @fn SetSysClockTo16_HSI * @fn SetSysClockTo16_HSI
* *
* @brief Sets System clock frequency to 16MHz and configure HCLK prescalers. * @brief Sets System clock frequency to 16MHz and configure HCLK prescalers.
* *
* @return none * @return none
*/ */
static void SetSysClockTo16_HSI(void) static void SetSysClockTo16_HSI(void)
{ {
/* Flash 2 wait state */ /* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK = APB1 */ /* HCLK = SYSCLK = APB1 */
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV3;
/* Flash 0 wait state */ /* Flash 0 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
} }
#elif defined SYSCLK_FREQ_24MHz_HSI #elif defined SYSCLK_FREQ_24MHz_HSI
/********************************************************************* /*********************************************************************
* @fn SetSysClockTo24_HSI * @fn SetSysClockTo24_HSI
* *
* @brief Sets System clock frequency to 24MHz and configure HCLK prescalers. * @brief Sets System clock frequency to 24MHz and configure HCLK prescalers.
* *
* @return none * @return none
*/ */
static void SetSysClockTo24_HSI(void) static void SetSysClockTo24_HSI(void)
{ {
/* Flash 2 wait state */ /* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK = APB1 */ /* HCLK = SYSCLK = APB1 */
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
/* Flash 1 wait state */ /* Flash 1 wait state */
FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1; FLASH->ACTLR = (uint32_t)FLASH_ACTLR_LATENCY_1;
} }
#elif defined SYSCLK_FREQ_48MHz_HSI #elif defined SYSCLK_FREQ_48MHz_HSI
/********************************************************************* /*********************************************************************
* @fn SetSysClockTo48_HSI * @fn SetSysClockTo48_HSI
* *
* @brief Sets System clock frequency to 48MHz and configure HCLK prescalers. * @brief Sets System clock frequency to 48MHz and configure HCLK prescalers.
* *
* @return none * @return none
*/ */
static void SetSysClockTo48_HSI(void) static void SetSysClockTo48_HSI(void)
{ {
/* Flash 2 wait state */ /* Flash 2 wait state */
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
/* HCLK = SYSCLK = APB1 */ /* HCLK = SYSCLK = APB1 */
RCC->CFGR0 &= (uint32_t)0xFFFFFF0F; RCC->CFGR0 &= (uint32_t)0xFFFFFF0F;
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
} }
#endif #endif

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User/system_ch32x035.h
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@ -1,32 +1,32 @@
/********************************** (C) COPYRIGHT ******************************* /********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32x035.h * File Name : system_ch32x035.h
* Author : WCH * Author : WCH
* Version : V1.0.0 * Version : V1.0.0
* Date : 2023/04/06 * Date : 2023/04/06
* Description : CH32X035 Device Peripheral Access Layer System Header File. * Description : CH32X035 Device Peripheral Access Layer System Header File.
********************************************************************************* *********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for * Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics. * microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/ *******************************************************************************/
#ifndef __SYSTEM_CH32X035_H #ifndef __SYSTEM_CH32X035_H
#define __SYSTEM_CH32X035_H #define __SYSTEM_CH32X035_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/* System_Exported_Functions */ /* System_Exported_Functions */
extern void SystemInit(void); extern void SystemInit(void);
extern void SystemCoreClockUpdate(void); extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif #endif