Quantum
b35d58df1f
Split code into generic, arch, and platform Made QEMU its own platform Added shitty uart upload script for lichee board until I can get fel to actually upload uboot payloads without hanging TODO: Move platform selection out of build script TODO: Move arch specific stuff from kernel to arch TODO: Common linker script for arch instead of having a copy in each platform
351 lines
7.2 KiB
C++
351 lines
7.2 KiB
C++
#include <stdarg.h>
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#include <inttypes.h>
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#define read_csr(csr) \
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({ \
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unsigned long __v; \
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asm volatile ("csrr %0, " csr : "=r"(__v) : : "memory");\
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__v;\
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})
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#define write_csr(csr, v) \
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({ \
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unsigned long __v = (v); \
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asm volatile ("csrw " csr ", %0" : : "r"(__v) : "memory");\
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})
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#define set_csr_bits(csr, bits) \
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({ \
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unsigned long __v = (bits); \
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asm volatile ("csrs " csr ", %0" : : "r"(__v) : "memory");\
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})
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#define clear_csr_bits(csr, bits) \
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({ \
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unsigned long __v = (bits); \
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asm volatile ("csrc " csr ", %0" : : "r"(__v) : "memory");\
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})
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typedef unsigned long sbi_word;
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void sbi_call1(int ext, int func, sbi_word arg0) {
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register sbi_word rExt asm("a7") = ext;
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register sbi_word rFunc asm("a6") = func;
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register sbi_word rArg0 asm("a0") = arg0;
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register sbi_word rArg1 asm("a1");
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asm volatile("ecall" : "+r"(rArg0), "=r"(rArg1) : "r"(rExt), "r"(rFunc));
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if(rArg0)
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__builtin_trap();
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}
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void sbi_call2(int ext, int func, sbi_word arg0, sbi_word arg1) {
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register sbi_word rExt asm("a7") = ext;
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register sbi_word rFunc asm("a6") = func;
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register sbi_word rArg0 asm("a0") = arg0;
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register sbi_word rArg1 asm("a1") = arg1;
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asm volatile("ecall" : "+r"(rArg0), "+r"(rArg1) : "r"(rExt), "r"(rFunc));
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if(rArg0)
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__builtin_trap();
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}
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void fmt(const char *f, ...) {
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va_list va;
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va_start(va, f);
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while(*f) {
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if(*f != '{') {
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sbi_call1(1, 0, *(f++));
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continue;
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}
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f++;
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while(*f != '}') {
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if(!(*f))
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return;
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f++;
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}
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f++;
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unsigned long v = va_arg(va, unsigned long);
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for(int i = 0; i < 16; ++i) {
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const char *digits = "0123456789abcdef";
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int d = (v >> (60 - i * 4)) & 0xF;
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sbi_call1(1, 0, digits[d]);
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}
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}
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va_end(va);
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}
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enum {
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pte_valid = 1 << 0,
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pte_r = 1 << 1,
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pte_w = 1 << 2,
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pte_x = 1 << 3,
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pte_user = 1 << 4,
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pte_access = 1 << 6,
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pte_dirty = 1 << 7,
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};
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enum {
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pte_ppn_shift = 10
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};
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struct pt_t {
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unsigned long ptes[512];
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} __attribute__((aligned(4096)));
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enum {
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satp_sv48 = 9UL << 60
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};
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const char *exception_strings[] = {
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"instruction misaligned",
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"instruction access fault",
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"illegal instruction",
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"breakpoint",
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"load misaligned",
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"load access fault",
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"store misaligned",
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"store access fault",
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"u-mode ecall",
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"s-mode ecall",
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"reserved (10)",
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"reserved (11)",
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"instruction page fault",
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"load page fault",
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"reserved (14)",
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"store page fault",
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};
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enum {
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sie_s_software = (1 << 1),
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sie_s_timer = (1 << 5)
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};
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enum {
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sstatus_sie = (1 << 1)
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};
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void cli() {
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clear_csr_bits("sstatus", sstatus_sie);
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}
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void sti() {
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set_csr_bits("sstatus", sstatus_sie);
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}
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typedef struct {
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void *sp;
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} continuation_t;
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struct task_t;
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struct isr_frame_t {
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task_t *task;
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isr_frame_t *next;
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unsigned long ra; // Offset 0x10.
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unsigned long a[8]; // Offset 0x18.
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unsigned long t[7]; // Offset 0x58.
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unsigned long s1; // Offset 0x90.
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unsigned long sstatus; // Offset 0x98.
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unsigned long sepc; // Offset 0xA0.
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};
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enum {
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kernel_stack_size = 0x10000
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};
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struct task_t {
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continuation_t cont;
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isr_frame_t isr_frames[2];
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isr_frame_t *next_isr;
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char kernel_stack[kernel_stack_size];
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};
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task_t task1;
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task_t task2;
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task_t *current_task;
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continuation_t prepare_stack(void *s_top, void (*mainfn)(continuation_t)) {
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void *sp = (void *)((uintptr_t)s_top - 0x78);
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*((uint64_t *)((uintptr_t)sp + 0x70)) = (uint64_t)mainfn;
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return (continuation_t){.sp = sp};
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}
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extern "C" void save_stack(void (*f)(void *, continuation_t), void *ctx);
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extern "C" void restore_stack(continuation_t c);
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void create_task(task_t *task, void (*mainfn)(continuation_t)) {
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task->isr_frames[0].task = task;
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task->isr_frames[1].task = task;
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task->isr_frames[0].next = &task->isr_frames[1];
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task->isr_frames[1].next = 0;
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task->next_isr = &task->isr_frames[0];
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task->cont = prepare_stack((void *)(task->kernel_stack + kernel_stack_size), mainfn);
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}
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void switch_task(void *ctx, continuation_t c) {
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task_t *task = (task_t *)ctx;
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if(task) {
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task->next_isr = (isr_frame_t *)read_csr("sscratch");
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task->cont = c;
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}
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task_t *next;
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if(task == &task1) {
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next = &task2;
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}else{
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next = &task1;
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}
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current_task = next;
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write_csr("sscratch", (unsigned long)next->next_isr);
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restore_stack(next->cont);
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}
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extern "C" void isr();
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extern "C" void handle_isr(isr_frame_t *frame) {
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unsigned long cause = read_csr("scause");
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unsigned long code = cause & ~(1UL << 63);
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if(cause & (1UL << 63)) {
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if(code == 1) {
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fmt("it's an IPI\n");
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clear_csr_bits("sip", sie_s_software);
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}else if(code == 5) { // Timer interrupt.
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//clear_csr_bits("sie", sie_s_timer);
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unsigned long time = read_csr("time");
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sbi_call1(0x54494D45, 0, time + 100000);
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save_stack(switch_task, current_task);
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}else{
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fmt("it's an unhandled interrupt, code: {}\n", code);
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}
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}else{
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if(code == 8) { // Syscall.
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sbi_call1(1, 0, frame->a[0]);
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}else{
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unsigned long sepc = read_csr("sepc");
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fmt("it's an exception at {}\n", sepc);
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const char *s = exception_strings[cause];
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while(*s)
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sbi_call1(1, 0, *(s++));
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while(1)
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;
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}
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}
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}
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extern "C" void isr_frame_overflow() {
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fmt("isr frame overflow\n");
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while(1)
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;
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}
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pt_t pml4;
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extern "C" void enter_umode(void *entry);
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void syscall(int n, unsigned long arg0) {
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register sbi_word rArg0 asm("a0") = arg0;
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register sbi_word rN asm("a7") = n;
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asm volatile("ecall" : "+r"(rArg0) : "r"(rN) : "memory");
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if(rArg0)
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__builtin_trap();
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}
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void task1_umode() {
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while(1)
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syscall(0, '!');
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}
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void task1_main(continuation_t c) {
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fmt("hello from task1\n");
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sti();
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//syscall(0, '!');
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//enter_umode((void *)task1_umode);
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}
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void task2_main(continuation_t c) {
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fmt("hello from task2\n");
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sti();
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//while(1)
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//fmt(".");
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}
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isr_frame_t global_isr_frames[2];
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extern "C" void kmain(unsigned long hart, void *dtb) {
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(void)hart;
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(void)dtb;
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//fmt("test\n");
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/*
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volatile uint32_t *cfg = (uint32_t *)0x2000060;
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volatile uint32_t *dat = (uint32_t *)0x2000070;
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*cfg = 0x10;
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*dat = 0xFF;
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*/
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fmt("y");
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cli();
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global_isr_frames[0].next = &global_isr_frames[1];
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write_csr("sscratch", (unsigned long)&global_isr_frames[0]);
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write_csr("stvec", ((unsigned long)&isr));
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const char *s;
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set_csr_bits("sie", sie_s_software | sie_s_timer);
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// Self-IPI.
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sbi_call2(0x735049, 0, 1 << hart, 0);
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sti();
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cli();
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unsigned long time;
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//volatile uint32_t *meme = (uint32_t *)0x6011010;
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//while(true) {
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time = read_csr("time");
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fmt("hello world {}\n", time);
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//*meme = *meme | (0xA57 << 1) | (1 << 0);
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//}
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// Identity map the first 512GiB.
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pml4.ptes[0] = ((0UL >> 12) << pte_ppn_shift) | pte_valid
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| pte_r | pte_w | pte_x | pte_access | pte_dirty | pte_user;
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// Map 512GiB -> 0.
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pml4.ptes[1] = ((0UL >> 12) << pte_ppn_shift) | pte_valid
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| pte_r | pte_w | pte_x | pte_access | pte_dirty | pte_user;
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fmt("Writing paging memes\n");
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unsigned long pml4p = (unsigned long)&pml4;
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fmt("pml4p @ {}\n", pml4p);
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fmt("Setting SStatus\n");
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set_csr_bits("sstatus", 1 << 18);
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fmt("Setting Satp\n");
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write_csr("satp", (pml4p >> 12) | satp_sv48);
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fmt("Paging might work?...\n");
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s = "paging works!\n";
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s += 512UL * 1024 * 1024 * 1024;
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while(*s)
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sbi_call1(1, 0, *(s++));
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create_task(&task1, task1_main);
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create_task(&task2, task2_main);
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time = read_csr("time");
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sbi_call1(0x54494D45, 0, time + 100000);
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save_stack(switch_task, 0);
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sbi_call1(8, 0, 0);
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while(1);
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}
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