2024-03-08 23:10:08 -05:00
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---------------
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-- Opcodes --
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---------------
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Argless
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NOP
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HLT
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RST
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Idfk
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DBG
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Memory ops
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MOV
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PUSH
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POP
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Branches
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JMPA
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JMP
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JZ
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ALU stuff
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CMP
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INC
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DEC
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------------------------
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-- Addressing Modes --
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------------------------
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reg - Register
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imm - Immediate
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abs - Absolute
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ida - Indirect absolute
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idr - Indirect register
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---- Examples ----
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Assembly -- Mode -- Function
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---------------------------------------------------------
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mov A, 5 -- reg imm -- A <- 5
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mov [$23], 5 -- ida imm -- mem[mem[23]] <- 5
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mov $69, A -- abs imm -- mem[69] <- A
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mov 420, [A] -- imm idr -- mem[ip + 1] <- mem[A]
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add $13, $32 -- ida ida -- mem[13] <- mem[13] + mem[32]
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inc A, 14 -- reg imm -- A <- A + 1 | Z <- (A == 14) # Cursed zero flag
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2024-03-08 23:24:34 -05:00
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---------------
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-- Signals --
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---------------
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IR_W -- level -- D_BUS -> IR
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LATCH_PC -- edge -- PC_MUX -> PC, PC_MUX is either PC++ or from branch logic, see SEL_PC_LOAD
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SEL_PC_LOAD -- mux -- Selects between PC++ or branch logic, feeds PC register
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PC_BUF -- level -- PC -> A_BUS
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MAR_W -- level -- A_BUS -> MEM_A
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MBR_W -- level -- MEM_D -> D_BUS or D_BUS -> MEM_D depending on MBR_W
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2024-03-08 23:56:29 -05:00
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MBR_BUF -- level -- MBR -> D_BUS
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2024-03-08 23:24:34 -05:00
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MEM_R -- level -- Put mem[MEM_A] on MEM_D
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IN_SEL -- bus -- Selects register to write to
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A_SEL -- bus -- Selects "A"(first operand) register
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B_SEL -- bus -- Selects "B"(second operand) register
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REG_WR -- edge -- regs[IN_SEL] <- REG_D_IN
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REG_A_RD -- level -- A_OUT <- regs[A_SEL]
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REG_B_RD -- level -- B_OUT <- regs[B_SEL]
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2024-03-08 23:56:29 -05:00
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-----------------
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-- Sequences --
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-----------------
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---- Ring Clock ----
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Clk | |#| |#| |#| |#| |#|...
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PH_0 |###| | | | | | | | |...
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PH_1 | | |###| | | | | | |...
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PH_2 | | | | |###| | | | |...
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PH_3 | | | | | | |###| | |...
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PH_4 | | | | | | | | |###|...
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PH_n | | | | | | | | | | |...
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Clk is actually the inverse of the real "clock", on the rising edge the phase changes, then on the falling edge Clk goes high
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*MOST* registers are fed by Clk and enabled by one of the phases
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---- Template ----
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Clk | |#| |#| |#| |#| |#|
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Phase |PH0|PH1|PH2|PH3|PH4|
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IR_W | | | | | | | | | | |
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LATCH_PC | | | | | | | | | | |
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SEL_PC_LOAD | | | | | | | | | | |
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PC_BUF | | | | | | | | | | |
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MAR_W | | | | | | | | | | |
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MBR_W | | | | | | | | | | |
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MBR_BUF | | | | | | | | | | |
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MEM_R | | | | | | | | | | |
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IN_SEL | | | | | | | | | | |
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A_SEL | | | | | | | | | | |
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B_SEL | | | | | | | | | | |
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REG_WR | | | | | | | | | | |
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REG_A_RD | | | | | | | | | | |
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REG_B_RD | | | | | | | | | | |
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---- Instruction Fetch ----
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Clk | |#| |#|
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Phase |PH0|PH1|
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PC_BUF |###| | |
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MAR_W |###| | |
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LATCH_PC | | |###|
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MEM_R | | |###|
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MBR_W | | |###|
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MBR_BUF | | |###|
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IR_W | | |###|
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2024-03-09 00:00:38 -05:00
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--
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In phase 0 we need to write PC to MAR via the A_BUS
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In phase 1 we need to increment PC and write the data at mem[MAR] to both MBR and IR
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Honestly since the opcode is just the opcode and nothing else we might be able to skip the MBR step here
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2024-03-08 23:56:29 -05:00
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--
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Ph 0
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----
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PC -> A_BUS via PC_BUF(l)
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2024-03-09 00:00:38 -05:00
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A_BUS -> MAR via MAR_W(c)
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2024-03-08 23:56:29 -05:00
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Ph 1
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----
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PC + 1 -> PC via LATCH_PC(^) (SEL_PC_LOAD is 0)
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MEM -> MEM_D via MEM_R(l)
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MEM_D -> MBR via MBR_W(c)
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MBR -> MEM_D via MBR_BUF(l)
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MEM_D -> IR via IR_W(l)
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