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Added notes to fetch sequence

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Thomas Muller 2024-03-09 00:00:38 -05:00
parent d2fb5af35f
commit 473c49b2e8
1 changed files with 5 additions and 1 deletions
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@ -115,12 +115,16 @@ MBR_W | | |###|
MBR_BUF | | |###|
IR_W | | |###|
--
In phase 0 we need to write PC to MAR via the A_BUS
In phase 1 we need to increment PC and write the data at mem[MAR] to both MBR and IR
Honestly since the opcode is just the opcode and nothing else we might be able to skip the MBR step here
--
Ph 0
----
PC -> A_BUS via PC_BUF(l)
A_BUS -> MEM_A via MAR_W(c)
A_BUS -> MAR via MAR_W(c)
Ph 1
----