From 73587036c7cbb91690823ad7e7a11e66b1f07808 Mon Sep 17 00:00:00 2001 From: Quantum Date: Fri, 8 Mar 2024 23:24:34 -0500 Subject: [PATCH] Added signals --- notes | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/notes b/notes index da6cd1a..f2e5551 100644 --- a/notes +++ b/notes @@ -46,3 +46,22 @@ mov 420, [A] -- imm idr -- mem[ip + 1] <- mem[A] add $13, $32 -- ida ida -- mem[13] <- mem[13] + mem[32] inc A, 14 -- reg imm -- A <- A + 1 | Z <- (A == 14) # Cursed zero flag + + +--------------- +-- Signals -- +--------------- + +IR_W -- level -- D_BUS -> IR +LATCH_PC -- edge -- PC_MUX -> PC, PC_MUX is either PC++ or from branch logic, see SEL_PC_LOAD +SEL_PC_LOAD -- mux -- Selects between PC++ or branch logic, feeds PC register +PC_BUF -- level -- PC -> A_BUS +MAR_W -- level -- A_BUS -> MEM_A +MBR_W -- level -- MEM_D -> D_BUS or D_BUS -> MEM_D depending on MBR_W +MEM_R -- level -- Put mem[MEM_A] on MEM_D +IN_SEL -- bus -- Selects register to write to +A_SEL -- bus -- Selects "A"(first operand) register +B_SEL -- bus -- Selects "B"(second operand) register +REG_WR -- edge -- regs[IN_SEL] <- REG_D_IN +REG_A_RD -- level -- A_OUT <- regs[A_SEL] +REG_B_RD -- level -- B_OUT <- regs[B_SEL]