---------------
--  Opcodes  --
---------------

Argless
NOP
HLT
RST

Idfk
DBG

Memory ops
MOV
PUSH
POP

Branches
JMPA
JMP
JZ

ALU stuff
CMP
INC
DEC


------------------------
--  Addressing Modes  --
------------------------
reg - Register
imm - Immediate
abs - Absolute
ida - Indirect absolute
idr - Indirect register

----  Examples  ----

Assembly        --  Mode     --  Function
---------------------------------------------------------
mov A, 5        --  reg imm  --  A <- 5
mov [$23], 5    --  ida imm  --  mem[mem[23]] <- 5
mov $69, A      --  abs imm  --  mem[69] <- A
mov 420, [A]    --  imm idr  --  mem[ip + 1] <- mem[A]
add $13, $32    --  ida ida  --  mem[13] <- mem[13] + mem[32]
inc A, 14       --  reg imm  --  A <- A + 1  |  Z <- (A == 14)   # Cursed zero flag



---------------
--  Signals  --
---------------

IR_W        --  level  --  D_BUS -> IR
LATCH_PC    --  edge   --  PC_MUX -> PC, PC_MUX is either PC++ or from branch logic, see SEL_PC_LOAD
SEL_PC_LOAD --  mux    --  Selects between PC++ or branch logic, feeds PC register
PC_BUF      --  level  --  PC -> A_BUS
MAR_W       --  level  --  A_BUS -> MEM_A
MBR_W       --  level  --  MEM_D -> D_BUS or D_BUS -> MEM_D depending on MBR_W
MEM_R       --  level  --  Put mem[MEM_A] on MEM_D
IN_SEL      --  bus    --  Selects register to write to
A_SEL       --  bus    --  Selects "A"(first operand) register
B_SEL       --  bus    --  Selects "B"(second operand) register
REG_WR      --  edge   --  regs[IN_SEL] <- REG_D_IN
REG_A_RD    --  level  --  A_OUT <- regs[A_SEL]
REG_B_RD    --  level  --  B_OUT <- regs[B_SEL]