134 lines
3.9 KiB
C
134 lines
3.9 KiB
C
#include "ws2812.h"
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#include "ch32v20x.h"
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u8 colors[12*3] = {
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255, 0, 0,
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0, 255, 0,
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0, 0, 255,
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255, 255, 0,
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255, 0, 255,
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0, 255,255,
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255, 0, 0,
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0, 255, 0,
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0, 0, 255,
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255, 255, 0,
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255, 0, 255,
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0, 255,255
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};
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u8 pbuf[12*3*8]; // = {15, 30, 30, 15, 22, 22, 0, 0, 45, 45, 22, 22};
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void fuckballs() {
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u32 idx = 0;
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for (int i = 0; i < 12 * 3; i++)
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{
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for(int j = 0; j < 4; j++) {
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if (colors[i] & (1 << j)) {
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pbuf[idx++] = 29;
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} else {
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pbuf[idx++] = 14;
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}
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}
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}
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}
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void ws2812_init() {
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fuckballs();
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// Enable TIM1 and GPIOA
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RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1 | RCC_APB2Periph_GPIOA, ENABLE);
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// TIM1_CH1 - PA8
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GPIO_InitTypeDef gpio_init;
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gpio_init.GPIO_Mode = GPIO_Mode_AF_PP;
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gpio_init.GPIO_Speed = GPIO_Speed_50MHz;
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gpio_init.GPIO_Pin = GPIO_Pin_8;
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GPIO_Init(GPIOA, &gpio_init);
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// GPIO_SetBits(GPIOA, GPIO_Pin_8);
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TIM_TimeBaseInitTypeDef timebase_init;
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TIM_TimeBaseStructInit(&timebase_init);
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timebase_init.TIM_Prescaler = 0;
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timebase_init.TIM_Period = 43; // 0 - 45 where 45 is 36MHz / 45 = 800kHz
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timebase_init.TIM_ClockDivision = TIM_CKD_DIV1;
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timebase_init.TIM_CounterMode = TIM_CounterMode_Up;
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timebase_init.TIM_RepetitionCounter = 0x0000;
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TIM_TimeBaseInit(TIM1, &timebase_init);
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// Reload the CNT register with period?
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TIM_ARRPreloadConfig(TIM1, ENABLE);
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TIM_OCInitTypeDef oc_init;
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TIM_OCStructInit(&oc_init);
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oc_init.TIM_OCMode = TIM_OCMode_PWM2;
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oc_init.TIM_OutputState = TIM_OutputState_Enable;
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oc_init.TIM_OutputNState = TIM_OutputNState_Disable;
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oc_init.TIM_Pulse = 0;
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oc_init.TIM_OCPolarity = TIM_OCPolarity_High;
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oc_init.TIM_OCNPolarity = TIM_OCPolarity_Low;
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oc_init.TIM_OCIdleState = TIM_OCIdleState_Reset;
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oc_init.TIM_OCNIdleState = TIM_OCNIdleState_Reset;
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TIM_OC1Init(TIM1, &oc_init);
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TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Disable);
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// TIM_OC1FastConfig(TIM1, ENABLE);
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// TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
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// TIM_CtrlPWMOutputs(TIM1, ENABLE);
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// TIM_Cmd(TIM1, ENABLE);
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RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
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DMA_InitTypeDef dma_init;
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DMA_StructInit(&dma_init);
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dma_init.DMA_PeripheralBaseAddr = (u32)(&(TIM1->CH1CVR));
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dma_init.DMA_MemoryBaseAddr = (u32)&pbuf[0];
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dma_init.DMA_DIR = DMA_DIR_PeripheralDST;
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dma_init.DMA_BufferSize = 12;
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dma_init.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
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dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
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dma_init.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord;
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dma_init.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
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dma_init.DMA_Mode = DMA_Mode_Normal;
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dma_init.DMA_Priority = DMA_Priority_VeryHigh;
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dma_init.DMA_M2M = DMA_M2M_Disable;
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DMA_Init(DMA1_Channel5, &dma_init);
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DMA_Cmd(DMA1_Channel5, ENABLE);
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TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
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TIM_CtrlPWMOutputs(TIM1, ENABLE);
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TIM_Cmd(TIM1, ENABLE);
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// TIM_SetCompare1(TIM1, 14);
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// TIM_Cmd(TIM1, ENABLE);
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// DMA_Cmd(DMA1_Channel5, DISABLE);
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while(1) {
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// DMA_ClearFlag(DMA1_FLAG_HT5);
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// DMA_ClearFlag(DMA1_FLAG_TC5);
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// DMA_Cmd(DMA1_Channel5, ENABLE);
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// TIM_Cmd(TIM1, ENABLE);
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DMA_Cmd(DMA1_Channel5, DISABLE);
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TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Disable);
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TIM_Cmd(TIM1, DISABLE);
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// TIM_DMACmd(TIM1, TIM_DMA_Update, DISABLE);
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Delay_Ms(100);
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// DMA_Cmd(DMA1_Channel5, ENABLE);
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// TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
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// TIM_Cmd(TIM1, ENABLE);
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// TIM_DMACmd(TIM1, TIM_DMA_Update, ENABLE);
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DMA_ClearFlag(DMA1_FLAG_TC5);
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// DMA_ClearFlag(DMA1_FLAG_HT5);
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DMA_SetCurrDataCounter(DMA1_Channel5, 12*3*8);
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DMA_Cmd(DMA1_Channel5, ENABLE);
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TIM_SetCounter(TIM1, 0);
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TIM_Cmd(TIM1, ENABLE);
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TIM_CCxCmd(TIM1, TIM_Channel_1, TIM_CCx_Enable);
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// Delay_Ms(100);
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while(!DMA_GetITStatus(DMA1_IT_TC5));
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// Delay_Ms(10);
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}
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}
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