The original march option was wrong (RV32E). According to WCH, the instruction
set is RV32IMAC. Updating the GCC version broke a ton of things since it
better complied with stack alignment requirements that RV32E had, which
RV32I was not compatible with.
Additionally, newer versions of the RISC-V ISA spec split off the Zicsr and
Zifencei instruction from RV32I. GCC versions 12 and newer began using
this spec, leading to missing opcode errors.
Lastly, "--specs=nosys.specs" and "--specs=nano.specs" allegedly don't
go together, and nano is apparently preferred.
Also "-mcmodel=medany" is needed apparently.
See https://gcc.gnu.org/onlinedocs/gcc/RISC-V-Options.html#index-mcmodel_003dmedany
